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ef582182 | 1 | @c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
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2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node M32R-Dependent | |
7 | @chapter M32R Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter M32R Dependent Features | |
12 | @end ifclear | |
13 | ||
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14 | @c start-sanitize-m32rx |
15 | ||
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16 | @cindex M32R support |
17 | @menu | |
18 | * M32R-Opts:: M32R Options | |
ef582182 | 19 | * M32R-Warnings:: M32R Warnings |
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20 | @end menu |
21 | ||
22 | @node M32R-Opts | |
23 | @section M32R Options | |
24 | ||
25 | @cindex options, M32R | |
26 | @cindex M32R options | |
ef582182 | 27 | |
ee73be40 | 28 | The Mitsubishi M32R version of @code{@value{AS}} has a few machine |
ef582182 | 29 | dependent options: |
ee73be40 | 30 | |
ef582182 | 31 | @table @code |
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32 | @item -m32rx |
33 | @cindex @samp{-m32rx} option, M32RX | |
ef582182 | 34 | @cindex architecture options, M32RX |
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35 | @cindex M32R architecture options |
36 | @code{@value{AS}} can assemble code for several different members of the | |
37 | Mitsubishi M32R family. Normally the default is to assemble code for | |
38 | the M32R microprocessor. This option may be used to change the default | |
39 | to the M32RX microprocessor, which adds some more instructions to the | |
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40 | basic M32R instruction set, and some additional parameters to some of |
41 | the original instructions. | |
42 | ||
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43 | @item -warn-explicit-parallel-conflicts |
44 | @cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX | |
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45 | Instructs @code{@value{AS}} to produce warning messages when |
46 | questionable parallel instructions are encountered. This option is | |
47 | enabled by default, but @code{@value{GCC}} disables it when it invokes | |
48 | @code{@value{AS}} directly. Questionable instructions are those whoes | |
49 | behaviour would be different if they were executed sequentially. For | |
50 | example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a | |
51 | different result from @samp{mv r1, r2 \n mv r3, r1} since the former | |
52 | moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 | |
53 | and r3. | |
54 | ||
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55 | @item -Wp |
56 | @cindex @samp{-Wp} option, M32RX | |
57 | This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} | |
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58 | option. |
59 | ||
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60 | @item -no-warn-explicit-parallel-conflicts |
61 | @cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX | |
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62 | Instructs @code{@value{AS}} not to produce warning messages when |
63 | questionable parallel instructions are encountered. | |
64 | ||
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65 | @item -Wnp |
66 | @cindex @samp{-Wnp} option, M32RX | |
67 | This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} | |
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68 | option. |
69 | ||
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70 | @end table |
71 | ||
72 | @node M32R-Warnings | |
73 | @section M32R Warnings | |
74 | ||
75 | @cindex warnings, M32R | |
76 | @cindex M32R warnings | |
77 | ||
78 | There are several warning and error messages that can be produced by | |
79 | @code{@value{AS}} which are specific to the M32R: | |
80 | ||
81 | @table @code | |
82 | ||
8e7a5a04 | 83 | @item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? |
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84 | This message is only produced if warnings for explicit parallel |
85 | conflicts have been enabled. It indicates that the assembler has | |
86 | encountered a parallel instruction in which the destination register of | |
87 | the left hand instruction is used as an input register in the right hand | |
88 | instruction. For example in this code fragment | |
89 | @samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the | |
90 | move instruction and the input to the neg instruction. | |
91 | ||
8e7a5a04 | 92 | @item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? |
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93 | This message is only produced if warnings for explicit parallel |
94 | conflicts have been enabled. It indicates that the assembler has | |
95 | encountered a parallel instruction in which the destination register of | |
96 | the right hand instruction is used as an input register in the left hand | |
97 | instruction. For example in this code fragment | |
98 | @samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the | |
99 | neg instruction and the input to the move instruction. | |
100 | ||
101 | @item instruction @samp{...} is for the M32RX only | |
102 | This message is produced when the assembler encounters an instruction | |
26be2423 | 103 | which is only supported by the M32Rx processor, and the @samp{-m32rx} |
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104 | command line flag has not been specified to allow assembly of such |
105 | instructions. | |
106 | ||
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107 | @item unknown instruction @samp{...} |
108 | This message is produced when the assembler encounters an instruction | |
109 | which it doe snot recognise. | |
110 | ||
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111 | @item only the NOP instruction can be issued in parallel on the m32r |
112 | This message is produced when the assembler encounters a parallel | |
113 | instruction which does not involve a NOP instruction and the | |
26be2423 | 114 | @samp{-m32rx} command line flag has not been specified. Only the M32Rx |
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115 | processor is able to execute two instructions in parallel. |
116 | ||
117 | @item instruction @samp{...} cannot be executed in parallel. | |
118 | This message is produced when the assembler encounters a parallel | |
119 | instruction which is made up of one or two instructions which cannot be | |
120 | executed in parallel. | |
121 | ||
122 | @item Instructions share the same execution pipeline | |
123 | This message is produced when the assembler encounters a parallel | |
124 | instruction whoes components both use the same execution pipeline. | |
125 | ||
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126 | @item Instructions write to the same destination register. |
127 | This message is produced when the assembler encounters a parallel | |
128 | instruction where both components attempt to modify the same register. | |
8e7a5a04 | 129 | For example these code fragments will produce this message: |
ef582182 | 130 | @samp{mv r1, r2 || neg r1, r3} |
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131 | @samp{jl r0 || mv r14, r1} |
132 | @samp{st r2, @@-r1 || mv r1, r3} | |
133 | @samp{mv r1, r2 || ld r0, @@r1+} | |
32c2be76 | 134 | @samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) |
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136 | @end table |
137 | @c end-sanitize-m32rx |