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9f7598c1 | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2003 |
f7e42eb4 | 2 | @c Free Software Foundation, Inc. |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @ifset GENERIC | |
6 | @page | |
7 | @node M32R-Dependent | |
8 | @chapter M32R Dependent Features | |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter M32R Dependent Features | |
13 | @end ifclear | |
14 | ||
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15 | @cindex M32R support |
16 | @menu | |
17 | * M32R-Opts:: M32R Options | |
9f7598c1 | 18 | * M32R-Directives:: M32R Directives |
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19 | * M32R-Warnings:: M32R Warnings |
20 | @end menu | |
21 | ||
22 | @node M32R-Opts | |
23 | @section M32R Options | |
24 | ||
25 | @cindex options, M32R | |
26 | @cindex M32R options | |
27 | ||
26597c86 | 28 | The Renease M32R version of @code{@value{AS}} has a few machine |
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29 | dependent options: |
30 | ||
31 | @table @code | |
88845958 | 32 | |
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33 | @item -m32rx |
34 | @cindex @samp{-m32rx} option, M32RX | |
35 | @cindex architecture options, M32RX | |
36 | @cindex M32R architecture options | |
37 | @code{@value{AS}} can assemble code for several different members of the | |
26597c86 | 38 | Renesas M32R family. Normally the default is to assemble code for |
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39 | the M32R microprocessor. This option may be used to change the default |
40 | to the M32RX microprocessor, which adds some more instructions to the | |
41 | basic M32R instruction set, and some additional parameters to some of | |
42 | the original instructions. | |
43 | ||
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44 | @item -m32r2 |
45 | @cindex @samp{-m32rx} option, M32R2 | |
46 | @cindex architecture options, M32R2 | |
47 | @cindex M32R architecture options | |
48 | This option changes the target processor to the the M32R2 | |
49 | microprocessor. | |
50 | ||
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51 | @item -m32r |
52 | @cindex @samp{-m32r} option, M32R | |
53 | @cindex architecture options, M32R | |
54 | @cindex M32R architecture options | |
55 | This option can be used to restore the assembler's default behaviour of | |
56 | assembling for the M32R microprocessor. This can be useful if the | |
57 | default has been changed by a previous command line option. | |
58 | ||
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59 | @item -little |
60 | @cindex @code{-little} option, M32R | |
61 | This option tells the assembler to produce little-endian code and | |
62 | data. The default is dependent upon how the toolchain was | |
63 | configured. | |
64 | ||
65 | @item -EL | |
66 | @cindex @code{-EL} option, M32R | |
67 | This is a synonum for @emph{-little}. | |
68 | ||
69 | @item -big | |
70 | @cindex @code{-big} option, M32R | |
71 | This option tells the assembler to produce big-endian code and | |
72 | data. | |
73 | ||
74 | @item -EB | |
75 | @cindex @code{-EB} option, M32R | |
76 | This is a synonum for @emph{-big}. | |
77 | ||
78 | @item -parallel | |
79 | @cindex @code{-parallel} option, M32RX | |
80 | This option tells the assembler to attempts to combine two sequential | |
81 | instructions into a single, parallel instruction, where it is legal to | |
82 | do so. | |
83 | ||
84 | @item -no-parallel | |
85 | @cindex @code{-no-parallel} option, M32RX | |
86 | This option disables a previously enabled @emph{-parallel} option. | |
87 | ||
88 | @item -O | |
89 | @cindex @code{-O} option, M32RX | |
90 | This option tells the assembler to attempt to optimize the | |
91 | instructions that it produces. This includes filling delay slots and | |
92 | converting sequential instructions into parallel ones. This option | |
93 | implies @emph{-parallel}. | |
94 | ||
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95 | @item -warn-explicit-parallel-conflicts |
96 | @cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX | |
97 | Instructs @code{@value{AS}} to produce warning messages when | |
98 | questionable parallel instructions are encountered. This option is | |
99 | enabled by default, but @code{@value{GCC}} disables it when it invokes | |
100 | @code{@value{AS}} directly. Questionable instructions are those whoes | |
101 | behaviour would be different if they were executed sequentially. For | |
102 | example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a | |
103 | different result from @samp{mv r1, r2 \n mv r3, r1} since the former | |
104 | moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 | |
105 | and r3. | |
106 | ||
107 | @item -Wp | |
108 | @cindex @samp{-Wp} option, M32RX | |
109 | This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} | |
110 | option. | |
111 | ||
112 | @item -no-warn-explicit-parallel-conflicts | |
113 | @cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX | |
114 | Instructs @code{@value{AS}} not to produce warning messages when | |
115 | questionable parallel instructions are encountered. | |
116 | ||
117 | @item -Wnp | |
118 | @cindex @samp{-Wnp} option, M32RX | |
119 | This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} | |
120 | option. | |
121 | ||
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122 | @item -ignore-parallel-conflicts |
123 | @cindex @samp{-ignore-parallel-conflicts} option, M32RX | |
124 | This option tells the assembler's to stop checking parallel | |
125 | instructions for contraint violations. This ability is provided for | |
126 | hardware vendors testing chip designs and should not be used under | |
127 | normal circumstances. | |
128 | ||
129 | @item -no-ignore-parallel-conflicts | |
130 | @cindex @samp{-no-ignore-parallel-conflicts} option, M32RX | |
131 | This option restores the assembler's default behaviour of checking | |
132 | parallel instructions to detect constraint violations. | |
133 | ||
134 | @item -Ip | |
135 | @cindex @samp{-Ip} option, M32RX | |
136 | This is a shorter synonym for the @emph{-ignore-parallel-conflicts} | |
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137 | option. |
138 | ||
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139 | @item -nIp |
140 | @cindex @samp{-nIp} option, M32RX | |
141 | This is a shorter synonym for the @emph{-no-ignore-parallel-conflicts} | |
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142 | option. |
143 | ||
144 | @item -warn-unmatched-high | |
145 | @cindex @samp{-warn-unmatched-high} option, M32R | |
146 | This option tells the assembler to produce a warning message if a | |
147 | @code{.high} pseudo op is encountered without a mathcing @code{.low} | |
148 | pseudo op. The presence of such an unmatches pseudo op usually | |
149 | indicates a programming error. | |
150 | ||
151 | @item -no-warn-unmatched-high | |
152 | @cindex @samp{-no-warn-unmatched-high} option, M32R | |
153 | Disables a previously enabled @emph{-warn-unmatched-high} option. | |
154 | ||
155 | @item -Wuh | |
156 | @cindex @samp{-Wuh} option, M32RX | |
157 | This is a shorter synonym for the @emph{-warn-unmatched-high} option. | |
158 | ||
159 | @item -Wnuh | |
160 | @cindex @samp{-Wnuh} option, M32RX | |
161 | This is a shorter synonym for the @emph{-no-warn-unmatched-high} option. | |
162 | ||
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163 | @end table |
164 | ||
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165 | @node M32R-Directives |
166 | @section M32R Directives | |
167 | @cindex directives, M32R | |
168 | @cindex M32R directives | |
169 | ||
170 | The Renease M32R version of @code{@value{AS}} has a few architecture | |
171 | specific directives: | |
172 | ||
173 | @table @code | |
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174 | |
175 | @cindex @code{low} directive, M32R | |
176 | @item low @var{expression} | |
177 | The @code{low} directive computes the value of its expression and | |
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178 | places the lower 16-bits of the result into the immediate-field of the |
179 | instruction. For example: | |
180 | ||
181 | @smallexample | |
182 | or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 | |
183 | add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred | |
184 | @end smallexample | |
185 | ||
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186 | @item high @var{expression} |
187 | @cindex @code{high} directive, M32R | |
188 | The @code{high} directive computes the value of its expression and | |
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189 | places the upper 16-bits of the result into the immediate-field of the |
190 | instruction. For example: | |
191 | ||
192 | @smallexample | |
193 | seth r0, #high(0x12345678) ; compute r0 = 0x12340000 | |
194 | seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred | |
195 | @end smallexample | |
196 | ||
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197 | @item shigh @var{expression} |
198 | @cindex @code{shigh} directive, M32R | |
199 | The @code{shigh} directive is very similar to the @code{high} | |
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200 | directive. It also computes the value of its expression and places |
201 | the upper 16-bits of the result into the immediate-field of the | |
88845958 | 202 | instruction. The difference is that @code{shigh} also checks to see |
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203 | if the lower 16-bits could be interpreted as a signed number, and if |
204 | so it assumes that a borrow will occur from the upper-16 bits. To | |
88845958 | 205 | compensate for this the @code{shigh} directive pre-biases the upper |
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206 | 16 bit value by adding one to it. For example: |
207 | ||
208 | For example: | |
209 | ||
210 | @smallexample | |
211 | seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 | |
212 | seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 | |
213 | @end smallexample | |
214 | ||
215 | In the second example the lower 16-bits are 0x8000. If these are | |
216 | treated as a signed value and sign extended to 32-bits then the value | |
217 | becomes 0xffff8000. If this value is then added to 0x00010000 then | |
218 | the result is 0x00008000. | |
219 | ||
220 | This behaviour is to allow for the different semantics of the | |
221 | @code{or3} and @code{add3} instructions. The @code{or3} instruction | |
222 | treats its 16-bit immediate argument as unsigned whereas the | |
223 | @code{add3} treats its 16-bit immediate as a signed value. So for | |
224 | example: | |
225 | ||
226 | @smallexample | |
227 | seth r0, #shigh(0x00008000) | |
228 | add3 r0, r0, #low(0x00008000) | |
229 | @end smallexample | |
230 | ||
231 | Produces the correct result in r0, whereas: | |
232 | ||
233 | @smallexample | |
234 | seth r0, #shigh(0x00008000) | |
235 | or3 r0, r0, #low(0x00008000) | |
236 | @end smallexample | |
237 | ||
238 | Stores 0xffff8000 into r0. | |
239 | ||
240 | Note - the @code{shigh} directive does not know where in the assembly | |
241 | source code the lower 16-bits of the value are going set, so it cannot | |
242 | check to make sure that an @code{or3} instruction is being used rather | |
243 | than an @code{add3} instruction. It is up to the programmer to make | |
244 | sure that correct directives are used. | |
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245 | |
246 | @cindex @code{.m32r} directive, M32R | |
247 | @item .m32r | |
248 | The directive performs a similar thing as the @emph{-m32r} command | |
249 | line option. It tells the assembler to only accept M32R instructions | |
250 | from now on. An instructions from later M32R architectures are | |
251 | refused. | |
252 | ||
253 | @cindex @code{.m32rx} directive, M32RX | |
254 | @item .m32rx | |
255 | The directive performs a similar thing as the @emph{-m32rx} command | |
256 | line option. It tells the assembler to start accepting the extra | |
257 | instructions in the M32RX ISA as well as the ordinary M32R ISA. | |
258 | ||
259 | @cindex @code{.m32r2} directive, M32R2 | |
260 | @item .m32r2 | |
261 | The directive performs a similar thing as the @emph{-m32r2} command | |
262 | line option. It tells the assembler to start accepting the extra | |
263 | instructions in the M32R2 ISA as well as the ordinary M32R ISA. | |
264 | ||
265 | @cindex @code{.little} directive, M32RX | |
266 | @item .little | |
267 | The directive performs a similar thing as the @emph{-little} command | |
268 | line option. It tells the assembler to start producing little-endian | |
269 | code and data. This option should be used with care as producing | |
270 | mixed-endian binary files is frought with danger. | |
271 | ||
272 | @cindex @code{.big} directive, M32RX | |
273 | @item .big | |
274 | The directive performs a similar thing as the @emph{-big} command | |
275 | line option. It tells the assembler to start producing big-endian | |
276 | code and data. This option should be used with care as producing | |
277 | mixed-endian binary files is frought with danger. | |
278 | ||
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279 | @end table |
280 | ||
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281 | @node M32R-Warnings |
282 | @section M32R Warnings | |
283 | ||
284 | @cindex warnings, M32R | |
285 | @cindex M32R warnings | |
286 | ||
287 | There are several warning and error messages that can be produced by | |
288 | @code{@value{AS}} which are specific to the M32R: | |
289 | ||
290 | @table @code | |
291 | ||
292 | @item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? | |
293 | This message is only produced if warnings for explicit parallel | |
294 | conflicts have been enabled. It indicates that the assembler has | |
295 | encountered a parallel instruction in which the destination register of | |
296 | the left hand instruction is used as an input register in the right hand | |
297 | instruction. For example in this code fragment | |
298 | @samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the | |
299 | move instruction and the input to the neg instruction. | |
300 | ||
301 | @item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? | |
302 | This message is only produced if warnings for explicit parallel | |
303 | conflicts have been enabled. It indicates that the assembler has | |
304 | encountered a parallel instruction in which the destination register of | |
305 | the right hand instruction is used as an input register in the left hand | |
306 | instruction. For example in this code fragment | |
307 | @samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the | |
308 | neg instruction and the input to the move instruction. | |
309 | ||
310 | @item instruction @samp{...} is for the M32RX only | |
311 | This message is produced when the assembler encounters an instruction | |
312 | which is only supported by the M32Rx processor, and the @samp{-m32rx} | |
313 | command line flag has not been specified to allow assembly of such | |
314 | instructions. | |
315 | ||
316 | @item unknown instruction @samp{...} | |
317 | This message is produced when the assembler encounters an instruction | |
9f7598c1 | 318 | which it does not recognise. |
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319 | |
320 | @item only the NOP instruction can be issued in parallel on the m32r | |
321 | This message is produced when the assembler encounters a parallel | |
322 | instruction which does not involve a NOP instruction and the | |
323 | @samp{-m32rx} command line flag has not been specified. Only the M32Rx | |
324 | processor is able to execute two instructions in parallel. | |
325 | ||
326 | @item instruction @samp{...} cannot be executed in parallel. | |
327 | This message is produced when the assembler encounters a parallel | |
328 | instruction which is made up of one or two instructions which cannot be | |
329 | executed in parallel. | |
330 | ||
331 | @item Instructions share the same execution pipeline | |
332 | This message is produced when the assembler encounters a parallel | |
333 | instruction whoes components both use the same execution pipeline. | |
334 | ||
335 | @item Instructions write to the same destination register. | |
336 | This message is produced when the assembler encounters a parallel | |
337 | instruction where both components attempt to modify the same register. | |
338 | For example these code fragments will produce this message: | |
339 | @samp{mv r1, r2 || neg r1, r3} | |
340 | @samp{jl r0 || mv r14, r1} | |
341 | @samp{st r2, @@-r1 || mv r1, r3} | |
342 | @samp{mv r1, r2 || ld r0, @@r1+} | |
343 | @samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) | |
344 | ||
345 | @end table |