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9f7598c1 | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2003 |
f7e42eb4 | 2 | @c Free Software Foundation, Inc. |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @ifset GENERIC | |
6 | @page | |
7 | @node M32R-Dependent | |
8 | @chapter M32R Dependent Features | |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter M32R Dependent Features | |
13 | @end ifclear | |
14 | ||
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15 | @cindex M32R support |
16 | @menu | |
17 | * M32R-Opts:: M32R Options | |
9f7598c1 | 18 | * M32R-Directives:: M32R Directives |
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19 | * M32R-Warnings:: M32R Warnings |
20 | @end menu | |
21 | ||
22 | @node M32R-Opts | |
23 | @section M32R Options | |
24 | ||
25 | @cindex options, M32R | |
26 | @cindex M32R options | |
27 | ||
26597c86 | 28 | The Renease M32R version of @code{@value{AS}} has a few machine |
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29 | dependent options: |
30 | ||
31 | @table @code | |
32 | @item -m32rx | |
33 | @cindex @samp{-m32rx} option, M32RX | |
34 | @cindex architecture options, M32RX | |
35 | @cindex M32R architecture options | |
36 | @code{@value{AS}} can assemble code for several different members of the | |
26597c86 | 37 | Renesas M32R family. Normally the default is to assemble code for |
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38 | the M32R microprocessor. This option may be used to change the default |
39 | to the M32RX microprocessor, which adds some more instructions to the | |
40 | basic M32R instruction set, and some additional parameters to some of | |
41 | the original instructions. | |
42 | ||
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43 | @item -m32r |
44 | @cindex @samp{-m32r} option, M32R | |
45 | @cindex architecture options, M32R | |
46 | @cindex M32R architecture options | |
47 | This option can be used to restore the assembler's default behaviour of | |
48 | assembling for the M32R microprocessor. This can be useful if the | |
49 | default has been changed by a previous command line option. | |
50 | ||
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51 | @item -warn-explicit-parallel-conflicts |
52 | @cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX | |
53 | Instructs @code{@value{AS}} to produce warning messages when | |
54 | questionable parallel instructions are encountered. This option is | |
55 | enabled by default, but @code{@value{GCC}} disables it when it invokes | |
56 | @code{@value{AS}} directly. Questionable instructions are those whoes | |
57 | behaviour would be different if they were executed sequentially. For | |
58 | example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a | |
59 | different result from @samp{mv r1, r2 \n mv r3, r1} since the former | |
60 | moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 | |
61 | and r3. | |
62 | ||
63 | @item -Wp | |
64 | @cindex @samp{-Wp} option, M32RX | |
65 | This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} | |
66 | option. | |
67 | ||
68 | @item -no-warn-explicit-parallel-conflicts | |
69 | @cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX | |
70 | Instructs @code{@value{AS}} not to produce warning messages when | |
71 | questionable parallel instructions are encountered. | |
72 | ||
73 | @item -Wnp | |
74 | @cindex @samp{-Wnp} option, M32RX | |
75 | This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} | |
76 | option. | |
77 | ||
78 | @end table | |
79 | ||
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80 | @node M32R-Directives |
81 | @section M32R Directives | |
82 | @cindex directives, M32R | |
83 | @cindex M32R directives | |
84 | ||
85 | The Renease M32R version of @code{@value{AS}} has a few architecture | |
86 | specific directives: | |
87 | ||
88 | @table @code | |
89 | @cindex @code{.low} directive, M32R | |
90 | @item .low @var{expression} | |
91 | The @code{.low} directive computes the value of its expression and | |
92 | places the lower 16-bits of the result into the immediate-field of the | |
93 | instruction. For example: | |
94 | ||
95 | @smallexample | |
96 | or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 | |
97 | add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred | |
98 | @end smallexample | |
99 | ||
100 | @item .high @var{expression} | |
101 | @cindex @code{.high} directive, M32R | |
102 | The @code{.high} directive computes the value of its expression and | |
103 | places the upper 16-bits of the result into the immediate-field of the | |
104 | instruction. For example: | |
105 | ||
106 | @smallexample | |
107 | seth r0, #high(0x12345678) ; compute r0 = 0x12340000 | |
108 | seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred | |
109 | @end smallexample | |
110 | ||
111 | @item .shigh @var{expression} | |
112 | @cindex @code{.shigh} directive, M32R | |
113 | The @code{.shigh} directive is very similar to the @code{.high} | |
114 | directive. It also computes the value of its expression and places | |
115 | the upper 16-bits of the result into the immediate-field of the | |
116 | instruction. The difference is that @code{.shigh} also checks to see | |
117 | if the lower 16-bits could be interpreted as a signed number, and if | |
118 | so it assumes that a borrow will occur from the upper-16 bits. To | |
119 | compensate for this the @code{.shigh} directive pre-biases the upper | |
120 | 16 bit value by adding one to it. For example: | |
121 | ||
122 | For example: | |
123 | ||
124 | @smallexample | |
125 | seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 | |
126 | seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 | |
127 | @end smallexample | |
128 | ||
129 | In the second example the lower 16-bits are 0x8000. If these are | |
130 | treated as a signed value and sign extended to 32-bits then the value | |
131 | becomes 0xffff8000. If this value is then added to 0x00010000 then | |
132 | the result is 0x00008000. | |
133 | ||
134 | This behaviour is to allow for the different semantics of the | |
135 | @code{or3} and @code{add3} instructions. The @code{or3} instruction | |
136 | treats its 16-bit immediate argument as unsigned whereas the | |
137 | @code{add3} treats its 16-bit immediate as a signed value. So for | |
138 | example: | |
139 | ||
140 | @smallexample | |
141 | seth r0, #shigh(0x00008000) | |
142 | add3 r0, r0, #low(0x00008000) | |
143 | @end smallexample | |
144 | ||
145 | Produces the correct result in r0, whereas: | |
146 | ||
147 | @smallexample | |
148 | seth r0, #shigh(0x00008000) | |
149 | or3 r0, r0, #low(0x00008000) | |
150 | @end smallexample | |
151 | ||
152 | Stores 0xffff8000 into r0. | |
153 | ||
154 | Note - the @code{shigh} directive does not know where in the assembly | |
155 | source code the lower 16-bits of the value are going set, so it cannot | |
156 | check to make sure that an @code{or3} instruction is being used rather | |
157 | than an @code{add3} instruction. It is up to the programmer to make | |
158 | sure that correct directives are used. | |
159 | @end table | |
160 | ||
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161 | @node M32R-Warnings |
162 | @section M32R Warnings | |
163 | ||
164 | @cindex warnings, M32R | |
165 | @cindex M32R warnings | |
166 | ||
167 | There are several warning and error messages that can be produced by | |
168 | @code{@value{AS}} which are specific to the M32R: | |
169 | ||
170 | @table @code | |
171 | ||
172 | @item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? | |
173 | This message is only produced if warnings for explicit parallel | |
174 | conflicts have been enabled. It indicates that the assembler has | |
175 | encountered a parallel instruction in which the destination register of | |
176 | the left hand instruction is used as an input register in the right hand | |
177 | instruction. For example in this code fragment | |
178 | @samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the | |
179 | move instruction and the input to the neg instruction. | |
180 | ||
181 | @item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? | |
182 | This message is only produced if warnings for explicit parallel | |
183 | conflicts have been enabled. It indicates that the assembler has | |
184 | encountered a parallel instruction in which the destination register of | |
185 | the right hand instruction is used as an input register in the left hand | |
186 | instruction. For example in this code fragment | |
187 | @samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the | |
188 | neg instruction and the input to the move instruction. | |
189 | ||
190 | @item instruction @samp{...} is for the M32RX only | |
191 | This message is produced when the assembler encounters an instruction | |
192 | which is only supported by the M32Rx processor, and the @samp{-m32rx} | |
193 | command line flag has not been specified to allow assembly of such | |
194 | instructions. | |
195 | ||
196 | @item unknown instruction @samp{...} | |
197 | This message is produced when the assembler encounters an instruction | |
9f7598c1 | 198 | which it does not recognise. |
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199 | |
200 | @item only the NOP instruction can be issued in parallel on the m32r | |
201 | This message is produced when the assembler encounters a parallel | |
202 | instruction which does not involve a NOP instruction and the | |
203 | @samp{-m32rx} command line flag has not been specified. Only the M32Rx | |
204 | processor is able to execute two instructions in parallel. | |
205 | ||
206 | @item instruction @samp{...} cannot be executed in parallel. | |
207 | This message is produced when the assembler encounters a parallel | |
208 | instruction which is made up of one or two instructions which cannot be | |
209 | executed in parallel. | |
210 | ||
211 | @item Instructions share the same execution pipeline | |
212 | This message is produced when the assembler encounters a parallel | |
213 | instruction whoes components both use the same execution pipeline. | |
214 | ||
215 | @item Instructions write to the same destination register. | |
216 | This message is produced when the assembler encounters a parallel | |
217 | instruction where both components attempt to modify the same register. | |
218 | For example these code fragments will produce this message: | |
219 | @samp{mv r1, r2 || neg r1, r3} | |
220 | @samp{jl r0 || mv r14, r1} | |
221 | @samp{st r2, @@-r1 || mv r1, r3} | |
222 | @samp{mv r1, r2 || ld r0, @@r1+} | |
223 | @samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) | |
224 | ||
225 | @end table |