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1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, |
2 | @c 2002, 2003, 2004 | |
f7e42eb4 | 3 | @c Free Software Foundation, Inc. |
252b5132 RH |
4 | @c This is part of the GAS manual. |
5 | @c For copying conditions, see the file as.texinfo. | |
6 | @ifset GENERIC | |
7 | @page | |
8 | @node MIPS-Dependent | |
9 | @chapter MIPS Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter MIPS Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex MIPS processor | |
17 | @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several | |
84ea6cf2 | 18 | different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, |
584da044 NC |
19 | and MIPS64. For information about the @sc{mips} instruction set, see |
20 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). | |
21 | For an overview of @sc{mips} assembly conventions, see ``Appendix D: | |
22 | Assembly Language Programming'' in the same work. | |
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23 | |
24 | @menu | |
25 | * MIPS Opts:: Assembler options | |
26 | * MIPS Object:: ECOFF object code | |
27 | * MIPS Stabs:: Directives for debugging information | |
28 | * MIPS ISA:: Directives to override the ISA level | |
aed1a261 | 29 | * MIPS symbol sizes:: Directives to override the size of symbols |
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30 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
31 | * MIPS insn:: Directive to mark data as an instruction | |
32 | * MIPS option stack:: Directives to save and restore options | |
0eb7102d AJ |
33 | * MIPS ASE instruction generation overrides:: Directives to control |
34 | generation of MIPS ASE instructions | |
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35 | @end menu |
36 | ||
37 | @node MIPS Opts | |
38 | @section Assembler options | |
39 | ||
40 | The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these | |
41 | special options: | |
42 | ||
43 | @table @code | |
44 | @cindex @code{-G} option (MIPS) | |
45 | @item -G @var{num} | |
46 | This option sets the largest size of an object that can be referenced | |
47 | implicitly with the @code{gp} register. It is only accepted for targets | |
48 | that use @sc{ecoff} format. The default value is 8. | |
49 | ||
50 | @cindex @code{-EB} option (MIPS) | |
51 | @cindex @code{-EL} option (MIPS) | |
52 | @cindex MIPS big-endian output | |
53 | @cindex MIPS little-endian output | |
54 | @cindex big-endian output, MIPS | |
55 | @cindex little-endian output, MIPS | |
56 | @item -EB | |
57 | @itemx -EL | |
58 | Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or | |
59 | little-endian output at run time (unlike the other @sc{gnu} development | |
60 | tools, which must be configured for one or the other). Use @samp{-EB} | |
61 | to select big-endian output, and @samp{-EL} for little-endian. | |
62 | ||
63 | @cindex MIPS architecture options | |
64 | @item -mips1 | |
65 | @itemx -mips2 | |
66 | @itemx -mips3 | |
67 | @itemx -mips4 | |
84ea6cf2 | 68 | @itemx -mips5 |
e7af610e | 69 | @itemx -mips32 |
af7ee8bf | 70 | @itemx -mips32r2 |
84ea6cf2 | 71 | @itemx -mips64 |
5f74bc13 | 72 | @itemx -mips64r2 |
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73 | Generate code for a particular MIPS Instruction Set Architecture level. |
74 | @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, | |
75 | @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the | |
84ea6cf2 | 76 | @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and |
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77 | @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, |
78 | @samp{-mips64}, and @samp{-mips64r2} | |
79 | correspond to generic | |
80 | @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, | |
81 | and @sc{MIPS64 Release 2} | |
82 | ISA processors, respectively. You can also switch | |
584da044 | 83 | instruction sets during the assembly; see @ref{MIPS ISA, Directives to |
ec68c924 | 84 | override the ISA level}. |
252b5132 | 85 | |
6349b5f4 | 86 | @item -mgp32 |
ca4e0257 RS |
87 | @itemx -mfp32 |
88 | Some macros have different expansions for 32-bit and 64-bit registers. | |
89 | The register sizes are normally inferred from the ISA and ABI, but these | |
90 | flags force a certain group of registers to be treated as 32 bits wide at | |
91 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
92 | and @samp{-mfp32} controls the size of floating-point registers. | |
93 | ||
ad3fea08 TS |
94 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
95 | of registers to be changed for parts of an object. The default value is | |
96 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
97 | ||
ca4e0257 RS |
98 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
99 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
100 | save the 32-bit registers on a context switch, so it is essential never | |
101 | to use the 64-bit registers. | |
6349b5f4 AH |
102 | |
103 | @item -mgp64 | |
ad3fea08 TS |
104 | @itemx -mfp64 |
105 | Assume that 64-bit registers are available. This is provided in the | |
106 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. | |
107 | ||
108 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size | |
109 | of registers to be changed for parts of an object. The default value is | |
110 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
6349b5f4 | 111 | |
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112 | @item -mips16 |
113 | @itemx -no-mips16 | |
114 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
ad3fea08 | 115 | @code{.set mips16} at the start of the assembly file. @samp{-no-mips16} |
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116 | turns off this option. |
117 | ||
e16bfa71 TS |
118 | @item -msmartmips |
119 | @itemx -mno-smartmips | |
120 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which | |
121 | provides a number of new instructions which target smartcard and | |
122 | cryptographic applications. This is equivalent to putting | |
ad3fea08 | 123 | @code{.set smartmips} at the start of the assembly file. |
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124 | @samp{-mno-smartmips} turns off this option. |
125 | ||
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126 | @item -mips3d |
127 | @itemx -no-mips3d | |
128 | Generate code for the MIPS-3D Application Specific Extension. | |
129 | This tells the assembler to accept MIPS-3D instructions. | |
130 | @samp{-no-mips3d} turns off this option. | |
131 | ||
deec1734 CD |
132 | @item -mdmx |
133 | @itemx -no-mdmx | |
134 | Generate code for the MDMX Application Specific Extension. | |
135 | This tells the assembler to accept MDMX instructions. | |
136 | @samp{-no-mdmx} turns off this option. | |
137 | ||
2ef2b9ae CF |
138 | @item -mdsp |
139 | @itemx -mno-dsp | |
140 | Generate code for the DSP Application Specific Extension. | |
141 | This tells the assembler to accept DSP instructions. | |
142 | @samp{-mno-dsp} turns off this option. | |
143 | ||
ef2e4d86 CF |
144 | @item -mmt |
145 | @itemx -mno-mt | |
146 | Generate code for the MT Application Specific Extension. | |
147 | This tells the assembler to accept MT instructions. | |
148 | @samp{-mno-mt} turns off this option. | |
149 | ||
6b76fefe | 150 | @item -mfix7000 |
9ee72ff1 | 151 | @itemx -mno-fix7000 |
6b76fefe CM |
152 | Cause nops to be inserted if the read of the destination register |
153 | of an mfhi or mflo instruction occurs in the following two instructions. | |
154 | ||
d766e8ec RS |
155 | @item -mfix-vr4120 |
156 | @itemx -no-mfix-vr4120 | |
157 | Insert nops to work around certain VR4120 errata. This option is | |
158 | intended to be used on GCC-generated code: it is not designed to catch | |
159 | all problems in hand-written assembler code. | |
60b63b72 | 160 | |
11db99f8 RS |
161 | @item -mfix-vr4130 |
162 | @itemx -no-mfix-vr4130 | |
163 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. | |
164 | ||
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165 | @item -m4010 |
166 | @itemx -no-m4010 | |
167 | Generate code for the LSI @sc{r4010} chip. This tells the assembler to | |
168 | accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, | |
169 | etc.), and to not schedule @samp{nop} instructions around accesses to | |
170 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
171 | option. | |
172 | ||
173 | @item -m4650 | |
174 | @itemx -no-m4650 | |
175 | Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept | |
176 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} | |
177 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
178 | @samp{-no-m4650} turns off this option. | |
179 | ||
180 | @itemx -m3900 | |
181 | @itemx -no-m3900 | |
182 | @itemx -m4100 | |
183 | @itemx -no-m4100 | |
184 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
185 | @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions | |
186 | specific to that chip, and to schedule for that chip's hazards. | |
187 | ||
ec68c924 | 188 | @item -march=@var{cpu} |
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189 | Generate code for a particular MIPS cpu. It is exactly equivalent to |
190 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} | |
191 | understood. Valid @var{cpu} value are: | |
192 | ||
193 | @quotation | |
194 | 2000, | |
195 | 3000, | |
196 | 3900, | |
197 | 4000, | |
198 | 4010, | |
199 | 4100, | |
200 | 4111, | |
60b63b72 RS |
201 | vr4120, |
202 | vr4130, | |
203 | vr4181, | |
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204 | 4300, |
205 | 4400, | |
206 | 4600, | |
207 | 4650, | |
208 | 5000, | |
b946ec34 NC |
209 | rm5200, |
210 | rm5230, | |
211 | rm5231, | |
212 | rm5261, | |
213 | rm5721, | |
60b63b72 RS |
214 | vr5400, |
215 | vr5500, | |
252b5132 | 216 | 6000, |
b946ec34 | 217 | rm7000, |
252b5132 | 218 | 8000, |
963ac363 | 219 | rm9000, |
e7af610e | 220 | 10000, |
18ae5d72 | 221 | 12000, |
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222 | 4kc, |
223 | 4km, | |
224 | 4kp, | |
225 | 4ksc, | |
226 | 4kec, | |
227 | 4kem, | |
228 | 4kep, | |
229 | 4ksd, | |
230 | m4k, | |
231 | m4kp, | |
232 | 24kc, | |
233 | 24kf, | |
234 | 24kx, | |
235 | 24kec, | |
236 | 24kef, | |
237 | 24kex, | |
238 | 34kc, | |
239 | 34kf, | |
240 | 34kx, | |
241 | 5kc, | |
242 | 5kf, | |
243 | 20kc, | |
244 | 25kf, | |
c6c98b38 | 245 | sb1 |
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246 | @end quotation |
247 | ||
ec68c924 EC |
248 | @item -mtune=@var{cpu} |
249 | Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are | |
250 | identical to @samp{-march=@var{cpu}}. | |
251 | ||
316f5878 RS |
252 | @item -mabi=@var{abi} |
253 | Record which ABI the source code uses. The recognized arguments | |
254 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
252b5132 | 255 | |
aed1a261 RS |
256 | @item -msym32 |
257 | @itemx -mno-sym32 | |
258 | @cindex -msym32 | |
259 | @cindex -mno-sym32 | |
260 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to | |
261 | the beginning of the assembler input. @xref{MIPS symbol sizes}. | |
262 | ||
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263 | @cindex @code{-nocpp} ignored (MIPS) |
264 | @item -nocpp | |
265 | This option is ignored. It is accepted for command-line compatibility with | |
266 | other assemblers, which use it to turn off C style preprocessing. With | |
267 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
268 | @sc{gnu} assembler itself never runs the C preprocessor. | |
269 | ||
119d663a NC |
270 | @item --construct-floats |
271 | @itemx --no-construct-floats | |
272 | @cindex --construct-floats | |
273 | @cindex --no-construct-floats | |
274 | The @code{--no-construct-floats} option disables the construction of | |
275 | double width floating point constants by loading the two halves of the | |
276 | value into the two single width floating point registers that make up | |
277 | the double width register. This feature is useful if the processor | |
278 | support the FR bit in its status register, and this bit is known (by | |
279 | the programmer) to be set. This bit prevents the aliasing of the double | |
280 | width register by the single width registers. | |
281 | ||
63bf5651 | 282 | By default @code{--construct-floats} is selected, allowing construction |
119d663a NC |
283 | of these floating point constants. |
284 | ||
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285 | @item --trap |
286 | @itemx --no-break | |
287 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
288 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
289 | @code{@value{AS}} automatically macro expands certain division and | |
290 | multiplication instructions to check for overflow and division by zero. This | |
291 | option causes @code{@value{AS}} to generate code to take a trap exception | |
292 | rather than a break exception when an error is detected. The trap instructions | |
293 | are only supported at Instruction Set Architecture level 2 and higher. | |
294 | ||
295 | @item --break | |
296 | @itemx --no-trap | |
297 | Generate code to take a break exception rather than a trap exception when an | |
298 | error is detected. This is the default. | |
63486801 | 299 | |
dcd410fe RO |
300 | @item -mpdr |
301 | @itemx -mno-pdr | |
302 | Control generation of @code{.pdr} sections. Off by default on IRIX, on | |
303 | elsewhere. | |
aa6975fb ILT |
304 | |
305 | @item -mshared | |
306 | @itemx -mno-shared | |
307 | When generating code using the Unix calling conventions (selected by | |
308 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code | |
309 | which can go into a shared library. The @samp{-mno-shared} option | |
310 | tells gas to generate code which uses the calling convention, but can | |
311 | not go into a shared library. The resulting code is slightly more | |
312 | efficient. This option only affects the handling of the | |
313 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. | |
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314 | @end table |
315 | ||
316 | @node MIPS Object | |
317 | @section MIPS ECOFF object code | |
318 | ||
319 | @cindex ECOFF sections | |
320 | @cindex MIPS ECOFF sections | |
321 | Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections | |
322 | besides the usual @code{.text}, @code{.data} and @code{.bss}. The | |
323 | additional sections are @code{.rdata}, used for read-only data, | |
324 | @code{.sdata}, used for small data, and @code{.sbss}, used for small | |
325 | common objects. | |
326 | ||
327 | @cindex small objects, MIPS ECOFF | |
328 | @cindex @code{gp} register, MIPS | |
329 | When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) | |
330 | register to form the address of a ``small object''. Any object in the | |
331 | @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. | |
332 | For external objects, or for objects in the @code{.bss} section, you can use | |
333 | the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via | |
334 | @code{$gp}; the default value is 8, meaning that a reference to any object | |
335 | eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to | |
336 | @code{@value{AS}} prevents it from using the @code{$gp} register on the basis | |
337 | of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} | |
338 | or @code{sbss} in any case). The size of an object in the @code{.bss} section | |
339 | is set by the @code{.comm} or @code{.lcomm} directive that defines it. The | |
340 | size of an external object may be set with the @code{.extern} directive. For | |
341 | example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes | |
342 | in length, whie leaving @code{sym} otherwise undefined. | |
343 | ||
344 | Using small @sc{ecoff} objects requires linker support, and assumes that the | |
345 | @code{$gp} register is correctly initialized (normally done automatically by | |
346 | the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the | |
347 | @code{$gp} register. | |
348 | ||
349 | @node MIPS Stabs | |
350 | @section Directives for debugging information | |
351 | ||
352 | @cindex MIPS debugging directives | |
353 | @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for | |
354 | generating debugging information which are not support by traditional @sc{mips} | |
355 | assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, | |
356 | @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, | |
357 | @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information | |
358 | generated by the three @code{.stab} directives can only be read by @sc{gdb}, | |
359 | not by traditional @sc{mips} debuggers (this enhancement is required to fully | |
360 | support C++ debugging). These directives are primarily used by compilers, not | |
361 | assembly language programmers! | |
362 | ||
aed1a261 RS |
363 | @node MIPS symbol sizes |
364 | @section Directives to override the size of symbols | |
365 | ||
366 | @cindex @code{.set sym32} | |
367 | @cindex @code{.set nosym32} | |
368 | The n64 ABI allows symbols to have any 64-bit value. Although this | |
369 | provides a great deal of flexibility, it means that some macros have | |
370 | much longer expansions than their 32-bit counterparts. For example, | |
371 | the non-PIC expansion of @samp{dla $4,sym} is usually: | |
372 | ||
373 | @smallexample | |
374 | lui $4,%highest(sym) | |
375 | lui $1,%hi(sym) | |
376 | daddiu $4,$4,%higher(sym) | |
377 | daddiu $1,$1,%lo(sym) | |
378 | dsll32 $4,$4,0 | |
379 | daddu $4,$4,$1 | |
380 | @end smallexample | |
381 | ||
382 | whereas the 32-bit expansion is simply: | |
383 | ||
384 | @smallexample | |
385 | lui $4,%hi(sym) | |
386 | daddiu $4,$4,%lo(sym) | |
387 | @end smallexample | |
388 | ||
389 | n64 code is sometimes constructed in such a way that all symbolic | |
390 | constants are known to have 32-bit values, and in such cases, it's | |
391 | preferable to use the 32-bit expansion instead of the 64-bit | |
392 | expansion. | |
393 | ||
394 | You can use the @code{.set sym32} directive to tell the assembler | |
395 | that, from this point on, all expressions of the form | |
396 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} | |
397 | have 32-bit values. For example: | |
398 | ||
399 | @smallexample | |
400 | .set sym32 | |
401 | dla $4,sym | |
402 | lw $4,sym+16 | |
403 | sw $4,sym+0x8000($4) | |
404 | @end smallexample | |
405 | ||
406 | will cause the assembler to treat @samp{sym}, @code{sym+16} and | |
407 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic | |
408 | addresses is not affected. | |
409 | ||
410 | The directive @code{.set nosym32} ends a @code{.set sym32} block and | |
411 | reverts to the normal behavior. It is also possible to change the | |
412 | symbol size using the command-line options @option{-msym32} and | |
413 | @option{-mno-sym32}. | |
414 | ||
415 | These options and directives are always accepted, but at present, | |
416 | they have no effect for anything other than n64. | |
417 | ||
252b5132 RH |
418 | @node MIPS ISA |
419 | @section Directives to override the ISA level | |
420 | ||
421 | @cindex MIPS ISA override | |
422 | @kindex @code{.set mips@var{n}} | |
423 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
424 | the @sc{mips} Instruction Set Architecture level on the fly: @code{.set | |
5f74bc13 CD |
425 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 |
426 | or 64r2. | |
071742cf | 427 | The values other than 0 make the assembler accept instructions |
584da044 NC |
428 | for the corresponding @sc{isa} level, from that point on in the |
429 | assembly. @code{.set mips@var{n}} affects not only which instructions | |
430 | are permitted, but also how certain macros are expanded. @code{.set | |
431 | mips0} restores the @sc{isa} level to its original level: either the | |
432 | level you selected with command line options, or the default for your | |
ad3fea08 | 433 | configuration. You can use this feature to permit specific @sc{mips3} |
584da044 | 434 | instructions while assembling in 32 bit mode. Use this directive with |
ec68c924 | 435 | care! |
252b5132 | 436 | |
ad3fea08 TS |
437 | @cindex MIPS CPU override |
438 | @kindex @code{.set arch=@var{cpu}} | |
439 | The @code{.set arch=@var{cpu}} directive provides even finer control. | |
440 | It changes the effective CPU target and allows the assembler to use | |
441 | instructions specific to a particular CPU. All CPUs supported by the | |
442 | @samp{-march} command line option are also selectable by this directive. | |
443 | The original value is restored by @code{.set arch=default}. | |
252b5132 | 444 | |
ad3fea08 TS |
445 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
446 | in which it will assemble instructions for the MIPS 16 processor. Use | |
447 | @code{.set nomips16} to return to normal 32 bit mode. | |
e16bfa71 | 448 | |
ec68c924 | 449 | Traditional @sc{mips} assemblers do not support this directive. |
252b5132 RH |
450 | |
451 | @node MIPS autoextend | |
452 | @section Directives for extending MIPS 16 bit instructions | |
453 | ||
454 | @kindex @code{.set autoextend} | |
455 | @kindex @code{.set noautoextend} | |
456 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
ad3fea08 TS |
457 | when necessary. The directive @code{.set noautoextend} will turn this |
458 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction | |
459 | must be explicitly extended with the @code{.e} modifier (e.g., | |
460 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used | |
252b5132 RH |
461 | to once again automatically extend instructions when necessary. |
462 | ||
463 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
464 | @sc{mips} assemblers do not support this directive. | |
465 | ||
466 | @node MIPS insn | |
467 | @section Directive to mark data as an instruction | |
468 | ||
469 | @kindex @code{.insn} | |
470 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
471 | data is actually instructions. This makes a difference in MIPS 16 mode: | |
472 | when loading the address of a label which precedes instructions, | |
473 | @code{@value{AS}} automatically adds 1 to the value, so that jumping to | |
474 | the loaded address will do the right thing. | |
475 | ||
476 | @node MIPS option stack | |
477 | @section Directives to save and restore options | |
478 | ||
479 | @cindex MIPS option stack | |
480 | @kindex @code{.set push} | |
481 | @kindex @code{.set pop} | |
482 | The directives @code{.set push} and @code{.set pop} may be used to save | |
483 | and restore the current settings for all the options which are | |
484 | controlled by @code{.set}. The @code{.set push} directive saves the | |
485 | current settings on a stack. The @code{.set pop} directive pops the | |
486 | stack and restores the settings. | |
487 | ||
488 | These directives can be useful inside an macro which must change an | |
489 | option such as the ISA level or instruction reordering but does not want | |
490 | to change the state of the code which invoked the macro. | |
491 | ||
492 | Traditional @sc{mips} assemblers do not support these directives. | |
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493 | |
494 | @node MIPS ASE instruction generation overrides | |
495 | @section Directives to control generation of MIPS ASE instructions | |
496 | ||
497 | @cindex MIPS MIPS-3D instruction generation override | |
498 | @kindex @code{.set mips3d} | |
499 | @kindex @code{.set nomips3d} | |
500 | The directive @code{.set mips3d} makes the assembler accept instructions | |
501 | from the MIPS-3D Application Specific Extension from that point on | |
502 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
503 | instructions from being accepted. | |
504 | ||
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505 | @cindex SmartMIPS instruction generation override |
506 | @kindex @code{.set smartmips} | |
507 | @kindex @code{.set nosmartmips} | |
508 | The directive @code{.set smartmips} makes the assembler accept | |
509 | instructions from the SmartMIPS Application Specific Extension to the | |
510 | MIPS32 @sc{isa} from that point on in the assembly. The | |
511 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from | |
512 | being accepted. | |
513 | ||
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514 | @cindex MIPS MDMX instruction generation override |
515 | @kindex @code{.set mdmx} | |
516 | @kindex @code{.set nomdmx} | |
517 | The directive @code{.set mdmx} makes the assembler accept instructions | |
518 | from the MDMX Application Specific Extension from that point on | |
519 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
520 | instructions from being accepted. | |
521 | ||
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522 | @cindex MIPS DSP instruction generation override |
523 | @kindex @code{.set dsp} | |
524 | @kindex @code{.set nodsp} | |
525 | The directive @code{.set dsp} makes the assembler accept instructions | |
526 | from the DSP Application Specific Extension from that point on | |
527 | in the assembly. The @code{.set nodsp} directive prevents DSP | |
528 | instructions from being accepted. | |
529 | ||
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530 | @cindex MIPS MT instruction generation override |
531 | @kindex @code{.set mt} | |
532 | @kindex @code{.set nomt} | |
533 | The directive @code{.set mt} makes the assembler accept instructions | |
534 | from the MT Application Specific Extension from that point on | |
535 | in the assembly. The @code{.set nomt} directive prevents MT | |
536 | instructions from being accepted. | |
537 | ||
1f25f5d3 | 538 | Traditional @sc{mips} assemblers do not support these directives. |