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219d1afa | 1 | @c Copyright (C) 1991-2018 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node MIPS-Dependent | |
7 | @chapter MIPS Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter MIPS Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex MIPS processor | |
98508b2a RS |
15 | @sc{gnu} @code{@value{AS}} for MIPS architectures supports several |
16 | different MIPS processors, and MIPS ISA levels I through V, MIPS32, | |
17 | and MIPS64. For information about the MIPS instruction set, see | |
584da044 | 18 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
98508b2a | 19 | For an overview of MIPS assembly conventions, see ``Appendix D: |
584da044 | 20 | Assembly Language Programming'' in the same work. |
252b5132 RH |
21 | |
22 | @menu | |
98508b2a | 23 | * MIPS Options:: Assembler options |
fc16f8cc | 24 | * MIPS Macros:: High-level assembly macros |
5a7560b5 | 25 | * MIPS Symbol Sizes:: Directives to override the size of symbols |
fc16f8cc | 26 | * MIPS Small Data:: Controlling the use of small data accesses |
252b5132 | 27 | * MIPS ISA:: Directives to override the ISA level |
833794fc | 28 | * MIPS assembly options:: Directives to control code generation |
252b5132 RH |
29 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
30 | * MIPS insn:: Directive to mark data as an instruction | |
351cdf24 | 31 | * MIPS FP ABIs:: Marking which FP ABI is in use |
ba92f887 | 32 | * MIPS NaN Encodings:: Directives to record which NaN encoding is being used |
98508b2a RS |
33 | * MIPS Option Stack:: Directives to save and restore options |
34 | * MIPS ASE Instruction Generation Overrides:: Directives to control | |
0eb7102d | 35 | generation of MIPS ASE instructions |
98508b2a | 36 | * MIPS Floating-Point:: Directives to override floating-point options |
7c31ae13 | 37 | * MIPS Syntax:: MIPS specific syntactical considerations |
252b5132 RH |
38 | @end menu |
39 | ||
98508b2a | 40 | @node MIPS Options |
252b5132 RH |
41 | @section Assembler options |
42 | ||
98508b2a | 43 | The MIPS configurations of @sc{gnu} @code{@value{AS}} support these |
252b5132 RH |
44 | special options: |
45 | ||
46 | @table @code | |
47 | @cindex @code{-G} option (MIPS) | |
48 | @item -G @var{num} | |
fc16f8cc RS |
49 | Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. |
50 | @xref{MIPS Small Data,, Controlling the use of small data accesses}. | |
252b5132 RH |
51 | |
52 | @cindex @code{-EB} option (MIPS) | |
53 | @cindex @code{-EL} option (MIPS) | |
54 | @cindex MIPS big-endian output | |
55 | @cindex MIPS little-endian output | |
56 | @cindex big-endian output, MIPS | |
57 | @cindex little-endian output, MIPS | |
58 | @item -EB | |
59 | @itemx -EL | |
98508b2a | 60 | Any MIPS configuration of @code{@value{AS}} can select big-endian or |
252b5132 RH |
61 | little-endian output at run time (unlike the other @sc{gnu} development |
62 | tools, which must be configured for one or the other). Use @samp{-EB} | |
63 | to select big-endian output, and @samp{-EL} for little-endian. | |
64 | ||
0c000745 RS |
65 | @item -KPIC |
66 | @cindex PIC selection, MIPS | |
67 | @cindex @option{-KPIC} option, MIPS | |
68 | Generate SVR4-style PIC. This option tells the assembler to generate | |
69 | SVR4-style position-independent macro expansions. It also tells the | |
70 | assembler to mark the output file as PIC. | |
71 | ||
72 | @item -mvxworks-pic | |
73 | @cindex @option{-mvxworks-pic} option, MIPS | |
74 | Generate VxWorks PIC. This option tells the assembler to generate | |
75 | VxWorks-style position-independent macro expansions. | |
76 | ||
252b5132 RH |
77 | @cindex MIPS architecture options |
78 | @item -mips1 | |
79 | @itemx -mips2 | |
80 | @itemx -mips3 | |
81 | @itemx -mips4 | |
b1929900 | 82 | @itemx -mips5 |
e7af610e | 83 | @itemx -mips32 |
af7ee8bf | 84 | @itemx -mips32r2 |
ae52f483 AB |
85 | @itemx -mips32r3 |
86 | @itemx -mips32r5 | |
7361da2c | 87 | @itemx -mips32r6 |
84ea6cf2 | 88 | @itemx -mips64 |
5f74bc13 | 89 | @itemx -mips64r2 |
ae52f483 AB |
90 | @itemx -mips64r3 |
91 | @itemx -mips64r5 | |
7361da2c | 92 | @itemx -mips64r6 |
252b5132 | 93 | Generate code for a particular MIPS Instruction Set Architecture level. |
98508b2a RS |
94 | @samp{-mips1} corresponds to the R2000 and R3000 processors, |
95 | @samp{-mips2} to the R6000 processor, @samp{-mips3} to the | |
81566a9b | 96 | R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. |
7361da2c AB |
97 | @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, |
98 | @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, | |
99 | @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to | |
100 | generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 | |
101 | Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 | |
102 | Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, | |
103 | respectively. You can also switch instruction sets during the assembly; | |
104 | see @ref{MIPS ISA, Directives to override the ISA level}. | |
252b5132 | 105 | |
6349b5f4 | 106 | @item -mgp32 |
ca4e0257 RS |
107 | @itemx -mfp32 |
108 | Some macros have different expansions for 32-bit and 64-bit registers. | |
109 | The register sizes are normally inferred from the ISA and ABI, but these | |
110 | flags force a certain group of registers to be treated as 32 bits wide at | |
111 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
112 | and @samp{-mfp32} controls the size of floating-point registers. | |
113 | ||
ad3fea08 TS |
114 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
115 | of registers to be changed for parts of an object. The default value is | |
116 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
117 | ||
ca4e0257 RS |
118 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
119 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
120 | save the 32-bit registers on a context switch, so it is essential never | |
121 | to use the 64-bit registers. | |
6349b5f4 AH |
122 | |
123 | @item -mgp64 | |
ad3fea08 TS |
124 | @itemx -mfp64 |
125 | Assume that 64-bit registers are available. This is provided in the | |
126 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. | |
127 | ||
128 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size | |
129 | of registers to be changed for parts of an object. The default value is | |
130 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
6349b5f4 | 131 | |
351cdf24 MF |
132 | @item -mfpxx |
133 | Make no assumptions about whether 32-bit or 64-bit floating-point | |
134 | registers are available. This is provided to support having modules | |
135 | compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can | |
136 | only be used with MIPS II and above. | |
137 | ||
138 | The @code{.set fp=xx} directive allows a part of an object to be marked | |
139 | as not making assumptions about 32-bit or 64-bit FP registers. The | |
140 | default value is restored by @code{.set fp=default}. | |
141 | ||
142 | @item -modd-spreg | |
143 | @itemx -mno-odd-spreg | |
144 | Enable use of floating-point operations on odd-numbered single-precision | |
145 | registers when supported by the ISA. @samp{-mfpxx} implies | |
146 | @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} | |
147 | ||
252b5132 RH |
148 | @item -mips16 |
149 | @itemx -no-mips16 | |
150 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
32035f51 | 151 | @code{.module mips16} at the start of the assembly file. @samp{-no-mips16} |
252b5132 RH |
152 | turns off this option. |
153 | ||
25499ac7 MR |
154 | @item -mmips16e2 |
155 | @itemx -mno-mips16e2 | |
156 | Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent | |
157 | to putting @code{.module mips16e2} at the start of the assembly file. | |
158 | @samp{-mno-mips16e2} turns off this option. | |
159 | ||
df58fc94 RS |
160 | @item -mmicromips |
161 | @itemx -mno-micromips | |
162 | Generate code for the microMIPS processor. This is equivalent to putting | |
32035f51 MR |
163 | @code{.module micromips} at the start of the assembly file. |
164 | @samp{-mno-micromips} turns off this option. This is equivalent to putting | |
165 | @code{.module nomicromips} at the start of the assembly file. | |
df58fc94 | 166 | |
e16bfa71 TS |
167 | @item -msmartmips |
168 | @itemx -mno-smartmips | |
169 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which | |
170 | provides a number of new instructions which target smartcard and | |
171 | cryptographic applications. This is equivalent to putting | |
32035f51 | 172 | @code{.module smartmips} at the start of the assembly file. |
e16bfa71 TS |
173 | @samp{-mno-smartmips} turns off this option. |
174 | ||
1f25f5d3 CD |
175 | @item -mips3d |
176 | @itemx -no-mips3d | |
177 | Generate code for the MIPS-3D Application Specific Extension. | |
178 | This tells the assembler to accept MIPS-3D instructions. | |
179 | @samp{-no-mips3d} turns off this option. | |
180 | ||
deec1734 CD |
181 | @item -mdmx |
182 | @itemx -no-mdmx | |
183 | Generate code for the MDMX Application Specific Extension. | |
184 | This tells the assembler to accept MDMX instructions. | |
185 | @samp{-no-mdmx} turns off this option. | |
186 | ||
2ef2b9ae CF |
187 | @item -mdsp |
188 | @itemx -mno-dsp | |
8b082fb1 TS |
189 | Generate code for the DSP Release 1 Application Specific Extension. |
190 | This tells the assembler to accept DSP Release 1 instructions. | |
2ef2b9ae CF |
191 | @samp{-mno-dsp} turns off this option. |
192 | ||
8b082fb1 TS |
193 | @item -mdspr2 |
194 | @itemx -mno-dspr2 | |
195 | Generate code for the DSP Release 2 Application Specific Extension. | |
8f4f9071 | 196 | This option implies @samp{-mdsp}. |
8b082fb1 TS |
197 | This tells the assembler to accept DSP Release 2 instructions. |
198 | @samp{-mno-dspr2} turns off this option. | |
199 | ||
8f4f9071 MF |
200 | @item -mdspr3 |
201 | @itemx -mno-dspr3 | |
202 | Generate code for the DSP Release 3 Application Specific Extension. | |
203 | This option implies @samp{-mdsp} and @samp{-mdspr2}. | |
204 | This tells the assembler to accept DSP Release 3 instructions. | |
205 | @samp{-mno-dspr3} turns off this option. | |
206 | ||
ef2e4d86 CF |
207 | @item -mmt |
208 | @itemx -mno-mt | |
209 | Generate code for the MT Application Specific Extension. | |
210 | This tells the assembler to accept MT instructions. | |
211 | @samp{-mno-mt} turns off this option. | |
212 | ||
dec0624d MR |
213 | @item -mmcu |
214 | @itemx -mno-mcu | |
215 | Generate code for the MCU Application Specific Extension. | |
216 | This tells the assembler to accept MCU instructions. | |
217 | @samp{-mno-mcu} turns off this option. | |
218 | ||
56d438b1 CF |
219 | @item -mmsa |
220 | @itemx -mno-msa | |
221 | Generate code for the MIPS SIMD Architecture Extension. | |
222 | This tells the assembler to accept MSA instructions. | |
223 | @samp{-mno-msa} turns off this option. | |
224 | ||
7d64c587 AB |
225 | @item -mxpa |
226 | @itemx -mno-xpa | |
227 | Generate code for the MIPS eXtended Physical Address (XPA) Extension. | |
228 | This tells the assembler to accept XPA instructions. | |
229 | @samp{-mno-xpa} turns off this option. | |
230 | ||
b015e599 AP |
231 | @item -mvirt |
232 | @itemx -mno-virt | |
233 | Generate code for the Virtualization Application Specific Extension. | |
234 | This tells the assembler to accept Virtualization instructions. | |
235 | @samp{-mno-virt} turns off this option. | |
236 | ||
730c3174 SE |
237 | @item -mcrc |
238 | @itemx -mno-crc | |
239 | Generate code for the cyclic redundancy check (CRC) Application Specific | |
240 | Extension. This tells the assembler to accept CRC instructions. | |
241 | @samp{-mno-crc} turns off this option. | |
242 | ||
6f20c942 FS |
243 | @item -mginv |
244 | @itemx -mno-ginv | |
245 | Generate code for the Global INValidate (GINV) Application Specific | |
246 | Extension. This tells the assembler to accept GINV instructions. | |
247 | @samp{-mno-ginv} turns off this option. | |
248 | ||
8095d2f7 CX |
249 | @item -mloongson-mmi |
250 | @itemx -mno-loongson-mmi | |
251 | Generate code for the Loongson MultiMedia extensions Instructions (MMI) | |
252 | Application Specific Extension. This tells the assembler to accept MMI | |
253 | instructions. | |
254 | @samp{-mno-loongson-mmi} turns off this option. | |
255 | ||
833794fc MR |
256 | @item -minsn32 |
257 | @itemx -mno-insn32 | |
258 | Only use 32-bit instruction encodings when generating code for the | |
259 | microMIPS processor. This option inhibits the use of any 16-bit | |
260 | instructions. This is equivalent to putting @code{.set insn32} at | |
261 | the start of the assembly file. @samp{-mno-insn32} turns off this | |
262 | option. This is equivalent to putting @code{.set noinsn32} at the | |
263 | start of the assembly file. By default @samp{-mno-insn32} is | |
264 | selected, allowing all instructions to be used. | |
265 | ||
6b76fefe | 266 | @item -mfix7000 |
9ee72ff1 | 267 | @itemx -mno-fix7000 |
6b76fefe CM |
268 | Cause nops to be inserted if the read of the destination register |
269 | of an mfhi or mflo instruction occurs in the following two instructions. | |
270 | ||
a8d14a88 CM |
271 | @item -mfix-rm7000 |
272 | @itemx -mno-fix-rm7000 | |
273 | Cause nops to be inserted if a dmult or dmultu instruction is | |
274 | followed by a load instruction. | |
275 | ||
c67a084a NC |
276 | @item -mfix-loongson2f-jump |
277 | @itemx -mno-fix-loongson2f-jump | |
278 | Eliminate instruction fetch from outside 256M region to work around the | |
279 | Loongson2F @samp{jump} instructions. Without it, under extreme cases, | |
280 | the kernel may crash. The issue has been solved in latest processor | |
281 | batches, but this fix has no side effect to them. | |
282 | ||
283 | @item -mfix-loongson2f-nop | |
284 | @itemx -mno-fix-loongson2f-nop | |
285 | Replace nops by @code{or at,at,zero} to work around the Loongson2F | |
98508b2a RS |
286 | @samp{nop} errata. Without it, under extreme cases, the CPU might |
287 | deadlock. The issue has been solved in later Loongson2F batches, but | |
c67a084a NC |
288 | this fix has no side effect to them. |
289 | ||
d766e8ec | 290 | @item -mfix-vr4120 |
2babba43 | 291 | @itemx -mno-fix-vr4120 |
d766e8ec RS |
292 | Insert nops to work around certain VR4120 errata. This option is |
293 | intended to be used on GCC-generated code: it is not designed to catch | |
294 | all problems in hand-written assembler code. | |
60b63b72 | 295 | |
11db99f8 | 296 | @item -mfix-vr4130 |
2babba43 | 297 | @itemx -mno-fix-vr4130 |
11db99f8 RS |
298 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
299 | ||
6a32d874 | 300 | @item -mfix-24k |
45e279f5 | 301 | @itemx -mno-fix-24k |
6a32d874 CM |
302 | Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. |
303 | ||
d954098f DD |
304 | @item -mfix-cn63xxp1 |
305 | @itemx -mno-fix-cn63xxp1 | |
306 | Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around | |
307 | certain CN63XXP1 errata. | |
308 | ||
252b5132 RH |
309 | @item -m4010 |
310 | @itemx -no-m4010 | |
98508b2a RS |
311 | Generate code for the LSI R4010 chip. This tells the assembler to |
312 | accept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, | |
252b5132 RH |
313 | etc.), and to not schedule @samp{nop} instructions around accesses to |
314 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
315 | option. | |
316 | ||
317 | @item -m4650 | |
318 | @itemx -no-m4650 | |
98508b2a | 319 | Generate code for the MIPS R4650 chip. This tells the assembler to accept |
252b5132 RH |
320 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
321 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
322 | @samp{-no-m4650} turns off this option. | |
323 | ||
a4ac1c42 | 324 | @item -m3900 |
252b5132 RH |
325 | @itemx -no-m3900 |
326 | @itemx -m4100 | |
327 | @itemx -no-m4100 | |
328 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
98508b2a | 329 | R@var{nnnn} chip. This tells the assembler to accept instructions |
252b5132 RH |
330 | specific to that chip, and to schedule for that chip's hazards. |
331 | ||
ec68c924 | 332 | @item -march=@var{cpu} |
98508b2a | 333 | Generate code for a particular MIPS CPU. It is exactly equivalent to |
252b5132 RH |
334 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
335 | understood. Valid @var{cpu} value are: | |
336 | ||
337 | @quotation | |
338 | 2000, | |
339 | 3000, | |
340 | 3900, | |
341 | 4000, | |
342 | 4010, | |
343 | 4100, | |
344 | 4111, | |
60b63b72 RS |
345 | vr4120, |
346 | vr4130, | |
347 | vr4181, | |
252b5132 RH |
348 | 4300, |
349 | 4400, | |
350 | 4600, | |
351 | 4650, | |
352 | 5000, | |
b946ec34 NC |
353 | rm5200, |
354 | rm5230, | |
355 | rm5231, | |
356 | rm5261, | |
357 | rm5721, | |
60b63b72 RS |
358 | vr5400, |
359 | vr5500, | |
252b5132 | 360 | 6000, |
b946ec34 | 361 | rm7000, |
252b5132 | 362 | 8000, |
963ac363 | 363 | rm9000, |
e7af610e | 364 | 10000, |
18ae5d72 | 365 | 12000, |
3aa3176b TS |
366 | 14000, |
367 | 16000, | |
ad3fea08 TS |
368 | 4kc, |
369 | 4km, | |
370 | 4kp, | |
371 | 4ksc, | |
372 | 4kec, | |
373 | 4kem, | |
374 | 4kep, | |
375 | 4ksd, | |
376 | m4k, | |
377 | m4kp, | |
b5503c7b MR |
378 | m14k, |
379 | m14kc, | |
7a795ef4 MR |
380 | m14ke, |
381 | m14kec, | |
ad3fea08 | 382 | 24kc, |
0fdf1951 | 383 | 24kf2_1, |
ad3fea08 | 384 | 24kf, |
0fdf1951 | 385 | 24kf1_1, |
ad3fea08 | 386 | 24kec, |
0fdf1951 | 387 | 24kef2_1, |
ad3fea08 | 388 | 24kef, |
0fdf1951 | 389 | 24kef1_1, |
ad3fea08 | 390 | 34kc, |
0fdf1951 | 391 | 34kf2_1, |
ad3fea08 | 392 | 34kf, |
0fdf1951 | 393 | 34kf1_1, |
711eefe4 | 394 | 34kn, |
f281862d | 395 | 74kc, |
0fdf1951 | 396 | 74kf2_1, |
f281862d | 397 | 74kf, |
0fdf1951 RS |
398 | 74kf1_1, |
399 | 74kf3_2, | |
30f8113a SL |
400 | 1004kc, |
401 | 1004kf2_1, | |
402 | 1004kf, | |
403 | 1004kf1_1, | |
77403ce9 | 404 | interaptiv, |
38bf472a | 405 | interaptiv-mr2, |
c6e5c03a RS |
406 | m5100, |
407 | m5101, | |
bbaa46c0 | 408 | p5600, |
ad3fea08 TS |
409 | 5kc, |
410 | 5kf, | |
411 | 20kc, | |
412 | 25kf, | |
82100185 | 413 | sb1, |
350cc38d | 414 | sb1a, |
7ef0d297 | 415 | i6400, |
a4968f42 | 416 | p6600, |
350cc38d | 417 | loongson2e, |
037b32b9 | 418 | loongson2f, |
fd503541 | 419 | loongson3a, |
52b6b6b9 | 420 | octeon, |
dd6a37e7 | 421 | octeon+, |
432233b3 | 422 | octeon2, |
2c629856 | 423 | octeon3, |
55a36193 MK |
424 | xlr, |
425 | xlp | |
252b5132 RH |
426 | @end quotation |
427 | ||
0fdf1951 RS |
428 | For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are |
429 | accepted as synonyms for @samp{@var{n}f1_1}. These values are | |
430 | deprecated. | |
431 | ||
ec68c924 | 432 | @item -mtune=@var{cpu} |
98508b2a | 433 | Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are |
ec68c924 EC |
434 | identical to @samp{-march=@var{cpu}}. |
435 | ||
316f5878 RS |
436 | @item -mabi=@var{abi} |
437 | Record which ABI the source code uses. The recognized arguments | |
438 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
252b5132 | 439 | |
aed1a261 RS |
440 | @item -msym32 |
441 | @itemx -mno-sym32 | |
442 | @cindex -msym32 | |
443 | @cindex -mno-sym32 | |
444 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to | |
5a7560b5 | 445 | the beginning of the assembler input. @xref{MIPS Symbol Sizes}. |
aed1a261 | 446 | |
252b5132 RH |
447 | @cindex @code{-nocpp} ignored (MIPS) |
448 | @item -nocpp | |
449 | This option is ignored. It is accepted for command-line compatibility with | |
450 | other assemblers, which use it to turn off C style preprocessing. With | |
451 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
452 | @sc{gnu} assembler itself never runs the C preprocessor. | |
453 | ||
037b32b9 AN |
454 | @item -msoft-float |
455 | @itemx -mhard-float | |
456 | Disable or enable floating-point instructions. Note that by default | |
457 | floating-point instructions are always allowed even with CPU targets | |
458 | that don't have support for these instructions. | |
459 | ||
460 | @item -msingle-float | |
461 | @itemx -mdouble-float | |
462 | Disable or enable double-precision floating-point operations. Note | |
463 | that by default double-precision floating-point operations are always | |
464 | allowed even with CPU targets that don't have support for these | |
465 | operations. | |
466 | ||
119d663a NC |
467 | @item --construct-floats |
468 | @itemx --no-construct-floats | |
119d663a NC |
469 | The @code{--no-construct-floats} option disables the construction of |
470 | double width floating point constants by loading the two halves of the | |
471 | value into the two single width floating point registers that make up | |
472 | the double width register. This feature is useful if the processor | |
473 | support the FR bit in its status register, and this bit is known (by | |
474 | the programmer) to be set. This bit prevents the aliasing of the double | |
475 | width register by the single width registers. | |
476 | ||
63bf5651 | 477 | By default @code{--construct-floats} is selected, allowing construction |
119d663a NC |
478 | of these floating point constants. |
479 | ||
3bf0dbfb MR |
480 | @item --relax-branch |
481 | @itemx --no-relax-branch | |
482 | The @samp{--relax-branch} option enables the relaxation of out-of-range | |
483 | branches. Any branches whose target cannot be reached directly are | |
484 | converted to a small instruction sequence including an inverse-condition | |
485 | branch to the physically next instruction, and a jump to the original | |
486 | target is inserted between the two instructions. In PIC code the jump | |
487 | will involve further instructions for address calculation. | |
488 | ||
489 | The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, | |
490 | @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from | |
491 | relaxation, because they have no complementing counterparts. They could | |
492 | be relaxed with the use of a longer sequence involving another branch, | |
493 | however this has not been implemented and if their target turns out of | |
494 | reach, they produce an error even if branch relaxation is enabled. | |
495 | ||
81566a9b | 496 | Also no MIPS16 branches are ever relaxed. |
3bf0dbfb MR |
497 | |
498 | By default @samp{--no-relax-branch} is selected, causing any out-of-range | |
499 | branches to produce an error. | |
500 | ||
8b10b0b3 MR |
501 | @item -mignore-branch-isa |
502 | @itemx -mno-ignore-branch-isa | |
503 | Ignore branch checks for invalid transitions between ISA modes. | |
504 | ||
505 | The semantics of branches does not provide for an ISA mode switch, so in | |
506 | most cases the ISA mode a branch has been encoded for has to be the same | |
507 | as the ISA mode of the branch's target label. If the ISA modes do not | |
508 | match, then such a branch, if taken, will cause the ISA mode to remain | |
509 | unchanged and instructions that follow will be executed in the wrong ISA | |
510 | mode causing the program to misbehave or crash. | |
511 | ||
512 | In the case of the @code{BAL} instruction it may be possible to relax | |
513 | it to an equivalent @code{JALX} instruction so that the ISA mode is | |
514 | switched at the run time as required. For other branches no relaxation | |
515 | is possible and therefore GAS has checks implemented that verify in | |
516 | branch assembly that the two ISA modes match, and report an error | |
517 | otherwise so that the problem with code can be diagnosed at the assembly | |
518 | time rather than at the run time. | |
519 | ||
520 | However some assembly code, including generated code produced by some | |
521 | versions of GCC, may incorrectly include branches to data labels, which | |
522 | appear to require a mode switch but are either dead or immediately | |
523 | followed by valid instructions encoded for the same ISA the branch has | |
524 | been encoded for. While not strictly correct at the source level such | |
525 | code will execute as intended, so to help with these cases | |
526 | @samp{-mignore-branch-isa} is supported which disables ISA mode checks | |
527 | for branches. | |
528 | ||
529 | By default @samp{-mno-ignore-branch-isa} is selected, causing any invalid | |
530 | branch requiring a transition between ISA modes to produce an error. | |
531 | ||
a05a5b64 | 532 | @cindex @option{-mnan=} command-line option, MIPS |
ba92f887 MR |
533 | @item -mnan=@var{encoding} |
534 | This option indicates whether the source code uses the IEEE 2008 | |
535 | NaN encoding (@option{-mnan=2008}) or the original MIPS encoding | |
536 | (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} | |
537 | directive to the beginning of the source file. @xref{MIPS NaN Encodings}. | |
538 | ||
539 | @option{-mnan=legacy} is the default if no @option{-mnan} option or | |
540 | @code{.nan} directive is used. | |
541 | ||
252b5132 RH |
542 | @item --trap |
543 | @itemx --no-break | |
544 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
545 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
546 | @code{@value{AS}} automatically macro expands certain division and | |
547 | multiplication instructions to check for overflow and division by zero. This | |
548 | option causes @code{@value{AS}} to generate code to take a trap exception | |
549 | rather than a break exception when an error is detected. The trap instructions | |
550 | are only supported at Instruction Set Architecture level 2 and higher. | |
551 | ||
552 | @item --break | |
553 | @itemx --no-trap | |
554 | Generate code to take a break exception rather than a trap exception when an | |
555 | error is detected. This is the default. | |
63486801 | 556 | |
dcd410fe RO |
557 | @item -mpdr |
558 | @itemx -mno-pdr | |
559 | Control generation of @code{.pdr} sections. Off by default on IRIX, on | |
560 | elsewhere. | |
aa6975fb ILT |
561 | |
562 | @item -mshared | |
563 | @itemx -mno-shared | |
564 | When generating code using the Unix calling conventions (selected by | |
565 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code | |
566 | which can go into a shared library. The @samp{-mno-shared} option | |
567 | tells gas to generate code which uses the calling convention, but can | |
568 | not go into a shared library. The resulting code is slightly more | |
569 | efficient. This option only affects the handling of the | |
570 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. | |
252b5132 RH |
571 | @end table |
572 | ||
fc16f8cc RS |
573 | @node MIPS Macros |
574 | @section High-level assembly macros | |
575 | ||
576 | MIPS assemblers have traditionally provided a wider range of | |
577 | instructions than the MIPS architecture itself. These extra | |
578 | instructions are usually referred to as ``macro'' instructions | |
579 | @footnote{The term ``macro'' is somewhat overloaded here, since | |
580 | these macros have no relation to those defined by @code{.macro}, | |
581 | @pxref{Macro,, @code{.macro}}.}. | |
582 | ||
583 | Some MIPS macro instructions extend an underlying architectural instruction | |
584 | while others are entirely new. An example of the former type is @code{and}, | |
585 | which allows the third operand to be either a register or an arbitrary | |
586 | immediate value. Examples of the latter type include @code{bgt}, which | |
587 | branches to the third operand when the first operand is greater than | |
588 | the second operand, and @code{ulh}, which implements an unaligned | |
589 | 2-byte load. | |
590 | ||
591 | One of the most common extensions provided by macros is to expand | |
592 | memory offsets to the full address range (32 or 64 bits) and to allow | |
593 | symbolic offsets such as @samp{my_data + 4} to be used in place of | |
594 | integer constants. For example, the architectural instruction | |
595 | @code{lbu} allows only a signed 16-bit offset, whereas the macro | |
596 | @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. | |
597 | The implementation of these symbolic offsets depends on several factors, | |
98508b2a RS |
598 | such as whether the assembler is generating SVR4-style PIC (selected by |
599 | @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols | |
fc16f8cc RS |
600 | (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), |
601 | and the small data limit (@pxref{MIPS Small Data,, Controlling the use | |
602 | of small data accesses}). | |
603 | ||
604 | @kindex @code{.set macro} | |
605 | @kindex @code{.set nomacro} | |
606 | Sometimes it is undesirable to have one assembly instruction expand | |
607 | to several machine instructions. The directive @code{.set nomacro} | |
608 | tells the assembler to warn when this happens. @code{.set macro} | |
609 | restores the default behavior. | |
610 | ||
611 | @cindex @code{at} register, MIPS | |
612 | @kindex @code{.set at=@var{reg}} | |
613 | Some macro instructions need a temporary register to store intermediate | |
614 | results. This register is usually @code{$1}, also known as @code{$at}, | |
615 | but it can be changed to any core register @var{reg} using | |
616 | @code{.set at=@var{reg}}. Note that @code{$at} always refers | |
617 | to @code{$1} regardless of which register is being used as the | |
618 | temporary register. | |
619 | ||
620 | @kindex @code{.set at} | |
621 | @kindex @code{.set noat} | |
622 | Implicit uses of the temporary register in macros could interfere with | |
623 | explicit uses in the assembly code. The assembler therefore warns | |
624 | whenever it sees an explicit use of the temporary register. The directive | |
625 | @code{.set noat} silences this warning while @code{.set at} restores | |
626 | the default behavior. It is safe to use @code{.set noat} while | |
627 | @code{.set nomacro} is in effect since single-instruction macros | |
628 | never need a temporary register. | |
629 | ||
630 | Note that while the @sc{gnu} assembler provides these macros for compatibility, | |
631 | it does not make any attempt to optimize them with the surrounding code. | |
632 | ||
5a7560b5 | 633 | @node MIPS Symbol Sizes |
aed1a261 RS |
634 | @section Directives to override the size of symbols |
635 | ||
5a7560b5 RS |
636 | @kindex @code{.set sym32} |
637 | @kindex @code{.set nosym32} | |
aed1a261 RS |
638 | The n64 ABI allows symbols to have any 64-bit value. Although this |
639 | provides a great deal of flexibility, it means that some macros have | |
640 | much longer expansions than their 32-bit counterparts. For example, | |
641 | the non-PIC expansion of @samp{dla $4,sym} is usually: | |
642 | ||
643 | @smallexample | |
644 | lui $4,%highest(sym) | |
645 | lui $1,%hi(sym) | |
646 | daddiu $4,$4,%higher(sym) | |
647 | daddiu $1,$1,%lo(sym) | |
648 | dsll32 $4,$4,0 | |
649 | daddu $4,$4,$1 | |
650 | @end smallexample | |
651 | ||
652 | whereas the 32-bit expansion is simply: | |
653 | ||
654 | @smallexample | |
655 | lui $4,%hi(sym) | |
656 | daddiu $4,$4,%lo(sym) | |
657 | @end smallexample | |
658 | ||
659 | n64 code is sometimes constructed in such a way that all symbolic | |
660 | constants are known to have 32-bit values, and in such cases, it's | |
661 | preferable to use the 32-bit expansion instead of the 64-bit | |
662 | expansion. | |
663 | ||
664 | You can use the @code{.set sym32} directive to tell the assembler | |
665 | that, from this point on, all expressions of the form | |
666 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} | |
667 | have 32-bit values. For example: | |
668 | ||
669 | @smallexample | |
670 | .set sym32 | |
671 | dla $4,sym | |
672 | lw $4,sym+16 | |
673 | sw $4,sym+0x8000($4) | |
674 | @end smallexample | |
675 | ||
676 | will cause the assembler to treat @samp{sym}, @code{sym+16} and | |
677 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic | |
678 | addresses is not affected. | |
679 | ||
680 | The directive @code{.set nosym32} ends a @code{.set sym32} block and | |
681 | reverts to the normal behavior. It is also possible to change the | |
682 | symbol size using the command-line options @option{-msym32} and | |
683 | @option{-mno-sym32}. | |
684 | ||
685 | These options and directives are always accepted, but at present, | |
686 | they have no effect for anything other than n64. | |
687 | ||
fc16f8cc RS |
688 | @node MIPS Small Data |
689 | @section Controlling the use of small data accesses | |
5a7560b5 | 690 | |
fc16f8cc RS |
691 | @c This section deliberately glosses over the possibility of using -G |
692 | @c in SVR4-style PIC, as could be done on IRIX. We don't support that. | |
693 | @cindex small data, MIPS | |
5a7560b5 | 694 | @cindex @code{gp} register, MIPS |
fc16f8cc RS |
695 | It often takes several instructions to load the address of a symbol. |
696 | For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion | |
697 | of @samp{dla $4,addr} is usually: | |
698 | ||
699 | @smallexample | |
700 | lui $4,%hi(addr) | |
701 | daddiu $4,$4,%lo(addr) | |
702 | @end smallexample | |
703 | ||
704 | The sequence is much longer when @samp{addr} is a 64-bit symbol. | |
705 | @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. | |
706 | ||
707 | In order to cut down on this overhead, most embedded MIPS systems | |
708 | set aside a 64-kilobyte ``small data'' area and guarantee that all | |
709 | data of size @var{n} and smaller will be placed in that area. | |
710 | The limit @var{n} is passed to both the assembler and the linker | |
98508b2a | 711 | using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, |
fc16f8cc RS |
712 | Assembler options}. Note that the same value of @var{n} must be used |
713 | when linking and when assembling all input files to the link; any | |
714 | inconsistency could cause a relocation overflow error. | |
715 | ||
716 | The size of an object in the @code{.bss} section is set by the | |
717 | @code{.comm} or @code{.lcomm} directive that defines it. The size of | |
718 | an external object may be set with the @code{.extern} directive. For | |
719 | example, @samp{.extern sym,4} declares that the object at @code{sym} | |
720 | is 4 bytes in length, while leaving @code{sym} otherwise undefined. | |
721 | ||
722 | When no @option{-G} option is given, the default limit is 8 bytes. | |
723 | The option @option{-G 0} prevents any data from being automatically | |
724 | classified as small. | |
725 | ||
726 | It is also possible to mark specific objects as small by putting them | |
727 | in the special sections @code{.sdata} and @code{.sbss}, which are | |
728 | ``small'' counterparts of @code{.data} and @code{.bss} respectively. | |
729 | The toolchain will treat such data as small regardless of the | |
730 | @option{-G} setting. | |
731 | ||
732 | On startup, systems that support a small data area are expected to | |
733 | initialize register @code{$28}, also known as @code{$gp}, in such a | |
734 | way that small data can be accessed using a 16-bit offset from that | |
735 | register. For example, when @samp{addr} is small data, | |
736 | the @samp{dla $4,addr} instruction above is equivalent to: | |
737 | ||
738 | @smallexample | |
739 | daddiu $4,$28,%gp_rel(addr) | |
740 | @end smallexample | |
741 | ||
742 | Small data is not supported for SVR4-style PIC. | |
5a7560b5 | 743 | |
252b5132 RH |
744 | @node MIPS ISA |
745 | @section Directives to override the ISA level | |
746 | ||
747 | @cindex MIPS ISA override | |
748 | @kindex @code{.set mips@var{n}} | |
749 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
98508b2a | 750 | the MIPS Instruction Set Architecture level on the fly: @code{.set |
ae52f483 | 751 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, |
7361da2c | 752 | 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. |
071742cf | 753 | The values other than 0 make the assembler accept instructions |
e335d9cb | 754 | for the corresponding ISA level, from that point on in the |
584da044 NC |
755 | assembly. @code{.set mips@var{n}} affects not only which instructions |
756 | are permitted, but also how certain macros are expanded. @code{.set | |
e335d9cb | 757 | mips0} restores the ISA level to its original level: either the |
a05a5b64 | 758 | level you selected with command-line options, or the default for your |
81566a9b | 759 | configuration. You can use this feature to permit specific MIPS III |
584da044 | 760 | instructions while assembling in 32 bit mode. Use this directive with |
ec68c924 | 761 | care! |
252b5132 | 762 | |
ad3fea08 TS |
763 | @cindex MIPS CPU override |
764 | @kindex @code{.set arch=@var{cpu}} | |
765 | The @code{.set arch=@var{cpu}} directive provides even finer control. | |
766 | It changes the effective CPU target and allows the assembler to use | |
767 | instructions specific to a particular CPU. All CPUs supported by the | |
a05a5b64 | 768 | @samp{-march} command-line option are also selectable by this directive. |
ad3fea08 | 769 | The original value is restored by @code{.set arch=default}. |
252b5132 | 770 | |
ad3fea08 TS |
771 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
772 | in which it will assemble instructions for the MIPS 16 processor. Use | |
773 | @code{.set nomips16} to return to normal 32 bit mode. | |
e16bfa71 | 774 | |
98508b2a | 775 | Traditional MIPS assemblers do not support this directive. |
252b5132 | 776 | |
df58fc94 RS |
777 | The directive @code{.set micromips} puts the assembler into microMIPS mode, |
778 | in which it will assemble instructions for the microMIPS processor. Use | |
779 | @code{.set nomicromips} to return to normal 32 bit mode. | |
780 | ||
98508b2a | 781 | Traditional MIPS assemblers do not support this directive. |
df58fc94 | 782 | |
833794fc MR |
783 | @node MIPS assembly options |
784 | @section Directives to control code generation | |
785 | ||
a05a5b64 | 786 | @cindex MIPS directives to override command-line options |
919731af | 787 | @kindex @code{.module} |
a05a5b64 | 788 | The @code{.module} directive allows command-line options to be set directly |
919731af | 789 | from assembly. The format of the directive matches the @code{.set} |
790 | directive but only those options which are relevant to a whole module are | |
791 | supported. The effect of a @code{.module} directive is the same as the | |
a05a5b64 | 792 | corresponding command-line option. Where @code{.set} directives support |
919731af | 793 | returning to a default then the @code{.module} directives do not as they |
794 | define the defaults. | |
795 | ||
796 | These module-level directives must appear first in assembly. | |
797 | ||
798 | Traditional MIPS assemblers do not support this directive. | |
799 | ||
833794fc MR |
800 | @cindex MIPS 32-bit microMIPS instruction generation override |
801 | @kindex @code{.set insn32} | |
802 | @kindex @code{.set noinsn32} | |
803 | The directive @code{.set insn32} makes the assembler only use 32-bit | |
804 | instruction encodings when generating code for the microMIPS processor. | |
805 | This directive inhibits the use of any 16-bit instructions from that | |
806 | point on in the assembly. The @code{.set noinsn32} directive allows | |
807 | 16-bit instructions to be accepted. | |
808 | ||
809 | Traditional MIPS assemblers do not support this directive. | |
810 | ||
252b5132 RH |
811 | @node MIPS autoextend |
812 | @section Directives for extending MIPS 16 bit instructions | |
813 | ||
814 | @kindex @code{.set autoextend} | |
815 | @kindex @code{.set noautoextend} | |
816 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
ad3fea08 TS |
817 | when necessary. The directive @code{.set noautoextend} will turn this |
818 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction | |
819 | must be explicitly extended with the @code{.e} modifier (e.g., | |
820 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used | |
252b5132 RH |
821 | to once again automatically extend instructions when necessary. |
822 | ||
823 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
98508b2a | 824 | MIPS assemblers do not support this directive. |
252b5132 RH |
825 | |
826 | @node MIPS insn | |
827 | @section Directive to mark data as an instruction | |
828 | ||
829 | @kindex @code{.insn} | |
830 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
df58fc94 RS |
831 | data is actually instructions. This makes a difference in MIPS 16 and |
832 | microMIPS modes: when loading the address of a label which precedes | |
833 | instructions, @code{@value{AS}} automatically adds 1 to the value, so | |
834 | that jumping to the loaded address will do the right thing. | |
252b5132 | 835 | |
a946d7e3 NC |
836 | @kindex @code{.global} |
837 | The @code{.global} and @code{.globl} directives supported by | |
838 | @code{@value{AS}} will by default mark the symbol as pointing to a | |
839 | region of data not code. This means that, for example, any | |
840 | instructions following such a symbol will not be disassembled by | |
f746e6b9 | 841 | @code{objdump} as it will regard them as data. To change this |
f179c512 | 842 | behavior an optional section name can be placed after the symbol name |
a946d7e3 | 843 | in the @code{.global} directive. If this section exists and is known |
f179c512 | 844 | to be a code section, then the symbol will be marked as pointing at |
a946d7e3 NC |
845 | code not data. Ie the syntax for the directive is: |
846 | ||
847 | @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, | |
848 | ||
849 | Here is a short example: | |
850 | ||
851 | @example | |
852 | .global foo .text, bar, baz .data | |
853 | foo: | |
854 | nop | |
855 | bar: | |
856 | .word 0x0 | |
857 | baz: | |
858 | .word 0x1 | |
34bca508 | 859 | |
a946d7e3 NC |
860 | @end example |
861 | ||
351cdf24 MF |
862 | @node MIPS FP ABIs |
863 | @section Directives to control the FP ABI | |
864 | @menu | |
865 | * MIPS FP ABI History:: History of FP ABIs | |
866 | * MIPS FP ABI Variants:: Supported FP ABIs | |
867 | * MIPS FP ABI Selection:: Automatic selection of FP ABI | |
868 | * MIPS FP ABI Compatibility:: Linking different FP ABI variants | |
869 | @end menu | |
870 | ||
871 | @node MIPS FP ABI History | |
872 | @subsection History of FP ABIs | |
873 | @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS | |
874 | @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS | |
875 | The MIPS ABIs support a variety of different floating-point extensions | |
876 | where calling-convention and register sizes vary for floating-point data. | |
877 | The extensions exist to support a wide variety of optional architecture | |
878 | features. The resulting ABI variants are generally incompatible with each | |
879 | other and must be tracked carefully. | |
880 | ||
881 | Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} | |
882 | directive is used to indicate which ABI is in use by a specific module. | |
a05a5b64 | 883 | It was then left to the user to ensure that command-line options and the |
351cdf24 MF |
884 | selected ABI were compatible with some potential for inconsistencies. |
885 | ||
886 | @node MIPS FP ABI Variants | |
887 | @subsection Supported FP ABIs | |
888 | The supported floating-point ABI variants are: | |
889 | ||
890 | @table @code | |
891 | @item 0 - No floating-point | |
892 | This variant is used to indicate that floating-point is not used within | |
893 | the module at all and therefore has no impact on the ABI. This is the | |
894 | default. | |
895 | ||
896 | @item 1 - Double-precision | |
897 | This variant indicates that double-precision support is used. For 64-bit | |
898 | ABIs this means that 64-bit wide floating-point registers are required. | |
899 | For 32-bit ABIs this means that 32-bit wide floating-point registers are | |
900 | required and double-precision operations use pairs of registers. | |
901 | ||
902 | @item 2 - Single-precision | |
903 | This variant indicates that single-precision support is used. Double | |
904 | precision operations will be supported via soft-float routines. | |
905 | ||
906 | @item 3 - Soft-float | |
907 | This variant indicates that although floating-point support is used all | |
908 | operations are emulated in software. This means the ABI is modified to | |
909 | pass all floating-point data in general-purpose registers. | |
910 | ||
911 | @item 4 - Deprecated | |
912 | This variant existed as an initial attempt at supporting 64-bit wide | |
f179c512 MF |
913 | floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been |
914 | superseded by 5, 6 and 7. | |
351cdf24 MF |
915 | |
916 | @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU | |
917 | This variant is used by 32-bit ABIs to indicate that the floating-point | |
918 | code in the module has been designed to operate correctly with either | |
919 | 32-bit wide or 64-bit wide floating-point registers. Double-precision | |
920 | support is used. Only O32 currently supports this variant and requires | |
921 | a minimum architecture of MIPS II. | |
922 | ||
923 | @item 6 - Double-precision 32-bit FPU, 64-bit FPU | |
924 | This variant is used by 32-bit ABIs to indicate that the floating-point | |
925 | code in the module requires 64-bit wide floating-point registers. | |
926 | Double-precision support is used. Only O32 currently supports this | |
927 | variant and requires a minimum architecture of MIPS32r2. | |
928 | ||
929 | @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU | |
930 | This variant is used by 32-bit ABIs to indicate that the floating-point | |
931 | code in the module requires 64-bit wide floating-point registers. | |
932 | Double-precision support is used. This differs from the previous ABI | |
933 | as it restricts use of odd-numbered single-precision registers. Only | |
934 | O32 currently supports this variant and requires a minimum architecture | |
935 | of MIPS32r2. | |
936 | @end table | |
937 | ||
938 | @node MIPS FP ABI Selection | |
939 | @subsection Automatic selection of FP ABI | |
940 | @cindex @code{.module fp=@var{nn}} directive, MIPS | |
941 | In order to simplify and add safety to the process of selecting the | |
942 | correct floating-point ABI, the assembler will automatically infer the | |
a05a5b64 | 943 | correct @code{.gnu_attribute 4, @var{n}} directive based on command-line |
351cdf24 MF |
944 | options and @code{.module} overrides. Where an explicit |
945 | @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning | |
946 | will be raised if it does not match an inferred setting. | |
947 | ||
948 | The floating-point ABI is inferred as follows. If @samp{-msoft-float} | |
949 | has been used the module will be marked as soft-float. If | |
950 | @samp{-msingle-float} has been used then the module will be marked as | |
951 | single-precision. The remaining ABIs are then selected based | |
952 | on the FP register width. Double-precision is selected if the width | |
953 | of GP and FP registers match and the special double-precision variants | |
954 | for 32-bit ABIs are then selected depending on @samp{-mfpxx}, | |
955 | @samp{-mfp64} and @samp{-mno-odd-spreg}. | |
956 | ||
957 | @node MIPS FP ABI Compatibility | |
958 | @subsection Linking different FP ABI variants | |
959 | Modules using the default FP ABI (no floating-point) can be linked with | |
960 | any other (singular) FP ABI variant. | |
961 | ||
962 | Special compatibility support exists for O32 with the four | |
963 | double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically | |
964 | designed to be compatible with the standard double-precision ABI and the | |
965 | @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be | |
966 | built as @samp{-mfpxx} to ensure the maximum compatibility with other | |
967 | modules produced for more specific needs. The only FP ABIs which cannot | |
968 | be linked together are the standard double-precision ABI and the full | |
969 | @samp{-mfp64} ABI with @samp{-modd-spreg}. | |
970 | ||
ba92f887 MR |
971 | @node MIPS NaN Encodings |
972 | @section Directives to record which NaN encoding is being used | |
973 | ||
974 | @cindex MIPS IEEE 754 NaN data encoding selection | |
975 | @cindex @code{.nan} directive, MIPS | |
976 | The IEEE 754 floating-point standard defines two types of not-a-number | |
977 | (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version | |
978 | of the standard did not specify how these two types should be | |
979 | distinguished. Most implementations followed the i387 model, in which | |
980 | the first bit of the significand is set for quiet NaNs and clear for | |
981 | signalling NaNs. However, the original MIPS implementation assigned the | |
982 | opposite meaning to the bit, so that it was set for signalling NaNs and | |
983 | clear for quiet NaNs. | |
984 | ||
985 | The 2008 revision of the standard formally suggested the i387 choice | |
986 | and as from Sep 2012 the current release of the MIPS architecture | |
987 | therefore optionally supports that form. Code that uses one NaN encoding | |
988 | would usually be incompatible with code that uses the other NaN encoding, | |
989 | so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which | |
990 | encoding is being used. | |
991 | ||
992 | Assembly files can use the @code{.nan} directive to select between the | |
993 | two encodings. @samp{.nan 2008} says that the assembly file uses the | |
994 | IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses | |
995 | the original MIPS encoding. If several @code{.nan} directives are given, | |
996 | the final setting is the one that is used. | |
997 | ||
998 | The command-line options @option{-mnan=legacy} and @option{-mnan=2008} | |
999 | can be used instead of @samp{.nan legacy} and @samp{.nan 2008} | |
1000 | respectively. However, any @code{.nan} directive overrides the | |
1001 | command-line setting. | |
1002 | ||
1003 | @samp{.nan legacy} is the default if no @code{.nan} directive or | |
1004 | @option{-mnan} option is given. | |
1005 | ||
1006 | Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and | |
1007 | therefore these directives do not affect code generation. They simply | |
1008 | control the setting of the @code{EF_MIPS_NAN2008} flag. | |
1009 | ||
1010 | Traditional MIPS assemblers do not support these directives. | |
1011 | ||
98508b2a | 1012 | @node MIPS Option Stack |
252b5132 RH |
1013 | @section Directives to save and restore options |
1014 | ||
1015 | @cindex MIPS option stack | |
1016 | @kindex @code{.set push} | |
1017 | @kindex @code{.set pop} | |
1018 | The directives @code{.set push} and @code{.set pop} may be used to save | |
1019 | and restore the current settings for all the options which are | |
1020 | controlled by @code{.set}. The @code{.set push} directive saves the | |
1021 | current settings on a stack. The @code{.set pop} directive pops the | |
1022 | stack and restores the settings. | |
1023 | ||
1024 | These directives can be useful inside an macro which must change an | |
1025 | option such as the ISA level or instruction reordering but does not want | |
1026 | to change the state of the code which invoked the macro. | |
1027 | ||
98508b2a | 1028 | Traditional MIPS assemblers do not support these directives. |
1f25f5d3 | 1029 | |
98508b2a | 1030 | @node MIPS ASE Instruction Generation Overrides |
1f25f5d3 CD |
1031 | @section Directives to control generation of MIPS ASE instructions |
1032 | ||
1033 | @cindex MIPS MIPS-3D instruction generation override | |
1034 | @kindex @code{.set mips3d} | |
1035 | @kindex @code{.set nomips3d} | |
1036 | The directive @code{.set mips3d} makes the assembler accept instructions | |
1037 | from the MIPS-3D Application Specific Extension from that point on | |
1038 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
1039 | instructions from being accepted. | |
1040 | ||
ad3fea08 TS |
1041 | @cindex SmartMIPS instruction generation override |
1042 | @kindex @code{.set smartmips} | |
1043 | @kindex @code{.set nosmartmips} | |
1044 | The directive @code{.set smartmips} makes the assembler accept | |
1045 | instructions from the SmartMIPS Application Specific Extension to the | |
e335d9cb | 1046 | MIPS32 ISA from that point on in the assembly. The |
ad3fea08 TS |
1047 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from |
1048 | being accepted. | |
1049 | ||
deec1734 CD |
1050 | @cindex MIPS MDMX instruction generation override |
1051 | @kindex @code{.set mdmx} | |
1052 | @kindex @code{.set nomdmx} | |
1053 | The directive @code{.set mdmx} makes the assembler accept instructions | |
1054 | from the MDMX Application Specific Extension from that point on | |
1055 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
1056 | instructions from being accepted. | |
1057 | ||
8b082fb1 | 1058 | @cindex MIPS DSP Release 1 instruction generation override |
2ef2b9ae CF |
1059 | @kindex @code{.set dsp} |
1060 | @kindex @code{.set nodsp} | |
1061 | The directive @code{.set dsp} makes the assembler accept instructions | |
8b082fb1 TS |
1062 | from the DSP Release 1 Application Specific Extension from that point |
1063 | on in the assembly. The @code{.set nodsp} directive prevents DSP | |
1064 | Release 1 instructions from being accepted. | |
1065 | ||
1066 | @cindex MIPS DSP Release 2 instruction generation override | |
1067 | @kindex @code{.set dspr2} | |
1068 | @kindex @code{.set nodspr2} | |
1069 | The directive @code{.set dspr2} makes the assembler accept instructions | |
1070 | from the DSP Release 2 Application Specific Extension from that point | |
f179c512 | 1071 | on in the assembly. This directive implies @code{.set dsp}. The |
8b082fb1 TS |
1072 | @code{.set nodspr2} directive prevents DSP Release 2 instructions from |
1073 | being accepted. | |
2ef2b9ae | 1074 | |
8f4f9071 MF |
1075 | @cindex MIPS DSP Release 3 instruction generation override |
1076 | @kindex @code{.set dspr3} | |
1077 | @kindex @code{.set nodspr3} | |
1078 | The directive @code{.set dspr3} makes the assembler accept instructions | |
1079 | from the DSP Release 3 Application Specific Extension from that point | |
1080 | on in the assembly. This directive implies @code{.set dsp} and | |
1081 | @code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP | |
1082 | Release 3 instructions from being accepted. | |
1083 | ||
ef2e4d86 CF |
1084 | @cindex MIPS MT instruction generation override |
1085 | @kindex @code{.set mt} | |
1086 | @kindex @code{.set nomt} | |
1087 | The directive @code{.set mt} makes the assembler accept instructions | |
1088 | from the MT Application Specific Extension from that point on | |
1089 | in the assembly. The @code{.set nomt} directive prevents MT | |
1090 | instructions from being accepted. | |
1091 | ||
dec0624d MR |
1092 | @cindex MIPS MCU instruction generation override |
1093 | @kindex @code{.set mcu} | |
1094 | @kindex @code{.set nomcu} | |
1095 | The directive @code{.set mcu} makes the assembler accept instructions | |
1096 | from the MCU Application Specific Extension from that point on | |
1097 | in the assembly. The @code{.set nomcu} directive prevents MCU | |
1098 | instructions from being accepted. | |
1099 | ||
56d438b1 CF |
1100 | @cindex MIPS SIMD Architecture instruction generation override |
1101 | @kindex @code{.set msa} | |
1102 | @kindex @code{.set nomsa} | |
1103 | The directive @code{.set msa} makes the assembler accept instructions | |
1104 | from the MIPS SIMD Architecture Extension from that point on | |
1105 | in the assembly. The @code{.set nomsa} directive prevents MSA | |
1106 | instructions from being accepted. | |
1107 | ||
b015e599 AP |
1108 | @cindex Virtualization instruction generation override |
1109 | @kindex @code{.set virt} | |
1110 | @kindex @code{.set novirt} | |
1111 | The directive @code{.set virt} makes the assembler accept instructions | |
1112 | from the Virtualization Application Specific Extension from that point | |
1113 | on in the assembly. The @code{.set novirt} directive prevents Virtualization | |
1114 | instructions from being accepted. | |
1115 | ||
7d64c587 AB |
1116 | @cindex MIPS eXtended Physical Address (XPA) instruction generation override |
1117 | @kindex @code{.set xpa} | |
1118 | @kindex @code{.set noxpa} | |
1119 | The directive @code{.set xpa} makes the assembler accept instructions | |
1120 | from the XPA Extension from that point on in the assembly. The | |
1121 | @code{.set noxpa} directive prevents XPA instructions from being accepted. | |
1122 | ||
25499ac7 MR |
1123 | @cindex MIPS16e2 instruction generation override |
1124 | @kindex @code{.set mips16e2} | |
1125 | @kindex @code{.set nomips16e2} | |
1126 | The directive @code{.set mips16e2} makes the assembler accept instructions | |
1127 | from the MIPS16e2 Application Specific Extension from that point on in the | |
75c80ee1 MR |
1128 | assembly, whenever in MIPS16 mode. The @code{.set nomips16e2} directive |
1129 | prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither | |
25499ac7 MR |
1130 | directive affects the state of MIPS16 mode being active itself which has |
1131 | separate controls. | |
1132 | ||
730c3174 SE |
1133 | @cindex MIPS cyclic redundancy check (CRC) instruction generation override |
1134 | @kindex @code{.set crc} | |
1135 | @kindex @code{.set nocrc} | |
1136 | The directive @code{.set crc} makes the assembler accept instructions | |
1137 | from the CRC Extension from that point on in the assembly. The | |
1138 | @code{.set nocrc} directive prevents CRC instructions from being accepted. | |
1139 | ||
6f20c942 FS |
1140 | @cindex MIPS Global INValidate (GINV) instruction generation override |
1141 | @kindex @code{.set ginv} | |
1142 | @kindex @code{.set noginv} | |
1143 | The directive @code{.set ginv} makes the assembler accept instructions | |
1144 | from the GINV Extension from that point on in the assembly. The | |
1145 | @code{.set noginv} directive prevents GINV instructions from being accepted. | |
1146 | ||
8095d2f7 CX |
1147 | @cindex Loongson MultiMedia extensions Instructions (MMI) generation override |
1148 | @kindex @code{.set loongson-mmi} | |
1149 | @kindex @code{.set noloongson-mmi} | |
1150 | The directive @code{.set loongson-mmi} makes the assembler accept | |
1151 | instructions from the MMI Extension from that point on in the assembly. | |
1152 | The @code{.set noloongson-mmi} directive prevents MMI instructions from | |
1153 | being accepted. | |
1154 | ||
98508b2a | 1155 | Traditional MIPS assemblers do not support these directives. |
037b32b9 | 1156 | |
98508b2a | 1157 | @node MIPS Floating-Point |
037b32b9 AN |
1158 | @section Directives to override floating-point options |
1159 | ||
1160 | @cindex Disable floating-point instructions | |
1161 | @kindex @code{.set softfloat} | |
1162 | @kindex @code{.set hardfloat} | |
1163 | The directives @code{.set softfloat} and @code{.set hardfloat} provide | |
1164 | finer control of disabling and enabling float-point instructions. | |
1165 | These directives always override the default (that hard-float | |
1166 | instructions are accepted) or the command-line options | |
1167 | (@samp{-msoft-float} and @samp{-mhard-float}). | |
1168 | ||
1169 | @cindex Disable single-precision floating-point operations | |
605b1dd4 NH |
1170 | @kindex @code{.set singlefloat} |
1171 | @kindex @code{.set doublefloat} | |
037b32b9 AN |
1172 | The directives @code{.set singlefloat} and @code{.set doublefloat} |
1173 | provide finer control of disabling and enabling double-precision | |
1174 | float-point operations. These directives always override the default | |
1175 | (that double-precision operations are accepted) or the command-line | |
1176 | options (@samp{-msingle-float} and @samp{-mdouble-float}). | |
1177 | ||
98508b2a | 1178 | Traditional MIPS assemblers do not support these directives. |
7c31ae13 NC |
1179 | |
1180 | @node MIPS Syntax | |
1181 | @section Syntactical considerations for the MIPS assembler | |
1182 | @menu | |
1183 | * MIPS-Chars:: Special Characters | |
1184 | @end menu | |
1185 | ||
1186 | @node MIPS-Chars | |
1187 | @subsection Special Characters | |
1188 | ||
1189 | @cindex line comment character, MIPS | |
1190 | @cindex MIPS line comment character | |
1191 | The presence of a @samp{#} on a line indicates the start of a comment | |
1192 | that extends to the end of the current line. | |
1193 | ||
1194 | If a @samp{#} appears as the first character of a line, the whole line | |
1195 | is treated as a comment, but in this case the line can also be a | |
1196 | logical line number directive (@pxref{Comments}) or a | |
1197 | preprocessor control command (@pxref{Preprocessing}). | |
1198 | ||
1199 | @cindex line separator, MIPS | |
1200 | @cindex statement separator, MIPS | |
1201 | @cindex MIPS line separator | |
1202 | The @samp{;} character can be used to separate statements on the same | |
1203 | line. |