Commit | Line | Data |
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78849248 | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, |
a4ac1c42 | 2 | @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013 |
f7e42eb4 | 3 | @c Free Software Foundation, Inc. |
252b5132 RH |
4 | @c This is part of the GAS manual. |
5 | @c For copying conditions, see the file as.texinfo. | |
6 | @ifset GENERIC | |
7 | @page | |
8 | @node MIPS-Dependent | |
9 | @chapter MIPS Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter MIPS Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex MIPS processor | |
98508b2a RS |
17 | @sc{gnu} @code{@value{AS}} for MIPS architectures supports several |
18 | different MIPS processors, and MIPS ISA levels I through V, MIPS32, | |
19 | and MIPS64. For information about the MIPS instruction set, see | |
584da044 | 20 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
98508b2a | 21 | For an overview of MIPS assembly conventions, see ``Appendix D: |
584da044 | 22 | Assembly Language Programming'' in the same work. |
252b5132 RH |
23 | |
24 | @menu | |
98508b2a | 25 | * MIPS Options:: Assembler options |
fc16f8cc | 26 | * MIPS Macros:: High-level assembly macros |
5a7560b5 | 27 | * MIPS Symbol Sizes:: Directives to override the size of symbols |
fc16f8cc | 28 | * MIPS Small Data:: Controlling the use of small data accesses |
252b5132 | 29 | * MIPS ISA:: Directives to override the ISA level |
833794fc | 30 | * MIPS assembly options:: Directives to control code generation |
252b5132 RH |
31 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
32 | * MIPS insn:: Directive to mark data as an instruction | |
ba92f887 | 33 | * MIPS NaN Encodings:: Directives to record which NaN encoding is being used |
98508b2a RS |
34 | * MIPS Option Stack:: Directives to save and restore options |
35 | * MIPS ASE Instruction Generation Overrides:: Directives to control | |
0eb7102d | 36 | generation of MIPS ASE instructions |
98508b2a | 37 | * MIPS Floating-Point:: Directives to override floating-point options |
7c31ae13 | 38 | * MIPS Syntax:: MIPS specific syntactical considerations |
252b5132 RH |
39 | @end menu |
40 | ||
98508b2a | 41 | @node MIPS Options |
252b5132 RH |
42 | @section Assembler options |
43 | ||
98508b2a | 44 | The MIPS configurations of @sc{gnu} @code{@value{AS}} support these |
252b5132 RH |
45 | special options: |
46 | ||
47 | @table @code | |
48 | @cindex @code{-G} option (MIPS) | |
49 | @item -G @var{num} | |
fc16f8cc RS |
50 | Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. |
51 | @xref{MIPS Small Data,, Controlling the use of small data accesses}. | |
252b5132 RH |
52 | |
53 | @cindex @code{-EB} option (MIPS) | |
54 | @cindex @code{-EL} option (MIPS) | |
55 | @cindex MIPS big-endian output | |
56 | @cindex MIPS little-endian output | |
57 | @cindex big-endian output, MIPS | |
58 | @cindex little-endian output, MIPS | |
59 | @item -EB | |
60 | @itemx -EL | |
98508b2a | 61 | Any MIPS configuration of @code{@value{AS}} can select big-endian or |
252b5132 RH |
62 | little-endian output at run time (unlike the other @sc{gnu} development |
63 | tools, which must be configured for one or the other). Use @samp{-EB} | |
64 | to select big-endian output, and @samp{-EL} for little-endian. | |
65 | ||
0c000745 RS |
66 | @item -KPIC |
67 | @cindex PIC selection, MIPS | |
68 | @cindex @option{-KPIC} option, MIPS | |
69 | Generate SVR4-style PIC. This option tells the assembler to generate | |
70 | SVR4-style position-independent macro expansions. It also tells the | |
71 | assembler to mark the output file as PIC. | |
72 | ||
73 | @item -mvxworks-pic | |
74 | @cindex @option{-mvxworks-pic} option, MIPS | |
75 | Generate VxWorks PIC. This option tells the assembler to generate | |
76 | VxWorks-style position-independent macro expansions. | |
77 | ||
252b5132 RH |
78 | @cindex MIPS architecture options |
79 | @item -mips1 | |
80 | @itemx -mips2 | |
81 | @itemx -mips3 | |
82 | @itemx -mips4 | |
b1929900 | 83 | @itemx -mips5 |
e7af610e | 84 | @itemx -mips32 |
af7ee8bf | 85 | @itemx -mips32r2 |
84ea6cf2 | 86 | @itemx -mips64 |
5f74bc13 | 87 | @itemx -mips64r2 |
252b5132 | 88 | Generate code for a particular MIPS Instruction Set Architecture level. |
98508b2a RS |
89 | @samp{-mips1} corresponds to the R2000 and R3000 processors, |
90 | @samp{-mips2} to the R6000 processor, @samp{-mips3} to the | |
81566a9b MR |
91 | R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. |
92 | @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and | |
93 | @samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, | |
94 | MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also | |
95 | switch instruction sets during the assembly; see @ref{MIPS ISA, | |
96 | Directives to override the ISA level}. | |
252b5132 | 97 | |
6349b5f4 | 98 | @item -mgp32 |
ca4e0257 RS |
99 | @itemx -mfp32 |
100 | Some macros have different expansions for 32-bit and 64-bit registers. | |
101 | The register sizes are normally inferred from the ISA and ABI, but these | |
102 | flags force a certain group of registers to be treated as 32 bits wide at | |
103 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
104 | and @samp{-mfp32} controls the size of floating-point registers. | |
105 | ||
ad3fea08 TS |
106 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
107 | of registers to be changed for parts of an object. The default value is | |
108 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
109 | ||
ca4e0257 RS |
110 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
111 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
112 | save the 32-bit registers on a context switch, so it is essential never | |
113 | to use the 64-bit registers. | |
6349b5f4 AH |
114 | |
115 | @item -mgp64 | |
ad3fea08 TS |
116 | @itemx -mfp64 |
117 | Assume that 64-bit registers are available. This is provided in the | |
118 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. | |
119 | ||
120 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size | |
121 | of registers to be changed for parts of an object. The default value is | |
122 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
6349b5f4 | 123 | |
252b5132 RH |
124 | @item -mips16 |
125 | @itemx -no-mips16 | |
126 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
ad3fea08 | 127 | @code{.set mips16} at the start of the assembly file. @samp{-no-mips16} |
252b5132 RH |
128 | turns off this option. |
129 | ||
df58fc94 RS |
130 | @item -mmicromips |
131 | @itemx -mno-micromips | |
132 | Generate code for the microMIPS processor. This is equivalent to putting | |
133 | @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips} | |
134 | turns off this option. This is equivalent to putting @code{.set nomicromips} | |
135 | at the start of the assembly file. | |
136 | ||
e16bfa71 TS |
137 | @item -msmartmips |
138 | @itemx -mno-smartmips | |
139 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which | |
140 | provides a number of new instructions which target smartcard and | |
141 | cryptographic applications. This is equivalent to putting | |
ad3fea08 | 142 | @code{.set smartmips} at the start of the assembly file. |
e16bfa71 TS |
143 | @samp{-mno-smartmips} turns off this option. |
144 | ||
1f25f5d3 CD |
145 | @item -mips3d |
146 | @itemx -no-mips3d | |
147 | Generate code for the MIPS-3D Application Specific Extension. | |
148 | This tells the assembler to accept MIPS-3D instructions. | |
149 | @samp{-no-mips3d} turns off this option. | |
150 | ||
deec1734 CD |
151 | @item -mdmx |
152 | @itemx -no-mdmx | |
153 | Generate code for the MDMX Application Specific Extension. | |
154 | This tells the assembler to accept MDMX instructions. | |
155 | @samp{-no-mdmx} turns off this option. | |
156 | ||
2ef2b9ae CF |
157 | @item -mdsp |
158 | @itemx -mno-dsp | |
8b082fb1 TS |
159 | Generate code for the DSP Release 1 Application Specific Extension. |
160 | This tells the assembler to accept DSP Release 1 instructions. | |
2ef2b9ae CF |
161 | @samp{-mno-dsp} turns off this option. |
162 | ||
8b082fb1 TS |
163 | @item -mdspr2 |
164 | @itemx -mno-dspr2 | |
165 | Generate code for the DSP Release 2 Application Specific Extension. | |
166 | This option implies -mdsp. | |
167 | This tells the assembler to accept DSP Release 2 instructions. | |
168 | @samp{-mno-dspr2} turns off this option. | |
169 | ||
ef2e4d86 CF |
170 | @item -mmt |
171 | @itemx -mno-mt | |
172 | Generate code for the MT Application Specific Extension. | |
173 | This tells the assembler to accept MT instructions. | |
174 | @samp{-mno-mt} turns off this option. | |
175 | ||
dec0624d MR |
176 | @item -mmcu |
177 | @itemx -mno-mcu | |
178 | Generate code for the MCU Application Specific Extension. | |
179 | This tells the assembler to accept MCU instructions. | |
180 | @samp{-mno-mcu} turns off this option. | |
181 | ||
56d438b1 CF |
182 | @item -mmsa |
183 | @itemx -mno-msa | |
184 | Generate code for the MIPS SIMD Architecture Extension. | |
185 | This tells the assembler to accept MSA instructions. | |
186 | @samp{-mno-msa} turns off this option. | |
187 | ||
b015e599 AP |
188 | @item -mvirt |
189 | @itemx -mno-virt | |
190 | Generate code for the Virtualization Application Specific Extension. | |
191 | This tells the assembler to accept Virtualization instructions. | |
192 | @samp{-mno-virt} turns off this option. | |
193 | ||
833794fc MR |
194 | @item -minsn32 |
195 | @itemx -mno-insn32 | |
196 | Only use 32-bit instruction encodings when generating code for the | |
197 | microMIPS processor. This option inhibits the use of any 16-bit | |
198 | instructions. This is equivalent to putting @code{.set insn32} at | |
199 | the start of the assembly file. @samp{-mno-insn32} turns off this | |
200 | option. This is equivalent to putting @code{.set noinsn32} at the | |
201 | start of the assembly file. By default @samp{-mno-insn32} is | |
202 | selected, allowing all instructions to be used. | |
203 | ||
6b76fefe | 204 | @item -mfix7000 |
9ee72ff1 | 205 | @itemx -mno-fix7000 |
6b76fefe CM |
206 | Cause nops to be inserted if the read of the destination register |
207 | of an mfhi or mflo instruction occurs in the following two instructions. | |
208 | ||
a8d14a88 CM |
209 | @item -mfix-rm7000 |
210 | @itemx -mno-fix-rm7000 | |
211 | Cause nops to be inserted if a dmult or dmultu instruction is | |
212 | followed by a load instruction. | |
213 | ||
c67a084a NC |
214 | @item -mfix-loongson2f-jump |
215 | @itemx -mno-fix-loongson2f-jump | |
216 | Eliminate instruction fetch from outside 256M region to work around the | |
217 | Loongson2F @samp{jump} instructions. Without it, under extreme cases, | |
218 | the kernel may crash. The issue has been solved in latest processor | |
219 | batches, but this fix has no side effect to them. | |
220 | ||
221 | @item -mfix-loongson2f-nop | |
222 | @itemx -mno-fix-loongson2f-nop | |
223 | Replace nops by @code{or at,at,zero} to work around the Loongson2F | |
98508b2a RS |
224 | @samp{nop} errata. Without it, under extreme cases, the CPU might |
225 | deadlock. The issue has been solved in later Loongson2F batches, but | |
c67a084a NC |
226 | this fix has no side effect to them. |
227 | ||
d766e8ec | 228 | @item -mfix-vr4120 |
2babba43 | 229 | @itemx -mno-fix-vr4120 |
d766e8ec RS |
230 | Insert nops to work around certain VR4120 errata. This option is |
231 | intended to be used on GCC-generated code: it is not designed to catch | |
232 | all problems in hand-written assembler code. | |
60b63b72 | 233 | |
11db99f8 | 234 | @item -mfix-vr4130 |
2babba43 | 235 | @itemx -mno-fix-vr4130 |
11db99f8 RS |
236 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
237 | ||
6a32d874 | 238 | @item -mfix-24k |
45e279f5 | 239 | @itemx -mno-fix-24k |
6a32d874 CM |
240 | Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. |
241 | ||
d954098f DD |
242 | @item -mfix-cn63xxp1 |
243 | @itemx -mno-fix-cn63xxp1 | |
244 | Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around | |
245 | certain CN63XXP1 errata. | |
246 | ||
252b5132 RH |
247 | @item -m4010 |
248 | @itemx -no-m4010 | |
98508b2a RS |
249 | Generate code for the LSI R4010 chip. This tells the assembler to |
250 | accept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, | |
252b5132 RH |
251 | etc.), and to not schedule @samp{nop} instructions around accesses to |
252 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
253 | option. | |
254 | ||
255 | @item -m4650 | |
256 | @itemx -no-m4650 | |
98508b2a | 257 | Generate code for the MIPS R4650 chip. This tells the assembler to accept |
252b5132 RH |
258 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
259 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
260 | @samp{-no-m4650} turns off this option. | |
261 | ||
a4ac1c42 | 262 | @item -m3900 |
252b5132 RH |
263 | @itemx -no-m3900 |
264 | @itemx -m4100 | |
265 | @itemx -no-m4100 | |
266 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
98508b2a | 267 | R@var{nnnn} chip. This tells the assembler to accept instructions |
252b5132 RH |
268 | specific to that chip, and to schedule for that chip's hazards. |
269 | ||
ec68c924 | 270 | @item -march=@var{cpu} |
98508b2a | 271 | Generate code for a particular MIPS CPU. It is exactly equivalent to |
252b5132 RH |
272 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
273 | understood. Valid @var{cpu} value are: | |
274 | ||
275 | @quotation | |
276 | 2000, | |
277 | 3000, | |
278 | 3900, | |
279 | 4000, | |
280 | 4010, | |
281 | 4100, | |
282 | 4111, | |
60b63b72 RS |
283 | vr4120, |
284 | vr4130, | |
285 | vr4181, | |
252b5132 RH |
286 | 4300, |
287 | 4400, | |
288 | 4600, | |
289 | 4650, | |
290 | 5000, | |
b946ec34 NC |
291 | rm5200, |
292 | rm5230, | |
293 | rm5231, | |
294 | rm5261, | |
295 | rm5721, | |
60b63b72 RS |
296 | vr5400, |
297 | vr5500, | |
252b5132 | 298 | 6000, |
b946ec34 | 299 | rm7000, |
252b5132 | 300 | 8000, |
963ac363 | 301 | rm9000, |
e7af610e | 302 | 10000, |
18ae5d72 | 303 | 12000, |
3aa3176b TS |
304 | 14000, |
305 | 16000, | |
ad3fea08 TS |
306 | 4kc, |
307 | 4km, | |
308 | 4kp, | |
309 | 4ksc, | |
310 | 4kec, | |
311 | 4kem, | |
312 | 4kep, | |
313 | 4ksd, | |
314 | m4k, | |
315 | m4kp, | |
b5503c7b MR |
316 | m14k, |
317 | m14kc, | |
7a795ef4 MR |
318 | m14ke, |
319 | m14kec, | |
ad3fea08 | 320 | 24kc, |
0fdf1951 | 321 | 24kf2_1, |
ad3fea08 | 322 | 24kf, |
0fdf1951 | 323 | 24kf1_1, |
ad3fea08 | 324 | 24kec, |
0fdf1951 | 325 | 24kef2_1, |
ad3fea08 | 326 | 24kef, |
0fdf1951 | 327 | 24kef1_1, |
ad3fea08 | 328 | 34kc, |
0fdf1951 | 329 | 34kf2_1, |
ad3fea08 | 330 | 34kf, |
0fdf1951 | 331 | 34kf1_1, |
711eefe4 | 332 | 34kn, |
f281862d | 333 | 74kc, |
0fdf1951 | 334 | 74kf2_1, |
f281862d | 335 | 74kf, |
0fdf1951 RS |
336 | 74kf1_1, |
337 | 74kf3_2, | |
30f8113a SL |
338 | 1004kc, |
339 | 1004kf2_1, | |
340 | 1004kf, | |
341 | 1004kf1_1, | |
ad3fea08 TS |
342 | 5kc, |
343 | 5kf, | |
344 | 20kc, | |
345 | 25kf, | |
82100185 | 346 | sb1, |
350cc38d MS |
347 | sb1a, |
348 | loongson2e, | |
037b32b9 | 349 | loongson2f, |
fd503541 | 350 | loongson3a, |
52b6b6b9 | 351 | octeon, |
dd6a37e7 | 352 | octeon+, |
432233b3 | 353 | octeon2, |
55a36193 MK |
354 | xlr, |
355 | xlp | |
252b5132 RH |
356 | @end quotation |
357 | ||
0fdf1951 RS |
358 | For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are |
359 | accepted as synonyms for @samp{@var{n}f1_1}. These values are | |
360 | deprecated. | |
361 | ||
ec68c924 | 362 | @item -mtune=@var{cpu} |
98508b2a | 363 | Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are |
ec68c924 EC |
364 | identical to @samp{-march=@var{cpu}}. |
365 | ||
316f5878 RS |
366 | @item -mabi=@var{abi} |
367 | Record which ABI the source code uses. The recognized arguments | |
368 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
252b5132 | 369 | |
aed1a261 RS |
370 | @item -msym32 |
371 | @itemx -mno-sym32 | |
372 | @cindex -msym32 | |
373 | @cindex -mno-sym32 | |
374 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to | |
5a7560b5 | 375 | the beginning of the assembler input. @xref{MIPS Symbol Sizes}. |
aed1a261 | 376 | |
252b5132 RH |
377 | @cindex @code{-nocpp} ignored (MIPS) |
378 | @item -nocpp | |
379 | This option is ignored. It is accepted for command-line compatibility with | |
380 | other assemblers, which use it to turn off C style preprocessing. With | |
381 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
382 | @sc{gnu} assembler itself never runs the C preprocessor. | |
383 | ||
037b32b9 AN |
384 | @item -msoft-float |
385 | @itemx -mhard-float | |
386 | Disable or enable floating-point instructions. Note that by default | |
387 | floating-point instructions are always allowed even with CPU targets | |
388 | that don't have support for these instructions. | |
389 | ||
390 | @item -msingle-float | |
391 | @itemx -mdouble-float | |
392 | Disable or enable double-precision floating-point operations. Note | |
393 | that by default double-precision floating-point operations are always | |
394 | allowed even with CPU targets that don't have support for these | |
395 | operations. | |
396 | ||
119d663a NC |
397 | @item --construct-floats |
398 | @itemx --no-construct-floats | |
119d663a NC |
399 | The @code{--no-construct-floats} option disables the construction of |
400 | double width floating point constants by loading the two halves of the | |
401 | value into the two single width floating point registers that make up | |
402 | the double width register. This feature is useful if the processor | |
403 | support the FR bit in its status register, and this bit is known (by | |
404 | the programmer) to be set. This bit prevents the aliasing of the double | |
405 | width register by the single width registers. | |
406 | ||
63bf5651 | 407 | By default @code{--construct-floats} is selected, allowing construction |
119d663a NC |
408 | of these floating point constants. |
409 | ||
3bf0dbfb MR |
410 | @item --relax-branch |
411 | @itemx --no-relax-branch | |
412 | The @samp{--relax-branch} option enables the relaxation of out-of-range | |
413 | branches. Any branches whose target cannot be reached directly are | |
414 | converted to a small instruction sequence including an inverse-condition | |
415 | branch to the physically next instruction, and a jump to the original | |
416 | target is inserted between the two instructions. In PIC code the jump | |
417 | will involve further instructions for address calculation. | |
418 | ||
419 | The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, | |
420 | @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from | |
421 | relaxation, because they have no complementing counterparts. They could | |
422 | be relaxed with the use of a longer sequence involving another branch, | |
423 | however this has not been implemented and if their target turns out of | |
424 | reach, they produce an error even if branch relaxation is enabled. | |
425 | ||
81566a9b | 426 | Also no MIPS16 branches are ever relaxed. |
3bf0dbfb MR |
427 | |
428 | By default @samp{--no-relax-branch} is selected, causing any out-of-range | |
429 | branches to produce an error. | |
430 | ||
ba92f887 MR |
431 | @cindex @option{-mnan=} command line option, MIPS |
432 | @item -mnan=@var{encoding} | |
433 | This option indicates whether the source code uses the IEEE 2008 | |
434 | NaN encoding (@option{-mnan=2008}) or the original MIPS encoding | |
435 | (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} | |
436 | directive to the beginning of the source file. @xref{MIPS NaN Encodings}. | |
437 | ||
438 | @option{-mnan=legacy} is the default if no @option{-mnan} option or | |
439 | @code{.nan} directive is used. | |
440 | ||
252b5132 RH |
441 | @item --trap |
442 | @itemx --no-break | |
443 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
444 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
445 | @code{@value{AS}} automatically macro expands certain division and | |
446 | multiplication instructions to check for overflow and division by zero. This | |
447 | option causes @code{@value{AS}} to generate code to take a trap exception | |
448 | rather than a break exception when an error is detected. The trap instructions | |
449 | are only supported at Instruction Set Architecture level 2 and higher. | |
450 | ||
451 | @item --break | |
452 | @itemx --no-trap | |
453 | Generate code to take a break exception rather than a trap exception when an | |
454 | error is detected. This is the default. | |
63486801 | 455 | |
dcd410fe RO |
456 | @item -mpdr |
457 | @itemx -mno-pdr | |
458 | Control generation of @code{.pdr} sections. Off by default on IRIX, on | |
459 | elsewhere. | |
aa6975fb ILT |
460 | |
461 | @item -mshared | |
462 | @itemx -mno-shared | |
463 | When generating code using the Unix calling conventions (selected by | |
464 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code | |
465 | which can go into a shared library. The @samp{-mno-shared} option | |
466 | tells gas to generate code which uses the calling convention, but can | |
467 | not go into a shared library. The resulting code is slightly more | |
468 | efficient. This option only affects the handling of the | |
469 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. | |
252b5132 RH |
470 | @end table |
471 | ||
fc16f8cc RS |
472 | @node MIPS Macros |
473 | @section High-level assembly macros | |
474 | ||
475 | MIPS assemblers have traditionally provided a wider range of | |
476 | instructions than the MIPS architecture itself. These extra | |
477 | instructions are usually referred to as ``macro'' instructions | |
478 | @footnote{The term ``macro'' is somewhat overloaded here, since | |
479 | these macros have no relation to those defined by @code{.macro}, | |
480 | @pxref{Macro,, @code{.macro}}.}. | |
481 | ||
482 | Some MIPS macro instructions extend an underlying architectural instruction | |
483 | while others are entirely new. An example of the former type is @code{and}, | |
484 | which allows the third operand to be either a register or an arbitrary | |
485 | immediate value. Examples of the latter type include @code{bgt}, which | |
486 | branches to the third operand when the first operand is greater than | |
487 | the second operand, and @code{ulh}, which implements an unaligned | |
488 | 2-byte load. | |
489 | ||
490 | One of the most common extensions provided by macros is to expand | |
491 | memory offsets to the full address range (32 or 64 bits) and to allow | |
492 | symbolic offsets such as @samp{my_data + 4} to be used in place of | |
493 | integer constants. For example, the architectural instruction | |
494 | @code{lbu} allows only a signed 16-bit offset, whereas the macro | |
495 | @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. | |
496 | The implementation of these symbolic offsets depends on several factors, | |
98508b2a RS |
497 | such as whether the assembler is generating SVR4-style PIC (selected by |
498 | @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols | |
fc16f8cc RS |
499 | (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), |
500 | and the small data limit (@pxref{MIPS Small Data,, Controlling the use | |
501 | of small data accesses}). | |
502 | ||
503 | @kindex @code{.set macro} | |
504 | @kindex @code{.set nomacro} | |
505 | Sometimes it is undesirable to have one assembly instruction expand | |
506 | to several machine instructions. The directive @code{.set nomacro} | |
507 | tells the assembler to warn when this happens. @code{.set macro} | |
508 | restores the default behavior. | |
509 | ||
510 | @cindex @code{at} register, MIPS | |
511 | @kindex @code{.set at=@var{reg}} | |
512 | Some macro instructions need a temporary register to store intermediate | |
513 | results. This register is usually @code{$1}, also known as @code{$at}, | |
514 | but it can be changed to any core register @var{reg} using | |
515 | @code{.set at=@var{reg}}. Note that @code{$at} always refers | |
516 | to @code{$1} regardless of which register is being used as the | |
517 | temporary register. | |
518 | ||
519 | @kindex @code{.set at} | |
520 | @kindex @code{.set noat} | |
521 | Implicit uses of the temporary register in macros could interfere with | |
522 | explicit uses in the assembly code. The assembler therefore warns | |
523 | whenever it sees an explicit use of the temporary register. The directive | |
524 | @code{.set noat} silences this warning while @code{.set at} restores | |
525 | the default behavior. It is safe to use @code{.set noat} while | |
526 | @code{.set nomacro} is in effect since single-instruction macros | |
527 | never need a temporary register. | |
528 | ||
529 | Note that while the @sc{gnu} assembler provides these macros for compatibility, | |
530 | it does not make any attempt to optimize them with the surrounding code. | |
531 | ||
5a7560b5 | 532 | @node MIPS Symbol Sizes |
aed1a261 RS |
533 | @section Directives to override the size of symbols |
534 | ||
5a7560b5 RS |
535 | @kindex @code{.set sym32} |
536 | @kindex @code{.set nosym32} | |
aed1a261 RS |
537 | The n64 ABI allows symbols to have any 64-bit value. Although this |
538 | provides a great deal of flexibility, it means that some macros have | |
539 | much longer expansions than their 32-bit counterparts. For example, | |
540 | the non-PIC expansion of @samp{dla $4,sym} is usually: | |
541 | ||
542 | @smallexample | |
543 | lui $4,%highest(sym) | |
544 | lui $1,%hi(sym) | |
545 | daddiu $4,$4,%higher(sym) | |
546 | daddiu $1,$1,%lo(sym) | |
547 | dsll32 $4,$4,0 | |
548 | daddu $4,$4,$1 | |
549 | @end smallexample | |
550 | ||
551 | whereas the 32-bit expansion is simply: | |
552 | ||
553 | @smallexample | |
554 | lui $4,%hi(sym) | |
555 | daddiu $4,$4,%lo(sym) | |
556 | @end smallexample | |
557 | ||
558 | n64 code is sometimes constructed in such a way that all symbolic | |
559 | constants are known to have 32-bit values, and in such cases, it's | |
560 | preferable to use the 32-bit expansion instead of the 64-bit | |
561 | expansion. | |
562 | ||
563 | You can use the @code{.set sym32} directive to tell the assembler | |
564 | that, from this point on, all expressions of the form | |
565 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} | |
566 | have 32-bit values. For example: | |
567 | ||
568 | @smallexample | |
569 | .set sym32 | |
570 | dla $4,sym | |
571 | lw $4,sym+16 | |
572 | sw $4,sym+0x8000($4) | |
573 | @end smallexample | |
574 | ||
575 | will cause the assembler to treat @samp{sym}, @code{sym+16} and | |
576 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic | |
577 | addresses is not affected. | |
578 | ||
579 | The directive @code{.set nosym32} ends a @code{.set sym32} block and | |
580 | reverts to the normal behavior. It is also possible to change the | |
581 | symbol size using the command-line options @option{-msym32} and | |
582 | @option{-mno-sym32}. | |
583 | ||
584 | These options and directives are always accepted, but at present, | |
585 | they have no effect for anything other than n64. | |
586 | ||
fc16f8cc RS |
587 | @node MIPS Small Data |
588 | @section Controlling the use of small data accesses | |
5a7560b5 | 589 | |
fc16f8cc RS |
590 | @c This section deliberately glosses over the possibility of using -G |
591 | @c in SVR4-style PIC, as could be done on IRIX. We don't support that. | |
592 | @cindex small data, MIPS | |
5a7560b5 | 593 | @cindex @code{gp} register, MIPS |
fc16f8cc RS |
594 | It often takes several instructions to load the address of a symbol. |
595 | For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion | |
596 | of @samp{dla $4,addr} is usually: | |
597 | ||
598 | @smallexample | |
599 | lui $4,%hi(addr) | |
600 | daddiu $4,$4,%lo(addr) | |
601 | @end smallexample | |
602 | ||
603 | The sequence is much longer when @samp{addr} is a 64-bit symbol. | |
604 | @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. | |
605 | ||
606 | In order to cut down on this overhead, most embedded MIPS systems | |
607 | set aside a 64-kilobyte ``small data'' area and guarantee that all | |
608 | data of size @var{n} and smaller will be placed in that area. | |
609 | The limit @var{n} is passed to both the assembler and the linker | |
98508b2a | 610 | using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, |
fc16f8cc RS |
611 | Assembler options}. Note that the same value of @var{n} must be used |
612 | when linking and when assembling all input files to the link; any | |
613 | inconsistency could cause a relocation overflow error. | |
614 | ||
615 | The size of an object in the @code{.bss} section is set by the | |
616 | @code{.comm} or @code{.lcomm} directive that defines it. The size of | |
617 | an external object may be set with the @code{.extern} directive. For | |
618 | example, @samp{.extern sym,4} declares that the object at @code{sym} | |
619 | is 4 bytes in length, while leaving @code{sym} otherwise undefined. | |
620 | ||
621 | When no @option{-G} option is given, the default limit is 8 bytes. | |
622 | The option @option{-G 0} prevents any data from being automatically | |
623 | classified as small. | |
624 | ||
625 | It is also possible to mark specific objects as small by putting them | |
626 | in the special sections @code{.sdata} and @code{.sbss}, which are | |
627 | ``small'' counterparts of @code{.data} and @code{.bss} respectively. | |
628 | The toolchain will treat such data as small regardless of the | |
629 | @option{-G} setting. | |
630 | ||
631 | On startup, systems that support a small data area are expected to | |
632 | initialize register @code{$28}, also known as @code{$gp}, in such a | |
633 | way that small data can be accessed using a 16-bit offset from that | |
634 | register. For example, when @samp{addr} is small data, | |
635 | the @samp{dla $4,addr} instruction above is equivalent to: | |
636 | ||
637 | @smallexample | |
638 | daddiu $4,$28,%gp_rel(addr) | |
639 | @end smallexample | |
640 | ||
641 | Small data is not supported for SVR4-style PIC. | |
5a7560b5 | 642 | |
252b5132 RH |
643 | @node MIPS ISA |
644 | @section Directives to override the ISA level | |
645 | ||
646 | @cindex MIPS ISA override | |
647 | @kindex @code{.set mips@var{n}} | |
648 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
98508b2a | 649 | the MIPS Instruction Set Architecture level on the fly: @code{.set |
5f74bc13 CD |
650 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 |
651 | or 64r2. | |
071742cf | 652 | The values other than 0 make the assembler accept instructions |
e335d9cb | 653 | for the corresponding ISA level, from that point on in the |
584da044 NC |
654 | assembly. @code{.set mips@var{n}} affects not only which instructions |
655 | are permitted, but also how certain macros are expanded. @code{.set | |
e335d9cb | 656 | mips0} restores the ISA level to its original level: either the |
584da044 | 657 | level you selected with command line options, or the default for your |
81566a9b | 658 | configuration. You can use this feature to permit specific MIPS III |
584da044 | 659 | instructions while assembling in 32 bit mode. Use this directive with |
ec68c924 | 660 | care! |
252b5132 | 661 | |
ad3fea08 TS |
662 | @cindex MIPS CPU override |
663 | @kindex @code{.set arch=@var{cpu}} | |
664 | The @code{.set arch=@var{cpu}} directive provides even finer control. | |
665 | It changes the effective CPU target and allows the assembler to use | |
666 | instructions specific to a particular CPU. All CPUs supported by the | |
667 | @samp{-march} command line option are also selectable by this directive. | |
668 | The original value is restored by @code{.set arch=default}. | |
252b5132 | 669 | |
ad3fea08 TS |
670 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
671 | in which it will assemble instructions for the MIPS 16 processor. Use | |
672 | @code{.set nomips16} to return to normal 32 bit mode. | |
e16bfa71 | 673 | |
98508b2a | 674 | Traditional MIPS assemblers do not support this directive. |
252b5132 | 675 | |
df58fc94 RS |
676 | The directive @code{.set micromips} puts the assembler into microMIPS mode, |
677 | in which it will assemble instructions for the microMIPS processor. Use | |
678 | @code{.set nomicromips} to return to normal 32 bit mode. | |
679 | ||
98508b2a | 680 | Traditional MIPS assemblers do not support this directive. |
df58fc94 | 681 | |
833794fc MR |
682 | @node MIPS assembly options |
683 | @section Directives to control code generation | |
684 | ||
685 | @cindex MIPS 32-bit microMIPS instruction generation override | |
686 | @kindex @code{.set insn32} | |
687 | @kindex @code{.set noinsn32} | |
688 | The directive @code{.set insn32} makes the assembler only use 32-bit | |
689 | instruction encodings when generating code for the microMIPS processor. | |
690 | This directive inhibits the use of any 16-bit instructions from that | |
691 | point on in the assembly. The @code{.set noinsn32} directive allows | |
692 | 16-bit instructions to be accepted. | |
693 | ||
694 | Traditional MIPS assemblers do not support this directive. | |
695 | ||
252b5132 RH |
696 | @node MIPS autoextend |
697 | @section Directives for extending MIPS 16 bit instructions | |
698 | ||
699 | @kindex @code{.set autoextend} | |
700 | @kindex @code{.set noautoextend} | |
701 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
ad3fea08 TS |
702 | when necessary. The directive @code{.set noautoextend} will turn this |
703 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction | |
704 | must be explicitly extended with the @code{.e} modifier (e.g., | |
705 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used | |
252b5132 RH |
706 | to once again automatically extend instructions when necessary. |
707 | ||
708 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
98508b2a | 709 | MIPS assemblers do not support this directive. |
252b5132 RH |
710 | |
711 | @node MIPS insn | |
712 | @section Directive to mark data as an instruction | |
713 | ||
714 | @kindex @code{.insn} | |
715 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
df58fc94 RS |
716 | data is actually instructions. This makes a difference in MIPS 16 and |
717 | microMIPS modes: when loading the address of a label which precedes | |
718 | instructions, @code{@value{AS}} automatically adds 1 to the value, so | |
719 | that jumping to the loaded address will do the right thing. | |
252b5132 | 720 | |
a946d7e3 NC |
721 | @kindex @code{.global} |
722 | The @code{.global} and @code{.globl} directives supported by | |
723 | @code{@value{AS}} will by default mark the symbol as pointing to a | |
724 | region of data not code. This means that, for example, any | |
725 | instructions following such a symbol will not be disassembled by | |
f746e6b9 | 726 | @code{objdump} as it will regard them as data. To change this |
a946d7e3 NC |
727 | behaviour an optional section name can be placed after the symbol name |
728 | in the @code{.global} directive. If this section exists and is known | |
729 | to be a code section, then the symbol will be marked as poiting at | |
730 | code not data. Ie the syntax for the directive is: | |
731 | ||
732 | @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, | |
733 | ||
734 | Here is a short example: | |
735 | ||
736 | @example | |
737 | .global foo .text, bar, baz .data | |
738 | foo: | |
739 | nop | |
740 | bar: | |
741 | .word 0x0 | |
742 | baz: | |
743 | .word 0x1 | |
34bca508 | 744 | |
a946d7e3 NC |
745 | @end example |
746 | ||
ba92f887 MR |
747 | @node MIPS NaN Encodings |
748 | @section Directives to record which NaN encoding is being used | |
749 | ||
750 | @cindex MIPS IEEE 754 NaN data encoding selection | |
751 | @cindex @code{.nan} directive, MIPS | |
752 | The IEEE 754 floating-point standard defines two types of not-a-number | |
753 | (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version | |
754 | of the standard did not specify how these two types should be | |
755 | distinguished. Most implementations followed the i387 model, in which | |
756 | the first bit of the significand is set for quiet NaNs and clear for | |
757 | signalling NaNs. However, the original MIPS implementation assigned the | |
758 | opposite meaning to the bit, so that it was set for signalling NaNs and | |
759 | clear for quiet NaNs. | |
760 | ||
761 | The 2008 revision of the standard formally suggested the i387 choice | |
762 | and as from Sep 2012 the current release of the MIPS architecture | |
763 | therefore optionally supports that form. Code that uses one NaN encoding | |
764 | would usually be incompatible with code that uses the other NaN encoding, | |
765 | so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which | |
766 | encoding is being used. | |
767 | ||
768 | Assembly files can use the @code{.nan} directive to select between the | |
769 | two encodings. @samp{.nan 2008} says that the assembly file uses the | |
770 | IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses | |
771 | the original MIPS encoding. If several @code{.nan} directives are given, | |
772 | the final setting is the one that is used. | |
773 | ||
774 | The command-line options @option{-mnan=legacy} and @option{-mnan=2008} | |
775 | can be used instead of @samp{.nan legacy} and @samp{.nan 2008} | |
776 | respectively. However, any @code{.nan} directive overrides the | |
777 | command-line setting. | |
778 | ||
779 | @samp{.nan legacy} is the default if no @code{.nan} directive or | |
780 | @option{-mnan} option is given. | |
781 | ||
782 | Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and | |
783 | therefore these directives do not affect code generation. They simply | |
784 | control the setting of the @code{EF_MIPS_NAN2008} flag. | |
785 | ||
786 | Traditional MIPS assemblers do not support these directives. | |
787 | ||
98508b2a | 788 | @node MIPS Option Stack |
252b5132 RH |
789 | @section Directives to save and restore options |
790 | ||
791 | @cindex MIPS option stack | |
792 | @kindex @code{.set push} | |
793 | @kindex @code{.set pop} | |
794 | The directives @code{.set push} and @code{.set pop} may be used to save | |
795 | and restore the current settings for all the options which are | |
796 | controlled by @code{.set}. The @code{.set push} directive saves the | |
797 | current settings on a stack. The @code{.set pop} directive pops the | |
798 | stack and restores the settings. | |
799 | ||
800 | These directives can be useful inside an macro which must change an | |
801 | option such as the ISA level or instruction reordering but does not want | |
802 | to change the state of the code which invoked the macro. | |
803 | ||
98508b2a | 804 | Traditional MIPS assemblers do not support these directives. |
1f25f5d3 | 805 | |
98508b2a | 806 | @node MIPS ASE Instruction Generation Overrides |
1f25f5d3 CD |
807 | @section Directives to control generation of MIPS ASE instructions |
808 | ||
809 | @cindex MIPS MIPS-3D instruction generation override | |
810 | @kindex @code{.set mips3d} | |
811 | @kindex @code{.set nomips3d} | |
812 | The directive @code{.set mips3d} makes the assembler accept instructions | |
813 | from the MIPS-3D Application Specific Extension from that point on | |
814 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
815 | instructions from being accepted. | |
816 | ||
ad3fea08 TS |
817 | @cindex SmartMIPS instruction generation override |
818 | @kindex @code{.set smartmips} | |
819 | @kindex @code{.set nosmartmips} | |
820 | The directive @code{.set smartmips} makes the assembler accept | |
821 | instructions from the SmartMIPS Application Specific Extension to the | |
e335d9cb | 822 | MIPS32 ISA from that point on in the assembly. The |
ad3fea08 TS |
823 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from |
824 | being accepted. | |
825 | ||
deec1734 CD |
826 | @cindex MIPS MDMX instruction generation override |
827 | @kindex @code{.set mdmx} | |
828 | @kindex @code{.set nomdmx} | |
829 | The directive @code{.set mdmx} makes the assembler accept instructions | |
830 | from the MDMX Application Specific Extension from that point on | |
831 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
832 | instructions from being accepted. | |
833 | ||
8b082fb1 | 834 | @cindex MIPS DSP Release 1 instruction generation override |
2ef2b9ae CF |
835 | @kindex @code{.set dsp} |
836 | @kindex @code{.set nodsp} | |
837 | The directive @code{.set dsp} makes the assembler accept instructions | |
8b082fb1 TS |
838 | from the DSP Release 1 Application Specific Extension from that point |
839 | on in the assembly. The @code{.set nodsp} directive prevents DSP | |
840 | Release 1 instructions from being accepted. | |
841 | ||
842 | @cindex MIPS DSP Release 2 instruction generation override | |
843 | @kindex @code{.set dspr2} | |
844 | @kindex @code{.set nodspr2} | |
845 | The directive @code{.set dspr2} makes the assembler accept instructions | |
846 | from the DSP Release 2 Application Specific Extension from that point | |
847 | on in the assembly. This dirctive implies @code{.set dsp}. The | |
848 | @code{.set nodspr2} directive prevents DSP Release 2 instructions from | |
849 | being accepted. | |
2ef2b9ae | 850 | |
ef2e4d86 CF |
851 | @cindex MIPS MT instruction generation override |
852 | @kindex @code{.set mt} | |
853 | @kindex @code{.set nomt} | |
854 | The directive @code{.set mt} makes the assembler accept instructions | |
855 | from the MT Application Specific Extension from that point on | |
856 | in the assembly. The @code{.set nomt} directive prevents MT | |
857 | instructions from being accepted. | |
858 | ||
dec0624d MR |
859 | @cindex MIPS MCU instruction generation override |
860 | @kindex @code{.set mcu} | |
861 | @kindex @code{.set nomcu} | |
862 | The directive @code{.set mcu} makes the assembler accept instructions | |
863 | from the MCU Application Specific Extension from that point on | |
864 | in the assembly. The @code{.set nomcu} directive prevents MCU | |
865 | instructions from being accepted. | |
866 | ||
56d438b1 CF |
867 | @cindex MIPS SIMD Architecture instruction generation override |
868 | @kindex @code{.set msa} | |
869 | @kindex @code{.set nomsa} | |
870 | The directive @code{.set msa} makes the assembler accept instructions | |
871 | from the MIPS SIMD Architecture Extension from that point on | |
872 | in the assembly. The @code{.set nomsa} directive prevents MSA | |
873 | instructions from being accepted. | |
874 | ||
b015e599 AP |
875 | @cindex Virtualization instruction generation override |
876 | @kindex @code{.set virt} | |
877 | @kindex @code{.set novirt} | |
878 | The directive @code{.set virt} makes the assembler accept instructions | |
879 | from the Virtualization Application Specific Extension from that point | |
880 | on in the assembly. The @code{.set novirt} directive prevents Virtualization | |
881 | instructions from being accepted. | |
882 | ||
98508b2a | 883 | Traditional MIPS assemblers do not support these directives. |
037b32b9 | 884 | |
98508b2a | 885 | @node MIPS Floating-Point |
037b32b9 AN |
886 | @section Directives to override floating-point options |
887 | ||
888 | @cindex Disable floating-point instructions | |
889 | @kindex @code{.set softfloat} | |
890 | @kindex @code{.set hardfloat} | |
891 | The directives @code{.set softfloat} and @code{.set hardfloat} provide | |
892 | finer control of disabling and enabling float-point instructions. | |
893 | These directives always override the default (that hard-float | |
894 | instructions are accepted) or the command-line options | |
895 | (@samp{-msoft-float} and @samp{-mhard-float}). | |
896 | ||
897 | @cindex Disable single-precision floating-point operations | |
605b1dd4 NH |
898 | @kindex @code{.set singlefloat} |
899 | @kindex @code{.set doublefloat} | |
037b32b9 AN |
900 | The directives @code{.set singlefloat} and @code{.set doublefloat} |
901 | provide finer control of disabling and enabling double-precision | |
902 | float-point operations. These directives always override the default | |
903 | (that double-precision operations are accepted) or the command-line | |
904 | options (@samp{-msingle-float} and @samp{-mdouble-float}). | |
905 | ||
98508b2a | 906 | Traditional MIPS assemblers do not support these directives. |
7c31ae13 NC |
907 | |
908 | @node MIPS Syntax | |
909 | @section Syntactical considerations for the MIPS assembler | |
910 | @menu | |
911 | * MIPS-Chars:: Special Characters | |
912 | @end menu | |
913 | ||
914 | @node MIPS-Chars | |
915 | @subsection Special Characters | |
916 | ||
917 | @cindex line comment character, MIPS | |
918 | @cindex MIPS line comment character | |
919 | The presence of a @samp{#} on a line indicates the start of a comment | |
920 | that extends to the end of the current line. | |
921 | ||
922 | If a @samp{#} appears as the first character of a line, the whole line | |
923 | is treated as a comment, but in this case the line can also be a | |
924 | logical line number directive (@pxref{Comments}) or a | |
925 | preprocessor control command (@pxref{Preprocessing}). | |
926 | ||
927 | @cindex line separator, MIPS | |
928 | @cindex statement separator, MIPS | |
929 | @cindex MIPS line separator | |
930 | The @samp{;} character can be used to separate statements on the same | |
931 | line. |