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219d1afa | 1 | @c Copyright (C) 1991-2018 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node MIPS-Dependent | |
7 | @chapter MIPS Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter MIPS Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex MIPS processor | |
98508b2a RS |
15 | @sc{gnu} @code{@value{AS}} for MIPS architectures supports several |
16 | different MIPS processors, and MIPS ISA levels I through V, MIPS32, | |
17 | and MIPS64. For information about the MIPS instruction set, see | |
584da044 | 18 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
98508b2a | 19 | For an overview of MIPS assembly conventions, see ``Appendix D: |
584da044 | 20 | Assembly Language Programming'' in the same work. |
252b5132 RH |
21 | |
22 | @menu | |
98508b2a | 23 | * MIPS Options:: Assembler options |
fc16f8cc | 24 | * MIPS Macros:: High-level assembly macros |
5a7560b5 | 25 | * MIPS Symbol Sizes:: Directives to override the size of symbols |
fc16f8cc | 26 | * MIPS Small Data:: Controlling the use of small data accesses |
252b5132 | 27 | * MIPS ISA:: Directives to override the ISA level |
833794fc | 28 | * MIPS assembly options:: Directives to control code generation |
252b5132 RH |
29 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
30 | * MIPS insn:: Directive to mark data as an instruction | |
351cdf24 | 31 | * MIPS FP ABIs:: Marking which FP ABI is in use |
ba92f887 | 32 | * MIPS NaN Encodings:: Directives to record which NaN encoding is being used |
98508b2a RS |
33 | * MIPS Option Stack:: Directives to save and restore options |
34 | * MIPS ASE Instruction Generation Overrides:: Directives to control | |
0eb7102d | 35 | generation of MIPS ASE instructions |
98508b2a | 36 | * MIPS Floating-Point:: Directives to override floating-point options |
7c31ae13 | 37 | * MIPS Syntax:: MIPS specific syntactical considerations |
252b5132 RH |
38 | @end menu |
39 | ||
98508b2a | 40 | @node MIPS Options |
252b5132 RH |
41 | @section Assembler options |
42 | ||
98508b2a | 43 | The MIPS configurations of @sc{gnu} @code{@value{AS}} support these |
252b5132 RH |
44 | special options: |
45 | ||
46 | @table @code | |
47 | @cindex @code{-G} option (MIPS) | |
48 | @item -G @var{num} | |
fc16f8cc RS |
49 | Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. |
50 | @xref{MIPS Small Data,, Controlling the use of small data accesses}. | |
252b5132 RH |
51 | |
52 | @cindex @code{-EB} option (MIPS) | |
53 | @cindex @code{-EL} option (MIPS) | |
54 | @cindex MIPS big-endian output | |
55 | @cindex MIPS little-endian output | |
56 | @cindex big-endian output, MIPS | |
57 | @cindex little-endian output, MIPS | |
58 | @item -EB | |
59 | @itemx -EL | |
98508b2a | 60 | Any MIPS configuration of @code{@value{AS}} can select big-endian or |
252b5132 RH |
61 | little-endian output at run time (unlike the other @sc{gnu} development |
62 | tools, which must be configured for one or the other). Use @samp{-EB} | |
63 | to select big-endian output, and @samp{-EL} for little-endian. | |
64 | ||
0c000745 RS |
65 | @item -KPIC |
66 | @cindex PIC selection, MIPS | |
67 | @cindex @option{-KPIC} option, MIPS | |
68 | Generate SVR4-style PIC. This option tells the assembler to generate | |
69 | SVR4-style position-independent macro expansions. It also tells the | |
70 | assembler to mark the output file as PIC. | |
71 | ||
72 | @item -mvxworks-pic | |
73 | @cindex @option{-mvxworks-pic} option, MIPS | |
74 | Generate VxWorks PIC. This option tells the assembler to generate | |
75 | VxWorks-style position-independent macro expansions. | |
76 | ||
252b5132 RH |
77 | @cindex MIPS architecture options |
78 | @item -mips1 | |
79 | @itemx -mips2 | |
80 | @itemx -mips3 | |
81 | @itemx -mips4 | |
b1929900 | 82 | @itemx -mips5 |
e7af610e | 83 | @itemx -mips32 |
af7ee8bf | 84 | @itemx -mips32r2 |
ae52f483 AB |
85 | @itemx -mips32r3 |
86 | @itemx -mips32r5 | |
7361da2c | 87 | @itemx -mips32r6 |
84ea6cf2 | 88 | @itemx -mips64 |
5f74bc13 | 89 | @itemx -mips64r2 |
ae52f483 AB |
90 | @itemx -mips64r3 |
91 | @itemx -mips64r5 | |
7361da2c | 92 | @itemx -mips64r6 |
252b5132 | 93 | Generate code for a particular MIPS Instruction Set Architecture level. |
98508b2a RS |
94 | @samp{-mips1} corresponds to the R2000 and R3000 processors, |
95 | @samp{-mips2} to the R6000 processor, @samp{-mips3} to the | |
81566a9b | 96 | R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. |
7361da2c AB |
97 | @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, |
98 | @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, | |
99 | @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to | |
100 | generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 | |
101 | Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 | |
102 | Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, | |
103 | respectively. You can also switch instruction sets during the assembly; | |
104 | see @ref{MIPS ISA, Directives to override the ISA level}. | |
252b5132 | 105 | |
6349b5f4 | 106 | @item -mgp32 |
ca4e0257 RS |
107 | @itemx -mfp32 |
108 | Some macros have different expansions for 32-bit and 64-bit registers. | |
109 | The register sizes are normally inferred from the ISA and ABI, but these | |
110 | flags force a certain group of registers to be treated as 32 bits wide at | |
111 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
112 | and @samp{-mfp32} controls the size of floating-point registers. | |
113 | ||
ad3fea08 TS |
114 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
115 | of registers to be changed for parts of an object. The default value is | |
116 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
117 | ||
ca4e0257 RS |
118 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
119 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
120 | save the 32-bit registers on a context switch, so it is essential never | |
121 | to use the 64-bit registers. | |
6349b5f4 AH |
122 | |
123 | @item -mgp64 | |
ad3fea08 TS |
124 | @itemx -mfp64 |
125 | Assume that 64-bit registers are available. This is provided in the | |
126 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. | |
127 | ||
128 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size | |
129 | of registers to be changed for parts of an object. The default value is | |
130 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
6349b5f4 | 131 | |
351cdf24 MF |
132 | @item -mfpxx |
133 | Make no assumptions about whether 32-bit or 64-bit floating-point | |
134 | registers are available. This is provided to support having modules | |
135 | compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can | |
136 | only be used with MIPS II and above. | |
137 | ||
138 | The @code{.set fp=xx} directive allows a part of an object to be marked | |
139 | as not making assumptions about 32-bit or 64-bit FP registers. The | |
140 | default value is restored by @code{.set fp=default}. | |
141 | ||
142 | @item -modd-spreg | |
143 | @itemx -mno-odd-spreg | |
144 | Enable use of floating-point operations on odd-numbered single-precision | |
145 | registers when supported by the ISA. @samp{-mfpxx} implies | |
146 | @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} | |
147 | ||
252b5132 RH |
148 | @item -mips16 |
149 | @itemx -no-mips16 | |
150 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
32035f51 | 151 | @code{.module mips16} at the start of the assembly file. @samp{-no-mips16} |
252b5132 RH |
152 | turns off this option. |
153 | ||
25499ac7 MR |
154 | @item -mmips16e2 |
155 | @itemx -mno-mips16e2 | |
156 | Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent | |
157 | to putting @code{.module mips16e2} at the start of the assembly file. | |
158 | @samp{-mno-mips16e2} turns off this option. | |
159 | ||
df58fc94 RS |
160 | @item -mmicromips |
161 | @itemx -mno-micromips | |
162 | Generate code for the microMIPS processor. This is equivalent to putting | |
32035f51 MR |
163 | @code{.module micromips} at the start of the assembly file. |
164 | @samp{-mno-micromips} turns off this option. This is equivalent to putting | |
165 | @code{.module nomicromips} at the start of the assembly file. | |
df58fc94 | 166 | |
e16bfa71 TS |
167 | @item -msmartmips |
168 | @itemx -mno-smartmips | |
169 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which | |
170 | provides a number of new instructions which target smartcard and | |
171 | cryptographic applications. This is equivalent to putting | |
32035f51 | 172 | @code{.module smartmips} at the start of the assembly file. |
e16bfa71 TS |
173 | @samp{-mno-smartmips} turns off this option. |
174 | ||
1f25f5d3 CD |
175 | @item -mips3d |
176 | @itemx -no-mips3d | |
177 | Generate code for the MIPS-3D Application Specific Extension. | |
178 | This tells the assembler to accept MIPS-3D instructions. | |
179 | @samp{-no-mips3d} turns off this option. | |
180 | ||
deec1734 CD |
181 | @item -mdmx |
182 | @itemx -no-mdmx | |
183 | Generate code for the MDMX Application Specific Extension. | |
184 | This tells the assembler to accept MDMX instructions. | |
185 | @samp{-no-mdmx} turns off this option. | |
186 | ||
2ef2b9ae CF |
187 | @item -mdsp |
188 | @itemx -mno-dsp | |
8b082fb1 TS |
189 | Generate code for the DSP Release 1 Application Specific Extension. |
190 | This tells the assembler to accept DSP Release 1 instructions. | |
2ef2b9ae CF |
191 | @samp{-mno-dsp} turns off this option. |
192 | ||
8b082fb1 TS |
193 | @item -mdspr2 |
194 | @itemx -mno-dspr2 | |
195 | Generate code for the DSP Release 2 Application Specific Extension. | |
8f4f9071 | 196 | This option implies @samp{-mdsp}. |
8b082fb1 TS |
197 | This tells the assembler to accept DSP Release 2 instructions. |
198 | @samp{-mno-dspr2} turns off this option. | |
199 | ||
8f4f9071 MF |
200 | @item -mdspr3 |
201 | @itemx -mno-dspr3 | |
202 | Generate code for the DSP Release 3 Application Specific Extension. | |
203 | This option implies @samp{-mdsp} and @samp{-mdspr2}. | |
204 | This tells the assembler to accept DSP Release 3 instructions. | |
205 | @samp{-mno-dspr3} turns off this option. | |
206 | ||
ef2e4d86 CF |
207 | @item -mmt |
208 | @itemx -mno-mt | |
209 | Generate code for the MT Application Specific Extension. | |
210 | This tells the assembler to accept MT instructions. | |
211 | @samp{-mno-mt} turns off this option. | |
212 | ||
dec0624d MR |
213 | @item -mmcu |
214 | @itemx -mno-mcu | |
215 | Generate code for the MCU Application Specific Extension. | |
216 | This tells the assembler to accept MCU instructions. | |
217 | @samp{-mno-mcu} turns off this option. | |
218 | ||
56d438b1 CF |
219 | @item -mmsa |
220 | @itemx -mno-msa | |
221 | Generate code for the MIPS SIMD Architecture Extension. | |
222 | This tells the assembler to accept MSA instructions. | |
223 | @samp{-mno-msa} turns off this option. | |
224 | ||
7d64c587 AB |
225 | @item -mxpa |
226 | @itemx -mno-xpa | |
227 | Generate code for the MIPS eXtended Physical Address (XPA) Extension. | |
228 | This tells the assembler to accept XPA instructions. | |
229 | @samp{-mno-xpa} turns off this option. | |
230 | ||
b015e599 AP |
231 | @item -mvirt |
232 | @itemx -mno-virt | |
233 | Generate code for the Virtualization Application Specific Extension. | |
234 | This tells the assembler to accept Virtualization instructions. | |
235 | @samp{-mno-virt} turns off this option. | |
236 | ||
730c3174 SE |
237 | @item -mcrc |
238 | @itemx -mno-crc | |
239 | Generate code for the cyclic redundancy check (CRC) Application Specific | |
240 | Extension. This tells the assembler to accept CRC instructions. | |
241 | @samp{-mno-crc} turns off this option. | |
242 | ||
6f20c942 FS |
243 | @item -mginv |
244 | @itemx -mno-ginv | |
245 | Generate code for the Global INValidate (GINV) Application Specific | |
246 | Extension. This tells the assembler to accept GINV instructions. | |
247 | @samp{-mno-ginv} turns off this option. | |
248 | ||
833794fc MR |
249 | @item -minsn32 |
250 | @itemx -mno-insn32 | |
251 | Only use 32-bit instruction encodings when generating code for the | |
252 | microMIPS processor. This option inhibits the use of any 16-bit | |
253 | instructions. This is equivalent to putting @code{.set insn32} at | |
254 | the start of the assembly file. @samp{-mno-insn32} turns off this | |
255 | option. This is equivalent to putting @code{.set noinsn32} at the | |
256 | start of the assembly file. By default @samp{-mno-insn32} is | |
257 | selected, allowing all instructions to be used. | |
258 | ||
6b76fefe | 259 | @item -mfix7000 |
9ee72ff1 | 260 | @itemx -mno-fix7000 |
6b76fefe CM |
261 | Cause nops to be inserted if the read of the destination register |
262 | of an mfhi or mflo instruction occurs in the following two instructions. | |
263 | ||
a8d14a88 CM |
264 | @item -mfix-rm7000 |
265 | @itemx -mno-fix-rm7000 | |
266 | Cause nops to be inserted if a dmult or dmultu instruction is | |
267 | followed by a load instruction. | |
268 | ||
c67a084a NC |
269 | @item -mfix-loongson2f-jump |
270 | @itemx -mno-fix-loongson2f-jump | |
271 | Eliminate instruction fetch from outside 256M region to work around the | |
272 | Loongson2F @samp{jump} instructions. Without it, under extreme cases, | |
273 | the kernel may crash. The issue has been solved in latest processor | |
274 | batches, but this fix has no side effect to them. | |
275 | ||
276 | @item -mfix-loongson2f-nop | |
277 | @itemx -mno-fix-loongson2f-nop | |
278 | Replace nops by @code{or at,at,zero} to work around the Loongson2F | |
98508b2a RS |
279 | @samp{nop} errata. Without it, under extreme cases, the CPU might |
280 | deadlock. The issue has been solved in later Loongson2F batches, but | |
c67a084a NC |
281 | this fix has no side effect to them. |
282 | ||
d766e8ec | 283 | @item -mfix-vr4120 |
2babba43 | 284 | @itemx -mno-fix-vr4120 |
d766e8ec RS |
285 | Insert nops to work around certain VR4120 errata. This option is |
286 | intended to be used on GCC-generated code: it is not designed to catch | |
287 | all problems in hand-written assembler code. | |
60b63b72 | 288 | |
11db99f8 | 289 | @item -mfix-vr4130 |
2babba43 | 290 | @itemx -mno-fix-vr4130 |
11db99f8 RS |
291 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
292 | ||
6a32d874 | 293 | @item -mfix-24k |
45e279f5 | 294 | @itemx -mno-fix-24k |
6a32d874 CM |
295 | Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. |
296 | ||
d954098f DD |
297 | @item -mfix-cn63xxp1 |
298 | @itemx -mno-fix-cn63xxp1 | |
299 | Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around | |
300 | certain CN63XXP1 errata. | |
301 | ||
252b5132 RH |
302 | @item -m4010 |
303 | @itemx -no-m4010 | |
98508b2a RS |
304 | Generate code for the LSI R4010 chip. This tells the assembler to |
305 | accept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, | |
252b5132 RH |
306 | etc.), and to not schedule @samp{nop} instructions around accesses to |
307 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
308 | option. | |
309 | ||
310 | @item -m4650 | |
311 | @itemx -no-m4650 | |
98508b2a | 312 | Generate code for the MIPS R4650 chip. This tells the assembler to accept |
252b5132 RH |
313 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
314 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
315 | @samp{-no-m4650} turns off this option. | |
316 | ||
a4ac1c42 | 317 | @item -m3900 |
252b5132 RH |
318 | @itemx -no-m3900 |
319 | @itemx -m4100 | |
320 | @itemx -no-m4100 | |
321 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
98508b2a | 322 | R@var{nnnn} chip. This tells the assembler to accept instructions |
252b5132 RH |
323 | specific to that chip, and to schedule for that chip's hazards. |
324 | ||
ec68c924 | 325 | @item -march=@var{cpu} |
98508b2a | 326 | Generate code for a particular MIPS CPU. It is exactly equivalent to |
252b5132 RH |
327 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
328 | understood. Valid @var{cpu} value are: | |
329 | ||
330 | @quotation | |
331 | 2000, | |
332 | 3000, | |
333 | 3900, | |
334 | 4000, | |
335 | 4010, | |
336 | 4100, | |
337 | 4111, | |
60b63b72 RS |
338 | vr4120, |
339 | vr4130, | |
340 | vr4181, | |
252b5132 RH |
341 | 4300, |
342 | 4400, | |
343 | 4600, | |
344 | 4650, | |
345 | 5000, | |
b946ec34 NC |
346 | rm5200, |
347 | rm5230, | |
348 | rm5231, | |
349 | rm5261, | |
350 | rm5721, | |
60b63b72 RS |
351 | vr5400, |
352 | vr5500, | |
252b5132 | 353 | 6000, |
b946ec34 | 354 | rm7000, |
252b5132 | 355 | 8000, |
963ac363 | 356 | rm9000, |
e7af610e | 357 | 10000, |
18ae5d72 | 358 | 12000, |
3aa3176b TS |
359 | 14000, |
360 | 16000, | |
ad3fea08 TS |
361 | 4kc, |
362 | 4km, | |
363 | 4kp, | |
364 | 4ksc, | |
365 | 4kec, | |
366 | 4kem, | |
367 | 4kep, | |
368 | 4ksd, | |
369 | m4k, | |
370 | m4kp, | |
b5503c7b MR |
371 | m14k, |
372 | m14kc, | |
7a795ef4 MR |
373 | m14ke, |
374 | m14kec, | |
ad3fea08 | 375 | 24kc, |
0fdf1951 | 376 | 24kf2_1, |
ad3fea08 | 377 | 24kf, |
0fdf1951 | 378 | 24kf1_1, |
ad3fea08 | 379 | 24kec, |
0fdf1951 | 380 | 24kef2_1, |
ad3fea08 | 381 | 24kef, |
0fdf1951 | 382 | 24kef1_1, |
ad3fea08 | 383 | 34kc, |
0fdf1951 | 384 | 34kf2_1, |
ad3fea08 | 385 | 34kf, |
0fdf1951 | 386 | 34kf1_1, |
711eefe4 | 387 | 34kn, |
f281862d | 388 | 74kc, |
0fdf1951 | 389 | 74kf2_1, |
f281862d | 390 | 74kf, |
0fdf1951 RS |
391 | 74kf1_1, |
392 | 74kf3_2, | |
30f8113a SL |
393 | 1004kc, |
394 | 1004kf2_1, | |
395 | 1004kf, | |
396 | 1004kf1_1, | |
77403ce9 | 397 | interaptiv, |
38bf472a | 398 | interaptiv-mr2, |
c6e5c03a RS |
399 | m5100, |
400 | m5101, | |
bbaa46c0 | 401 | p5600, |
ad3fea08 TS |
402 | 5kc, |
403 | 5kf, | |
404 | 20kc, | |
405 | 25kf, | |
82100185 | 406 | sb1, |
350cc38d | 407 | sb1a, |
7ef0d297 | 408 | i6400, |
a4968f42 | 409 | p6600, |
350cc38d | 410 | loongson2e, |
037b32b9 | 411 | loongson2f, |
fd503541 | 412 | loongson3a, |
52b6b6b9 | 413 | octeon, |
dd6a37e7 | 414 | octeon+, |
432233b3 | 415 | octeon2, |
2c629856 | 416 | octeon3, |
55a36193 MK |
417 | xlr, |
418 | xlp | |
252b5132 RH |
419 | @end quotation |
420 | ||
0fdf1951 RS |
421 | For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are |
422 | accepted as synonyms for @samp{@var{n}f1_1}. These values are | |
423 | deprecated. | |
424 | ||
ec68c924 | 425 | @item -mtune=@var{cpu} |
98508b2a | 426 | Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are |
ec68c924 EC |
427 | identical to @samp{-march=@var{cpu}}. |
428 | ||
316f5878 RS |
429 | @item -mabi=@var{abi} |
430 | Record which ABI the source code uses. The recognized arguments | |
431 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
252b5132 | 432 | |
aed1a261 RS |
433 | @item -msym32 |
434 | @itemx -mno-sym32 | |
435 | @cindex -msym32 | |
436 | @cindex -mno-sym32 | |
437 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to | |
5a7560b5 | 438 | the beginning of the assembler input. @xref{MIPS Symbol Sizes}. |
aed1a261 | 439 | |
252b5132 RH |
440 | @cindex @code{-nocpp} ignored (MIPS) |
441 | @item -nocpp | |
442 | This option is ignored. It is accepted for command-line compatibility with | |
443 | other assemblers, which use it to turn off C style preprocessing. With | |
444 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
445 | @sc{gnu} assembler itself never runs the C preprocessor. | |
446 | ||
037b32b9 AN |
447 | @item -msoft-float |
448 | @itemx -mhard-float | |
449 | Disable or enable floating-point instructions. Note that by default | |
450 | floating-point instructions are always allowed even with CPU targets | |
451 | that don't have support for these instructions. | |
452 | ||
453 | @item -msingle-float | |
454 | @itemx -mdouble-float | |
455 | Disable or enable double-precision floating-point operations. Note | |
456 | that by default double-precision floating-point operations are always | |
457 | allowed even with CPU targets that don't have support for these | |
458 | operations. | |
459 | ||
119d663a NC |
460 | @item --construct-floats |
461 | @itemx --no-construct-floats | |
119d663a NC |
462 | The @code{--no-construct-floats} option disables the construction of |
463 | double width floating point constants by loading the two halves of the | |
464 | value into the two single width floating point registers that make up | |
465 | the double width register. This feature is useful if the processor | |
466 | support the FR bit in its status register, and this bit is known (by | |
467 | the programmer) to be set. This bit prevents the aliasing of the double | |
468 | width register by the single width registers. | |
469 | ||
63bf5651 | 470 | By default @code{--construct-floats} is selected, allowing construction |
119d663a NC |
471 | of these floating point constants. |
472 | ||
3bf0dbfb MR |
473 | @item --relax-branch |
474 | @itemx --no-relax-branch | |
475 | The @samp{--relax-branch} option enables the relaxation of out-of-range | |
476 | branches. Any branches whose target cannot be reached directly are | |
477 | converted to a small instruction sequence including an inverse-condition | |
478 | branch to the physically next instruction, and a jump to the original | |
479 | target is inserted between the two instructions. In PIC code the jump | |
480 | will involve further instructions for address calculation. | |
481 | ||
482 | The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, | |
483 | @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from | |
484 | relaxation, because they have no complementing counterparts. They could | |
485 | be relaxed with the use of a longer sequence involving another branch, | |
486 | however this has not been implemented and if their target turns out of | |
487 | reach, they produce an error even if branch relaxation is enabled. | |
488 | ||
81566a9b | 489 | Also no MIPS16 branches are ever relaxed. |
3bf0dbfb MR |
490 | |
491 | By default @samp{--no-relax-branch} is selected, causing any out-of-range | |
492 | branches to produce an error. | |
493 | ||
8b10b0b3 MR |
494 | @item -mignore-branch-isa |
495 | @itemx -mno-ignore-branch-isa | |
496 | Ignore branch checks for invalid transitions between ISA modes. | |
497 | ||
498 | The semantics of branches does not provide for an ISA mode switch, so in | |
499 | most cases the ISA mode a branch has been encoded for has to be the same | |
500 | as the ISA mode of the branch's target label. If the ISA modes do not | |
501 | match, then such a branch, if taken, will cause the ISA mode to remain | |
502 | unchanged and instructions that follow will be executed in the wrong ISA | |
503 | mode causing the program to misbehave or crash. | |
504 | ||
505 | In the case of the @code{BAL} instruction it may be possible to relax | |
506 | it to an equivalent @code{JALX} instruction so that the ISA mode is | |
507 | switched at the run time as required. For other branches no relaxation | |
508 | is possible and therefore GAS has checks implemented that verify in | |
509 | branch assembly that the two ISA modes match, and report an error | |
510 | otherwise so that the problem with code can be diagnosed at the assembly | |
511 | time rather than at the run time. | |
512 | ||
513 | However some assembly code, including generated code produced by some | |
514 | versions of GCC, may incorrectly include branches to data labels, which | |
515 | appear to require a mode switch but are either dead or immediately | |
516 | followed by valid instructions encoded for the same ISA the branch has | |
517 | been encoded for. While not strictly correct at the source level such | |
518 | code will execute as intended, so to help with these cases | |
519 | @samp{-mignore-branch-isa} is supported which disables ISA mode checks | |
520 | for branches. | |
521 | ||
522 | By default @samp{-mno-ignore-branch-isa} is selected, causing any invalid | |
523 | branch requiring a transition between ISA modes to produce an error. | |
524 | ||
ba92f887 MR |
525 | @cindex @option{-mnan=} command line option, MIPS |
526 | @item -mnan=@var{encoding} | |
527 | This option indicates whether the source code uses the IEEE 2008 | |
528 | NaN encoding (@option{-mnan=2008}) or the original MIPS encoding | |
529 | (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} | |
530 | directive to the beginning of the source file. @xref{MIPS NaN Encodings}. | |
531 | ||
532 | @option{-mnan=legacy} is the default if no @option{-mnan} option or | |
533 | @code{.nan} directive is used. | |
534 | ||
252b5132 RH |
535 | @item --trap |
536 | @itemx --no-break | |
537 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
538 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
539 | @code{@value{AS}} automatically macro expands certain division and | |
540 | multiplication instructions to check for overflow and division by zero. This | |
541 | option causes @code{@value{AS}} to generate code to take a trap exception | |
542 | rather than a break exception when an error is detected. The trap instructions | |
543 | are only supported at Instruction Set Architecture level 2 and higher. | |
544 | ||
545 | @item --break | |
546 | @itemx --no-trap | |
547 | Generate code to take a break exception rather than a trap exception when an | |
548 | error is detected. This is the default. | |
63486801 | 549 | |
dcd410fe RO |
550 | @item -mpdr |
551 | @itemx -mno-pdr | |
552 | Control generation of @code{.pdr} sections. Off by default on IRIX, on | |
553 | elsewhere. | |
aa6975fb ILT |
554 | |
555 | @item -mshared | |
556 | @itemx -mno-shared | |
557 | When generating code using the Unix calling conventions (selected by | |
558 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code | |
559 | which can go into a shared library. The @samp{-mno-shared} option | |
560 | tells gas to generate code which uses the calling convention, but can | |
561 | not go into a shared library. The resulting code is slightly more | |
562 | efficient. This option only affects the handling of the | |
563 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. | |
252b5132 RH |
564 | @end table |
565 | ||
fc16f8cc RS |
566 | @node MIPS Macros |
567 | @section High-level assembly macros | |
568 | ||
569 | MIPS assemblers have traditionally provided a wider range of | |
570 | instructions than the MIPS architecture itself. These extra | |
571 | instructions are usually referred to as ``macro'' instructions | |
572 | @footnote{The term ``macro'' is somewhat overloaded here, since | |
573 | these macros have no relation to those defined by @code{.macro}, | |
574 | @pxref{Macro,, @code{.macro}}.}. | |
575 | ||
576 | Some MIPS macro instructions extend an underlying architectural instruction | |
577 | while others are entirely new. An example of the former type is @code{and}, | |
578 | which allows the third operand to be either a register or an arbitrary | |
579 | immediate value. Examples of the latter type include @code{bgt}, which | |
580 | branches to the third operand when the first operand is greater than | |
581 | the second operand, and @code{ulh}, which implements an unaligned | |
582 | 2-byte load. | |
583 | ||
584 | One of the most common extensions provided by macros is to expand | |
585 | memory offsets to the full address range (32 or 64 bits) and to allow | |
586 | symbolic offsets such as @samp{my_data + 4} to be used in place of | |
587 | integer constants. For example, the architectural instruction | |
588 | @code{lbu} allows only a signed 16-bit offset, whereas the macro | |
589 | @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. | |
590 | The implementation of these symbolic offsets depends on several factors, | |
98508b2a RS |
591 | such as whether the assembler is generating SVR4-style PIC (selected by |
592 | @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols | |
fc16f8cc RS |
593 | (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), |
594 | and the small data limit (@pxref{MIPS Small Data,, Controlling the use | |
595 | of small data accesses}). | |
596 | ||
597 | @kindex @code{.set macro} | |
598 | @kindex @code{.set nomacro} | |
599 | Sometimes it is undesirable to have one assembly instruction expand | |
600 | to several machine instructions. The directive @code{.set nomacro} | |
601 | tells the assembler to warn when this happens. @code{.set macro} | |
602 | restores the default behavior. | |
603 | ||
604 | @cindex @code{at} register, MIPS | |
605 | @kindex @code{.set at=@var{reg}} | |
606 | Some macro instructions need a temporary register to store intermediate | |
607 | results. This register is usually @code{$1}, also known as @code{$at}, | |
608 | but it can be changed to any core register @var{reg} using | |
609 | @code{.set at=@var{reg}}. Note that @code{$at} always refers | |
610 | to @code{$1} regardless of which register is being used as the | |
611 | temporary register. | |
612 | ||
613 | @kindex @code{.set at} | |
614 | @kindex @code{.set noat} | |
615 | Implicit uses of the temporary register in macros could interfere with | |
616 | explicit uses in the assembly code. The assembler therefore warns | |
617 | whenever it sees an explicit use of the temporary register. The directive | |
618 | @code{.set noat} silences this warning while @code{.set at} restores | |
619 | the default behavior. It is safe to use @code{.set noat} while | |
620 | @code{.set nomacro} is in effect since single-instruction macros | |
621 | never need a temporary register. | |
622 | ||
623 | Note that while the @sc{gnu} assembler provides these macros for compatibility, | |
624 | it does not make any attempt to optimize them with the surrounding code. | |
625 | ||
5a7560b5 | 626 | @node MIPS Symbol Sizes |
aed1a261 RS |
627 | @section Directives to override the size of symbols |
628 | ||
5a7560b5 RS |
629 | @kindex @code{.set sym32} |
630 | @kindex @code{.set nosym32} | |
aed1a261 RS |
631 | The n64 ABI allows symbols to have any 64-bit value. Although this |
632 | provides a great deal of flexibility, it means that some macros have | |
633 | much longer expansions than their 32-bit counterparts. For example, | |
634 | the non-PIC expansion of @samp{dla $4,sym} is usually: | |
635 | ||
636 | @smallexample | |
637 | lui $4,%highest(sym) | |
638 | lui $1,%hi(sym) | |
639 | daddiu $4,$4,%higher(sym) | |
640 | daddiu $1,$1,%lo(sym) | |
641 | dsll32 $4,$4,0 | |
642 | daddu $4,$4,$1 | |
643 | @end smallexample | |
644 | ||
645 | whereas the 32-bit expansion is simply: | |
646 | ||
647 | @smallexample | |
648 | lui $4,%hi(sym) | |
649 | daddiu $4,$4,%lo(sym) | |
650 | @end smallexample | |
651 | ||
652 | n64 code is sometimes constructed in such a way that all symbolic | |
653 | constants are known to have 32-bit values, and in such cases, it's | |
654 | preferable to use the 32-bit expansion instead of the 64-bit | |
655 | expansion. | |
656 | ||
657 | You can use the @code{.set sym32} directive to tell the assembler | |
658 | that, from this point on, all expressions of the form | |
659 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} | |
660 | have 32-bit values. For example: | |
661 | ||
662 | @smallexample | |
663 | .set sym32 | |
664 | dla $4,sym | |
665 | lw $4,sym+16 | |
666 | sw $4,sym+0x8000($4) | |
667 | @end smallexample | |
668 | ||
669 | will cause the assembler to treat @samp{sym}, @code{sym+16} and | |
670 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic | |
671 | addresses is not affected. | |
672 | ||
673 | The directive @code{.set nosym32} ends a @code{.set sym32} block and | |
674 | reverts to the normal behavior. It is also possible to change the | |
675 | symbol size using the command-line options @option{-msym32} and | |
676 | @option{-mno-sym32}. | |
677 | ||
678 | These options and directives are always accepted, but at present, | |
679 | they have no effect for anything other than n64. | |
680 | ||
fc16f8cc RS |
681 | @node MIPS Small Data |
682 | @section Controlling the use of small data accesses | |
5a7560b5 | 683 | |
fc16f8cc RS |
684 | @c This section deliberately glosses over the possibility of using -G |
685 | @c in SVR4-style PIC, as could be done on IRIX. We don't support that. | |
686 | @cindex small data, MIPS | |
5a7560b5 | 687 | @cindex @code{gp} register, MIPS |
fc16f8cc RS |
688 | It often takes several instructions to load the address of a symbol. |
689 | For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion | |
690 | of @samp{dla $4,addr} is usually: | |
691 | ||
692 | @smallexample | |
693 | lui $4,%hi(addr) | |
694 | daddiu $4,$4,%lo(addr) | |
695 | @end smallexample | |
696 | ||
697 | The sequence is much longer when @samp{addr} is a 64-bit symbol. | |
698 | @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. | |
699 | ||
700 | In order to cut down on this overhead, most embedded MIPS systems | |
701 | set aside a 64-kilobyte ``small data'' area and guarantee that all | |
702 | data of size @var{n} and smaller will be placed in that area. | |
703 | The limit @var{n} is passed to both the assembler and the linker | |
98508b2a | 704 | using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, |
fc16f8cc RS |
705 | Assembler options}. Note that the same value of @var{n} must be used |
706 | when linking and when assembling all input files to the link; any | |
707 | inconsistency could cause a relocation overflow error. | |
708 | ||
709 | The size of an object in the @code{.bss} section is set by the | |
710 | @code{.comm} or @code{.lcomm} directive that defines it. The size of | |
711 | an external object may be set with the @code{.extern} directive. For | |
712 | example, @samp{.extern sym,4} declares that the object at @code{sym} | |
713 | is 4 bytes in length, while leaving @code{sym} otherwise undefined. | |
714 | ||
715 | When no @option{-G} option is given, the default limit is 8 bytes. | |
716 | The option @option{-G 0} prevents any data from being automatically | |
717 | classified as small. | |
718 | ||
719 | It is also possible to mark specific objects as small by putting them | |
720 | in the special sections @code{.sdata} and @code{.sbss}, which are | |
721 | ``small'' counterparts of @code{.data} and @code{.bss} respectively. | |
722 | The toolchain will treat such data as small regardless of the | |
723 | @option{-G} setting. | |
724 | ||
725 | On startup, systems that support a small data area are expected to | |
726 | initialize register @code{$28}, also known as @code{$gp}, in such a | |
727 | way that small data can be accessed using a 16-bit offset from that | |
728 | register. For example, when @samp{addr} is small data, | |
729 | the @samp{dla $4,addr} instruction above is equivalent to: | |
730 | ||
731 | @smallexample | |
732 | daddiu $4,$28,%gp_rel(addr) | |
733 | @end smallexample | |
734 | ||
735 | Small data is not supported for SVR4-style PIC. | |
5a7560b5 | 736 | |
252b5132 RH |
737 | @node MIPS ISA |
738 | @section Directives to override the ISA level | |
739 | ||
740 | @cindex MIPS ISA override | |
741 | @kindex @code{.set mips@var{n}} | |
742 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
98508b2a | 743 | the MIPS Instruction Set Architecture level on the fly: @code{.set |
ae52f483 | 744 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, |
7361da2c | 745 | 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. |
071742cf | 746 | The values other than 0 make the assembler accept instructions |
e335d9cb | 747 | for the corresponding ISA level, from that point on in the |
584da044 NC |
748 | assembly. @code{.set mips@var{n}} affects not only which instructions |
749 | are permitted, but also how certain macros are expanded. @code{.set | |
e335d9cb | 750 | mips0} restores the ISA level to its original level: either the |
584da044 | 751 | level you selected with command line options, or the default for your |
81566a9b | 752 | configuration. You can use this feature to permit specific MIPS III |
584da044 | 753 | instructions while assembling in 32 bit mode. Use this directive with |
ec68c924 | 754 | care! |
252b5132 | 755 | |
ad3fea08 TS |
756 | @cindex MIPS CPU override |
757 | @kindex @code{.set arch=@var{cpu}} | |
758 | The @code{.set arch=@var{cpu}} directive provides even finer control. | |
759 | It changes the effective CPU target and allows the assembler to use | |
760 | instructions specific to a particular CPU. All CPUs supported by the | |
761 | @samp{-march} command line option are also selectable by this directive. | |
762 | The original value is restored by @code{.set arch=default}. | |
252b5132 | 763 | |
ad3fea08 TS |
764 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
765 | in which it will assemble instructions for the MIPS 16 processor. Use | |
766 | @code{.set nomips16} to return to normal 32 bit mode. | |
e16bfa71 | 767 | |
98508b2a | 768 | Traditional MIPS assemblers do not support this directive. |
252b5132 | 769 | |
df58fc94 RS |
770 | The directive @code{.set micromips} puts the assembler into microMIPS mode, |
771 | in which it will assemble instructions for the microMIPS processor. Use | |
772 | @code{.set nomicromips} to return to normal 32 bit mode. | |
773 | ||
98508b2a | 774 | Traditional MIPS assemblers do not support this directive. |
df58fc94 | 775 | |
833794fc MR |
776 | @node MIPS assembly options |
777 | @section Directives to control code generation | |
778 | ||
919731af | 779 | @cindex MIPS directives to override command line options |
780 | @kindex @code{.module} | |
781 | The @code{.module} directive allows command line options to be set directly | |
782 | from assembly. The format of the directive matches the @code{.set} | |
783 | directive but only those options which are relevant to a whole module are | |
784 | supported. The effect of a @code{.module} directive is the same as the | |
785 | corresponding command line option. Where @code{.set} directives support | |
786 | returning to a default then the @code{.module} directives do not as they | |
787 | define the defaults. | |
788 | ||
789 | These module-level directives must appear first in assembly. | |
790 | ||
791 | Traditional MIPS assemblers do not support this directive. | |
792 | ||
833794fc MR |
793 | @cindex MIPS 32-bit microMIPS instruction generation override |
794 | @kindex @code{.set insn32} | |
795 | @kindex @code{.set noinsn32} | |
796 | The directive @code{.set insn32} makes the assembler only use 32-bit | |
797 | instruction encodings when generating code for the microMIPS processor. | |
798 | This directive inhibits the use of any 16-bit instructions from that | |
799 | point on in the assembly. The @code{.set noinsn32} directive allows | |
800 | 16-bit instructions to be accepted. | |
801 | ||
802 | Traditional MIPS assemblers do not support this directive. | |
803 | ||
252b5132 RH |
804 | @node MIPS autoextend |
805 | @section Directives for extending MIPS 16 bit instructions | |
806 | ||
807 | @kindex @code{.set autoextend} | |
808 | @kindex @code{.set noautoextend} | |
809 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
ad3fea08 TS |
810 | when necessary. The directive @code{.set noautoextend} will turn this |
811 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction | |
812 | must be explicitly extended with the @code{.e} modifier (e.g., | |
813 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used | |
252b5132 RH |
814 | to once again automatically extend instructions when necessary. |
815 | ||
816 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
98508b2a | 817 | MIPS assemblers do not support this directive. |
252b5132 RH |
818 | |
819 | @node MIPS insn | |
820 | @section Directive to mark data as an instruction | |
821 | ||
822 | @kindex @code{.insn} | |
823 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
df58fc94 RS |
824 | data is actually instructions. This makes a difference in MIPS 16 and |
825 | microMIPS modes: when loading the address of a label which precedes | |
826 | instructions, @code{@value{AS}} automatically adds 1 to the value, so | |
827 | that jumping to the loaded address will do the right thing. | |
252b5132 | 828 | |
a946d7e3 NC |
829 | @kindex @code{.global} |
830 | The @code{.global} and @code{.globl} directives supported by | |
831 | @code{@value{AS}} will by default mark the symbol as pointing to a | |
832 | region of data not code. This means that, for example, any | |
833 | instructions following such a symbol will not be disassembled by | |
f746e6b9 | 834 | @code{objdump} as it will regard them as data. To change this |
f179c512 | 835 | behavior an optional section name can be placed after the symbol name |
a946d7e3 | 836 | in the @code{.global} directive. If this section exists and is known |
f179c512 | 837 | to be a code section, then the symbol will be marked as pointing at |
a946d7e3 NC |
838 | code not data. Ie the syntax for the directive is: |
839 | ||
840 | @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, | |
841 | ||
842 | Here is a short example: | |
843 | ||
844 | @example | |
845 | .global foo .text, bar, baz .data | |
846 | foo: | |
847 | nop | |
848 | bar: | |
849 | .word 0x0 | |
850 | baz: | |
851 | .word 0x1 | |
34bca508 | 852 | |
a946d7e3 NC |
853 | @end example |
854 | ||
351cdf24 MF |
855 | @node MIPS FP ABIs |
856 | @section Directives to control the FP ABI | |
857 | @menu | |
858 | * MIPS FP ABI History:: History of FP ABIs | |
859 | * MIPS FP ABI Variants:: Supported FP ABIs | |
860 | * MIPS FP ABI Selection:: Automatic selection of FP ABI | |
861 | * MIPS FP ABI Compatibility:: Linking different FP ABI variants | |
862 | @end menu | |
863 | ||
864 | @node MIPS FP ABI History | |
865 | @subsection History of FP ABIs | |
866 | @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS | |
867 | @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS | |
868 | The MIPS ABIs support a variety of different floating-point extensions | |
869 | where calling-convention and register sizes vary for floating-point data. | |
870 | The extensions exist to support a wide variety of optional architecture | |
871 | features. The resulting ABI variants are generally incompatible with each | |
872 | other and must be tracked carefully. | |
873 | ||
874 | Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} | |
875 | directive is used to indicate which ABI is in use by a specific module. | |
876 | It was then left to the user to ensure that command line options and the | |
877 | selected ABI were compatible with some potential for inconsistencies. | |
878 | ||
879 | @node MIPS FP ABI Variants | |
880 | @subsection Supported FP ABIs | |
881 | The supported floating-point ABI variants are: | |
882 | ||
883 | @table @code | |
884 | @item 0 - No floating-point | |
885 | This variant is used to indicate that floating-point is not used within | |
886 | the module at all and therefore has no impact on the ABI. This is the | |
887 | default. | |
888 | ||
889 | @item 1 - Double-precision | |
890 | This variant indicates that double-precision support is used. For 64-bit | |
891 | ABIs this means that 64-bit wide floating-point registers are required. | |
892 | For 32-bit ABIs this means that 32-bit wide floating-point registers are | |
893 | required and double-precision operations use pairs of registers. | |
894 | ||
895 | @item 2 - Single-precision | |
896 | This variant indicates that single-precision support is used. Double | |
897 | precision operations will be supported via soft-float routines. | |
898 | ||
899 | @item 3 - Soft-float | |
900 | This variant indicates that although floating-point support is used all | |
901 | operations are emulated in software. This means the ABI is modified to | |
902 | pass all floating-point data in general-purpose registers. | |
903 | ||
904 | @item 4 - Deprecated | |
905 | This variant existed as an initial attempt at supporting 64-bit wide | |
f179c512 MF |
906 | floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been |
907 | superseded by 5, 6 and 7. | |
351cdf24 MF |
908 | |
909 | @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU | |
910 | This variant is used by 32-bit ABIs to indicate that the floating-point | |
911 | code in the module has been designed to operate correctly with either | |
912 | 32-bit wide or 64-bit wide floating-point registers. Double-precision | |
913 | support is used. Only O32 currently supports this variant and requires | |
914 | a minimum architecture of MIPS II. | |
915 | ||
916 | @item 6 - Double-precision 32-bit FPU, 64-bit FPU | |
917 | This variant is used by 32-bit ABIs to indicate that the floating-point | |
918 | code in the module requires 64-bit wide floating-point registers. | |
919 | Double-precision support is used. Only O32 currently supports this | |
920 | variant and requires a minimum architecture of MIPS32r2. | |
921 | ||
922 | @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU | |
923 | This variant is used by 32-bit ABIs to indicate that the floating-point | |
924 | code in the module requires 64-bit wide floating-point registers. | |
925 | Double-precision support is used. This differs from the previous ABI | |
926 | as it restricts use of odd-numbered single-precision registers. Only | |
927 | O32 currently supports this variant and requires a minimum architecture | |
928 | of MIPS32r2. | |
929 | @end table | |
930 | ||
931 | @node MIPS FP ABI Selection | |
932 | @subsection Automatic selection of FP ABI | |
933 | @cindex @code{.module fp=@var{nn}} directive, MIPS | |
934 | In order to simplify and add safety to the process of selecting the | |
935 | correct floating-point ABI, the assembler will automatically infer the | |
936 | correct @code{.gnu_attribute 4, @var{n}} directive based on command line | |
937 | options and @code{.module} overrides. Where an explicit | |
938 | @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning | |
939 | will be raised if it does not match an inferred setting. | |
940 | ||
941 | The floating-point ABI is inferred as follows. If @samp{-msoft-float} | |
942 | has been used the module will be marked as soft-float. If | |
943 | @samp{-msingle-float} has been used then the module will be marked as | |
944 | single-precision. The remaining ABIs are then selected based | |
945 | on the FP register width. Double-precision is selected if the width | |
946 | of GP and FP registers match and the special double-precision variants | |
947 | for 32-bit ABIs are then selected depending on @samp{-mfpxx}, | |
948 | @samp{-mfp64} and @samp{-mno-odd-spreg}. | |
949 | ||
950 | @node MIPS FP ABI Compatibility | |
951 | @subsection Linking different FP ABI variants | |
952 | Modules using the default FP ABI (no floating-point) can be linked with | |
953 | any other (singular) FP ABI variant. | |
954 | ||
955 | Special compatibility support exists for O32 with the four | |
956 | double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically | |
957 | designed to be compatible with the standard double-precision ABI and the | |
958 | @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be | |
959 | built as @samp{-mfpxx} to ensure the maximum compatibility with other | |
960 | modules produced for more specific needs. The only FP ABIs which cannot | |
961 | be linked together are the standard double-precision ABI and the full | |
962 | @samp{-mfp64} ABI with @samp{-modd-spreg}. | |
963 | ||
ba92f887 MR |
964 | @node MIPS NaN Encodings |
965 | @section Directives to record which NaN encoding is being used | |
966 | ||
967 | @cindex MIPS IEEE 754 NaN data encoding selection | |
968 | @cindex @code{.nan} directive, MIPS | |
969 | The IEEE 754 floating-point standard defines two types of not-a-number | |
970 | (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version | |
971 | of the standard did not specify how these two types should be | |
972 | distinguished. Most implementations followed the i387 model, in which | |
973 | the first bit of the significand is set for quiet NaNs and clear for | |
974 | signalling NaNs. However, the original MIPS implementation assigned the | |
975 | opposite meaning to the bit, so that it was set for signalling NaNs and | |
976 | clear for quiet NaNs. | |
977 | ||
978 | The 2008 revision of the standard formally suggested the i387 choice | |
979 | and as from Sep 2012 the current release of the MIPS architecture | |
980 | therefore optionally supports that form. Code that uses one NaN encoding | |
981 | would usually be incompatible with code that uses the other NaN encoding, | |
982 | so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which | |
983 | encoding is being used. | |
984 | ||
985 | Assembly files can use the @code{.nan} directive to select between the | |
986 | two encodings. @samp{.nan 2008} says that the assembly file uses the | |
987 | IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses | |
988 | the original MIPS encoding. If several @code{.nan} directives are given, | |
989 | the final setting is the one that is used. | |
990 | ||
991 | The command-line options @option{-mnan=legacy} and @option{-mnan=2008} | |
992 | can be used instead of @samp{.nan legacy} and @samp{.nan 2008} | |
993 | respectively. However, any @code{.nan} directive overrides the | |
994 | command-line setting. | |
995 | ||
996 | @samp{.nan legacy} is the default if no @code{.nan} directive or | |
997 | @option{-mnan} option is given. | |
998 | ||
999 | Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and | |
1000 | therefore these directives do not affect code generation. They simply | |
1001 | control the setting of the @code{EF_MIPS_NAN2008} flag. | |
1002 | ||
1003 | Traditional MIPS assemblers do not support these directives. | |
1004 | ||
98508b2a | 1005 | @node MIPS Option Stack |
252b5132 RH |
1006 | @section Directives to save and restore options |
1007 | ||
1008 | @cindex MIPS option stack | |
1009 | @kindex @code{.set push} | |
1010 | @kindex @code{.set pop} | |
1011 | The directives @code{.set push} and @code{.set pop} may be used to save | |
1012 | and restore the current settings for all the options which are | |
1013 | controlled by @code{.set}. The @code{.set push} directive saves the | |
1014 | current settings on a stack. The @code{.set pop} directive pops the | |
1015 | stack and restores the settings. | |
1016 | ||
1017 | These directives can be useful inside an macro which must change an | |
1018 | option such as the ISA level or instruction reordering but does not want | |
1019 | to change the state of the code which invoked the macro. | |
1020 | ||
98508b2a | 1021 | Traditional MIPS assemblers do not support these directives. |
1f25f5d3 | 1022 | |
98508b2a | 1023 | @node MIPS ASE Instruction Generation Overrides |
1f25f5d3 CD |
1024 | @section Directives to control generation of MIPS ASE instructions |
1025 | ||
1026 | @cindex MIPS MIPS-3D instruction generation override | |
1027 | @kindex @code{.set mips3d} | |
1028 | @kindex @code{.set nomips3d} | |
1029 | The directive @code{.set mips3d} makes the assembler accept instructions | |
1030 | from the MIPS-3D Application Specific Extension from that point on | |
1031 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
1032 | instructions from being accepted. | |
1033 | ||
ad3fea08 TS |
1034 | @cindex SmartMIPS instruction generation override |
1035 | @kindex @code{.set smartmips} | |
1036 | @kindex @code{.set nosmartmips} | |
1037 | The directive @code{.set smartmips} makes the assembler accept | |
1038 | instructions from the SmartMIPS Application Specific Extension to the | |
e335d9cb | 1039 | MIPS32 ISA from that point on in the assembly. The |
ad3fea08 TS |
1040 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from |
1041 | being accepted. | |
1042 | ||
deec1734 CD |
1043 | @cindex MIPS MDMX instruction generation override |
1044 | @kindex @code{.set mdmx} | |
1045 | @kindex @code{.set nomdmx} | |
1046 | The directive @code{.set mdmx} makes the assembler accept instructions | |
1047 | from the MDMX Application Specific Extension from that point on | |
1048 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
1049 | instructions from being accepted. | |
1050 | ||
8b082fb1 | 1051 | @cindex MIPS DSP Release 1 instruction generation override |
2ef2b9ae CF |
1052 | @kindex @code{.set dsp} |
1053 | @kindex @code{.set nodsp} | |
1054 | The directive @code{.set dsp} makes the assembler accept instructions | |
8b082fb1 TS |
1055 | from the DSP Release 1 Application Specific Extension from that point |
1056 | on in the assembly. The @code{.set nodsp} directive prevents DSP | |
1057 | Release 1 instructions from being accepted. | |
1058 | ||
1059 | @cindex MIPS DSP Release 2 instruction generation override | |
1060 | @kindex @code{.set dspr2} | |
1061 | @kindex @code{.set nodspr2} | |
1062 | The directive @code{.set dspr2} makes the assembler accept instructions | |
1063 | from the DSP Release 2 Application Specific Extension from that point | |
f179c512 | 1064 | on in the assembly. This directive implies @code{.set dsp}. The |
8b082fb1 TS |
1065 | @code{.set nodspr2} directive prevents DSP Release 2 instructions from |
1066 | being accepted. | |
2ef2b9ae | 1067 | |
8f4f9071 MF |
1068 | @cindex MIPS DSP Release 3 instruction generation override |
1069 | @kindex @code{.set dspr3} | |
1070 | @kindex @code{.set nodspr3} | |
1071 | The directive @code{.set dspr3} makes the assembler accept instructions | |
1072 | from the DSP Release 3 Application Specific Extension from that point | |
1073 | on in the assembly. This directive implies @code{.set dsp} and | |
1074 | @code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP | |
1075 | Release 3 instructions from being accepted. | |
1076 | ||
ef2e4d86 CF |
1077 | @cindex MIPS MT instruction generation override |
1078 | @kindex @code{.set mt} | |
1079 | @kindex @code{.set nomt} | |
1080 | The directive @code{.set mt} makes the assembler accept instructions | |
1081 | from the MT Application Specific Extension from that point on | |
1082 | in the assembly. The @code{.set nomt} directive prevents MT | |
1083 | instructions from being accepted. | |
1084 | ||
dec0624d MR |
1085 | @cindex MIPS MCU instruction generation override |
1086 | @kindex @code{.set mcu} | |
1087 | @kindex @code{.set nomcu} | |
1088 | The directive @code{.set mcu} makes the assembler accept instructions | |
1089 | from the MCU Application Specific Extension from that point on | |
1090 | in the assembly. The @code{.set nomcu} directive prevents MCU | |
1091 | instructions from being accepted. | |
1092 | ||
56d438b1 CF |
1093 | @cindex MIPS SIMD Architecture instruction generation override |
1094 | @kindex @code{.set msa} | |
1095 | @kindex @code{.set nomsa} | |
1096 | The directive @code{.set msa} makes the assembler accept instructions | |
1097 | from the MIPS SIMD Architecture Extension from that point on | |
1098 | in the assembly. The @code{.set nomsa} directive prevents MSA | |
1099 | instructions from being accepted. | |
1100 | ||
b015e599 AP |
1101 | @cindex Virtualization instruction generation override |
1102 | @kindex @code{.set virt} | |
1103 | @kindex @code{.set novirt} | |
1104 | The directive @code{.set virt} makes the assembler accept instructions | |
1105 | from the Virtualization Application Specific Extension from that point | |
1106 | on in the assembly. The @code{.set novirt} directive prevents Virtualization | |
1107 | instructions from being accepted. | |
1108 | ||
7d64c587 AB |
1109 | @cindex MIPS eXtended Physical Address (XPA) instruction generation override |
1110 | @kindex @code{.set xpa} | |
1111 | @kindex @code{.set noxpa} | |
1112 | The directive @code{.set xpa} makes the assembler accept instructions | |
1113 | from the XPA Extension from that point on in the assembly. The | |
1114 | @code{.set noxpa} directive prevents XPA instructions from being accepted. | |
1115 | ||
25499ac7 MR |
1116 | @cindex MIPS16e2 instruction generation override |
1117 | @kindex @code{.set mips16e2} | |
1118 | @kindex @code{.set nomips16e2} | |
1119 | The directive @code{.set mips16e2} makes the assembler accept instructions | |
1120 | from the MIPS16e2 Application Specific Extension from that point on in the | |
75c80ee1 MR |
1121 | assembly, whenever in MIPS16 mode. The @code{.set nomips16e2} directive |
1122 | prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither | |
25499ac7 MR |
1123 | directive affects the state of MIPS16 mode being active itself which has |
1124 | separate controls. | |
1125 | ||
730c3174 SE |
1126 | @cindex MIPS cyclic redundancy check (CRC) instruction generation override |
1127 | @kindex @code{.set crc} | |
1128 | @kindex @code{.set nocrc} | |
1129 | The directive @code{.set crc} makes the assembler accept instructions | |
1130 | from the CRC Extension from that point on in the assembly. The | |
1131 | @code{.set nocrc} directive prevents CRC instructions from being accepted. | |
1132 | ||
6f20c942 FS |
1133 | @cindex MIPS Global INValidate (GINV) instruction generation override |
1134 | @kindex @code{.set ginv} | |
1135 | @kindex @code{.set noginv} | |
1136 | The directive @code{.set ginv} makes the assembler accept instructions | |
1137 | from the GINV Extension from that point on in the assembly. The | |
1138 | @code{.set noginv} directive prevents GINV instructions from being accepted. | |
1139 | ||
98508b2a | 1140 | Traditional MIPS assemblers do not support these directives. |
037b32b9 | 1141 | |
98508b2a | 1142 | @node MIPS Floating-Point |
037b32b9 AN |
1143 | @section Directives to override floating-point options |
1144 | ||
1145 | @cindex Disable floating-point instructions | |
1146 | @kindex @code{.set softfloat} | |
1147 | @kindex @code{.set hardfloat} | |
1148 | The directives @code{.set softfloat} and @code{.set hardfloat} provide | |
1149 | finer control of disabling and enabling float-point instructions. | |
1150 | These directives always override the default (that hard-float | |
1151 | instructions are accepted) or the command-line options | |
1152 | (@samp{-msoft-float} and @samp{-mhard-float}). | |
1153 | ||
1154 | @cindex Disable single-precision floating-point operations | |
605b1dd4 NH |
1155 | @kindex @code{.set singlefloat} |
1156 | @kindex @code{.set doublefloat} | |
037b32b9 AN |
1157 | The directives @code{.set singlefloat} and @code{.set doublefloat} |
1158 | provide finer control of disabling and enabling double-precision | |
1159 | float-point operations. These directives always override the default | |
1160 | (that double-precision operations are accepted) or the command-line | |
1161 | options (@samp{-msingle-float} and @samp{-mdouble-float}). | |
1162 | ||
98508b2a | 1163 | Traditional MIPS assemblers do not support these directives. |
7c31ae13 NC |
1164 | |
1165 | @node MIPS Syntax | |
1166 | @section Syntactical considerations for the MIPS assembler | |
1167 | @menu | |
1168 | * MIPS-Chars:: Special Characters | |
1169 | @end menu | |
1170 | ||
1171 | @node MIPS-Chars | |
1172 | @subsection Special Characters | |
1173 | ||
1174 | @cindex line comment character, MIPS | |
1175 | @cindex MIPS line comment character | |
1176 | The presence of a @samp{#} on a line indicates the start of a comment | |
1177 | that extends to the end of the current line. | |
1178 | ||
1179 | If a @samp{#} appears as the first character of a line, the whole line | |
1180 | is treated as a comment, but in this case the line can also be a | |
1181 | logical line number directive (@pxref{Comments}) or a | |
1182 | preprocessor control command (@pxref{Preprocessing}). | |
1183 | ||
1184 | @cindex line separator, MIPS | |
1185 | @cindex statement separator, MIPS | |
1186 | @cindex MIPS line separator | |
1187 | The @samp{;} character can be used to separate statements on the same | |
1188 | line. |