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1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000 |
2 | @c Free Software Foundation, Inc. | |
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3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @ifset GENERIC | |
6 | @page | |
7 | @node MIPS-Dependent | |
8 | @chapter MIPS Dependent Features | |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter MIPS Dependent Features | |
13 | @end ifclear | |
14 | ||
15 | @cindex MIPS processor | |
16 | @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several | |
84ea6cf2 | 17 | different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, |
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18 | and MIPS64. For information about the @sc{mips} instruction set, see |
19 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). | |
20 | For an overview of @sc{mips} assembly conventions, see ``Appendix D: | |
21 | Assembly Language Programming'' in the same work. | |
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22 | |
23 | @menu | |
24 | * MIPS Opts:: Assembler options | |
25 | * MIPS Object:: ECOFF object code | |
26 | * MIPS Stabs:: Directives for debugging information | |
27 | * MIPS ISA:: Directives to override the ISA level | |
28 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions | |
29 | * MIPS insn:: Directive to mark data as an instruction | |
30 | * MIPS option stack:: Directives to save and restore options | |
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31 | * MIPS ASE instruction generation overrides:: Directives to control |
32 | generation of MIPS ASE instructions | |
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33 | @end menu |
34 | ||
35 | @node MIPS Opts | |
36 | @section Assembler options | |
37 | ||
38 | The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these | |
39 | special options: | |
40 | ||
41 | @table @code | |
42 | @cindex @code{-G} option (MIPS) | |
43 | @item -G @var{num} | |
44 | This option sets the largest size of an object that can be referenced | |
45 | implicitly with the @code{gp} register. It is only accepted for targets | |
46 | that use @sc{ecoff} format. The default value is 8. | |
47 | ||
48 | @cindex @code{-EB} option (MIPS) | |
49 | @cindex @code{-EL} option (MIPS) | |
50 | @cindex MIPS big-endian output | |
51 | @cindex MIPS little-endian output | |
52 | @cindex big-endian output, MIPS | |
53 | @cindex little-endian output, MIPS | |
54 | @item -EB | |
55 | @itemx -EL | |
56 | Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or | |
57 | little-endian output at run time (unlike the other @sc{gnu} development | |
58 | tools, which must be configured for one or the other). Use @samp{-EB} | |
59 | to select big-endian output, and @samp{-EL} for little-endian. | |
60 | ||
61 | @cindex MIPS architecture options | |
62 | @item -mips1 | |
63 | @itemx -mips2 | |
64 | @itemx -mips3 | |
65 | @itemx -mips4 | |
84ea6cf2 | 66 | @itemx -mips5 |
e7af610e | 67 | @itemx -mips32 |
af7ee8bf | 68 | @itemx -mips32r2 |
84ea6cf2 | 69 | @itemx -mips64 |
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70 | Generate code for a particular MIPS Instruction Set Architecture level. |
71 | @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, | |
72 | @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the | |
84ea6cf2 | 73 | @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and |
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74 | @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, and |
75 | @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, | |
76 | @sc{MIPS32 Release 2}, and | |
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77 | @sc{MIPS64} ISA processors, respectively. You can also switch |
78 | instruction sets during the assembly; see @ref{MIPS ISA, Directives to | |
ec68c924 | 79 | override the ISA level}. |
252b5132 | 80 | |
6349b5f4 | 81 | @item -mgp32 |
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82 | @itemx -mfp32 |
83 | Some macros have different expansions for 32-bit and 64-bit registers. | |
84 | The register sizes are normally inferred from the ISA and ABI, but these | |
85 | flags force a certain group of registers to be treated as 32 bits wide at | |
86 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
87 | and @samp{-mfp32} controls the size of floating-point registers. | |
88 | ||
89 | On some MIPS variants there is a 32-bit mode flag; when this flag is | |
90 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
91 | save the 32-bit registers on a context switch, so it is essential never | |
92 | to use the 64-bit registers. | |
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93 | |
94 | @item -mgp64 | |
95 | Assume that 64-bit general purpose registers are available. This is | |
96 | provided in the interests of symmetry with -gp32. | |
97 | ||
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98 | @item -mips16 |
99 | @itemx -no-mips16 | |
100 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
101 | @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} | |
102 | turns off this option. | |
103 | ||
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104 | @item -mips3d |
105 | @itemx -no-mips3d | |
106 | Generate code for the MIPS-3D Application Specific Extension. | |
107 | This tells the assembler to accept MIPS-3D instructions. | |
108 | @samp{-no-mips3d} turns off this option. | |
109 | ||
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110 | @item -mdmx |
111 | @itemx -no-mdmx | |
112 | Generate code for the MDMX Application Specific Extension. | |
113 | This tells the assembler to accept MDMX instructions. | |
114 | @samp{-no-mdmx} turns off this option. | |
115 | ||
6b76fefe | 116 | @item -mfix7000 |
9ee72ff1 | 117 | @itemx -mno-fix7000 |
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118 | Cause nops to be inserted if the read of the destination register |
119 | of an mfhi or mflo instruction occurs in the following two instructions. | |
120 | ||
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121 | @item -mfix-vr4122-bugs |
122 | @itemx -no-mfix-vr4122-bugs | |
123 | Insert @samp{nop} instructions to avoid errors in certain versions of | |
124 | the vr4122 core. This option is intended to be used on GCC-generated | |
125 | code: it is not designed to catch errors in hand-written assembler code. | |
126 | ||
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127 | @item -m4010 |
128 | @itemx -no-m4010 | |
129 | Generate code for the LSI @sc{r4010} chip. This tells the assembler to | |
130 | accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, | |
131 | etc.), and to not schedule @samp{nop} instructions around accesses to | |
132 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
133 | option. | |
134 | ||
135 | @item -m4650 | |
136 | @itemx -no-m4650 | |
137 | Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept | |
138 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} | |
139 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
140 | @samp{-no-m4650} turns off this option. | |
141 | ||
142 | @itemx -m3900 | |
143 | @itemx -no-m3900 | |
144 | @itemx -m4100 | |
145 | @itemx -no-m4100 | |
146 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
147 | @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions | |
148 | specific to that chip, and to schedule for that chip's hazards. | |
149 | ||
ec68c924 | 150 | @item -march=@var{cpu} |
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151 | Generate code for a particular MIPS cpu. It is exactly equivalent to |
152 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} | |
153 | understood. Valid @var{cpu} value are: | |
154 | ||
155 | @quotation | |
156 | 2000, | |
157 | 3000, | |
158 | 3900, | |
159 | 4000, | |
160 | 4010, | |
161 | 4100, | |
162 | 4111, | |
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163 | vr4120, |
164 | vr4130, | |
165 | vr4181, | |
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166 | 4300, |
167 | 4400, | |
168 | 4600, | |
169 | 4650, | |
170 | 5000, | |
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171 | rm5200, |
172 | rm5230, | |
173 | rm5231, | |
174 | rm5261, | |
175 | rm5721, | |
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176 | vr5400, |
177 | vr5500, | |
252b5132 | 178 | 6000, |
b946ec34 | 179 | rm7000, |
252b5132 | 180 | 8000, |
963ac363 | 181 | rm9000, |
e7af610e | 182 | 10000, |
18ae5d72 | 183 | 12000, |
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184 | mips32-4k, |
185 | sb1 | |
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186 | @end quotation |
187 | ||
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188 | @item -mtune=@var{cpu} |
189 | Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are | |
190 | identical to @samp{-march=@var{cpu}}. | |
191 | ||
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192 | @item -mabi=@var{abi} |
193 | Record which ABI the source code uses. The recognized arguments | |
194 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
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195 | |
196 | @cindex @code{-nocpp} ignored (MIPS) | |
197 | @item -nocpp | |
198 | This option is ignored. It is accepted for command-line compatibility with | |
199 | other assemblers, which use it to turn off C style preprocessing. With | |
200 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
201 | @sc{gnu} assembler itself never runs the C preprocessor. | |
202 | ||
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203 | @item --construct-floats |
204 | @itemx --no-construct-floats | |
205 | @cindex --construct-floats | |
206 | @cindex --no-construct-floats | |
207 | The @code{--no-construct-floats} option disables the construction of | |
208 | double width floating point constants by loading the two halves of the | |
209 | value into the two single width floating point registers that make up | |
210 | the double width register. This feature is useful if the processor | |
211 | support the FR bit in its status register, and this bit is known (by | |
212 | the programmer) to be set. This bit prevents the aliasing of the double | |
213 | width register by the single width registers. | |
214 | ||
63bf5651 | 215 | By default @code{--construct-floats} is selected, allowing construction |
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216 | of these floating point constants. |
217 | ||
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218 | @item --trap |
219 | @itemx --no-break | |
220 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
221 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
222 | @code{@value{AS}} automatically macro expands certain division and | |
223 | multiplication instructions to check for overflow and division by zero. This | |
224 | option causes @code{@value{AS}} to generate code to take a trap exception | |
225 | rather than a break exception when an error is detected. The trap instructions | |
226 | are only supported at Instruction Set Architecture level 2 and higher. | |
227 | ||
228 | @item --break | |
229 | @itemx --no-trap | |
230 | Generate code to take a break exception rather than a trap exception when an | |
231 | error is detected. This is the default. | |
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232 | |
233 | @item -n | |
234 | When this option is used, @code{@value{AS}} will issue a warning every | |
235 | time it generates a nop instruction from a macro. | |
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236 | @end table |
237 | ||
238 | @node MIPS Object | |
239 | @section MIPS ECOFF object code | |
240 | ||
241 | @cindex ECOFF sections | |
242 | @cindex MIPS ECOFF sections | |
243 | Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections | |
244 | besides the usual @code{.text}, @code{.data} and @code{.bss}. The | |
245 | additional sections are @code{.rdata}, used for read-only data, | |
246 | @code{.sdata}, used for small data, and @code{.sbss}, used for small | |
247 | common objects. | |
248 | ||
249 | @cindex small objects, MIPS ECOFF | |
250 | @cindex @code{gp} register, MIPS | |
251 | When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) | |
252 | register to form the address of a ``small object''. Any object in the | |
253 | @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. | |
254 | For external objects, or for objects in the @code{.bss} section, you can use | |
255 | the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via | |
256 | @code{$gp}; the default value is 8, meaning that a reference to any object | |
257 | eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to | |
258 | @code{@value{AS}} prevents it from using the @code{$gp} register on the basis | |
259 | of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} | |
260 | or @code{sbss} in any case). The size of an object in the @code{.bss} section | |
261 | is set by the @code{.comm} or @code{.lcomm} directive that defines it. The | |
262 | size of an external object may be set with the @code{.extern} directive. For | |
263 | example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes | |
264 | in length, whie leaving @code{sym} otherwise undefined. | |
265 | ||
266 | Using small @sc{ecoff} objects requires linker support, and assumes that the | |
267 | @code{$gp} register is correctly initialized (normally done automatically by | |
268 | the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the | |
269 | @code{$gp} register. | |
270 | ||
271 | @node MIPS Stabs | |
272 | @section Directives for debugging information | |
273 | ||
274 | @cindex MIPS debugging directives | |
275 | @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for | |
276 | generating debugging information which are not support by traditional @sc{mips} | |
277 | assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, | |
278 | @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, | |
279 | @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information | |
280 | generated by the three @code{.stab} directives can only be read by @sc{gdb}, | |
281 | not by traditional @sc{mips} debuggers (this enhancement is required to fully | |
282 | support C++ debugging). These directives are primarily used by compilers, not | |
283 | assembly language programmers! | |
284 | ||
285 | @node MIPS ISA | |
286 | @section Directives to override the ISA level | |
287 | ||
288 | @cindex MIPS ISA override | |
289 | @kindex @code{.set mips@var{n}} | |
290 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
291 | the @sc{mips} Instruction Set Architecture level on the fly: @code{.set | |
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292 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, or 64. |
293 | The values other than 0 make the assembler accept instructions | |
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294 | for the corresponding @sc{isa} level, from that point on in the |
295 | assembly. @code{.set mips@var{n}} affects not only which instructions | |
296 | are permitted, but also how certain macros are expanded. @code{.set | |
297 | mips0} restores the @sc{isa} level to its original level: either the | |
298 | level you selected with command line options, or the default for your | |
299 | configuration. You can use this feature to permit specific @sc{r4000} | |
300 | instructions while assembling in 32 bit mode. Use this directive with | |
ec68c924 | 301 | care! |
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302 | |
303 | The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, | |
304 | in which it will assemble instructions for the MIPS 16 processor. Use | |
305 | @samp{.set nomips16} to return to normal 32 bit mode. | |
306 | ||
ec68c924 | 307 | Traditional @sc{mips} assemblers do not support this directive. |
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308 | |
309 | @node MIPS autoextend | |
310 | @section Directives for extending MIPS 16 bit instructions | |
311 | ||
312 | @kindex @code{.set autoextend} | |
313 | @kindex @code{.set noautoextend} | |
314 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
315 | when necessary. The directive @samp{.set noautoextend} will turn this | |
316 | off. When @samp{.set noautoextend} is in effect, any 32 bit instruction | |
317 | must be explicitly extended with the @samp{.e} modifier (e.g., | |
318 | @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used | |
319 | to once again automatically extend instructions when necessary. | |
320 | ||
321 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
322 | @sc{mips} assemblers do not support this directive. | |
323 | ||
324 | @node MIPS insn | |
325 | @section Directive to mark data as an instruction | |
326 | ||
327 | @kindex @code{.insn} | |
328 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
329 | data is actually instructions. This makes a difference in MIPS 16 mode: | |
330 | when loading the address of a label which precedes instructions, | |
331 | @code{@value{AS}} automatically adds 1 to the value, so that jumping to | |
332 | the loaded address will do the right thing. | |
333 | ||
334 | @node MIPS option stack | |
335 | @section Directives to save and restore options | |
336 | ||
337 | @cindex MIPS option stack | |
338 | @kindex @code{.set push} | |
339 | @kindex @code{.set pop} | |
340 | The directives @code{.set push} and @code{.set pop} may be used to save | |
341 | and restore the current settings for all the options which are | |
342 | controlled by @code{.set}. The @code{.set push} directive saves the | |
343 | current settings on a stack. The @code{.set pop} directive pops the | |
344 | stack and restores the settings. | |
345 | ||
346 | These directives can be useful inside an macro which must change an | |
347 | option such as the ISA level or instruction reordering but does not want | |
348 | to change the state of the code which invoked the macro. | |
349 | ||
350 | Traditional @sc{mips} assemblers do not support these directives. | |
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351 | |
352 | @node MIPS ASE instruction generation overrides | |
353 | @section Directives to control generation of MIPS ASE instructions | |
354 | ||
355 | @cindex MIPS MIPS-3D instruction generation override | |
356 | @kindex @code{.set mips3d} | |
357 | @kindex @code{.set nomips3d} | |
358 | The directive @code{.set mips3d} makes the assembler accept instructions | |
359 | from the MIPS-3D Application Specific Extension from that point on | |
360 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
361 | instructions from being accepted. | |
362 | ||
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363 | @cindex MIPS MDMX instruction generation override |
364 | @kindex @code{.set mdmx} | |
365 | @kindex @code{.set nomdmx} | |
366 | The directive @code{.set mdmx} makes the assembler accept instructions | |
367 | from the MDMX Application Specific Extension from that point on | |
368 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
369 | instructions from being accepted. | |
370 | ||
1f25f5d3 | 371 | Traditional @sc{mips} assemblers do not support these directives. |