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2571583a | 1 | @c Copyright (C) 2001-2017 Free Software Foundation, Inc. |
418c1742 MG |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
b8b738ac | 4 | @c man end |
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5 | @ifset GENERIC |
6 | @page | |
7 | @node PPC-Dependent | |
8 | @chapter PowerPC Dependent Features | |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter PowerPC Dependent Features | |
13 | @end ifclear | |
14 | ||
15 | @cindex PowerPC support | |
16 | @menu | |
17 | * PowerPC-Opts:: Options | |
f22b3caf | 18 | * PowerPC-Pseudo:: PowerPC Assembler Directives |
7c31ae13 | 19 | * PowerPC-Syntax:: PowerPC Syntax |
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20 | @end menu |
21 | ||
22 | @node PowerPC-Opts | |
23 | @section Options | |
24 | ||
25 | @cindex options for PowerPC | |
26 | @cindex PowerPC options | |
27 | @cindex architectures, PowerPC | |
28 | @cindex PowerPC architectures | |
29 | The PowerPC chip family includes several successive levels, using the same | |
30 | core instruction set, but including a few additional instructions at | |
31 | each level. There are exceptions to this however. For details on what | |
32 | instructions each variant supports, please see the chip's architecture | |
33 | reference manual. | |
34 | ||
35 | The following table lists all available PowerPC options. | |
36 | ||
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37 | @c man begin OPTIONS |
38 | @table @gcctabopt | |
39 | @item -a32 | |
40 | Generate ELF32 or XCOFF32. | |
41 | ||
42 | @item -a64 | |
43 | Generate ELF64 or XCOFF64. | |
44 | ||
45 | @item -K PIC | |
46 | Set EF_PPC_RELOCATABLE_LIB in ELF flags. | |
47 | ||
418c1742 | 48 | @item -mpwrx | -mpwr2 |
23e1d84c | 49 | Generate code for POWER/2 (RIOS2). |
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50 | |
51 | @item -mpwr | |
23e1d84c | 52 | Generate code for POWER (RIOS1) |
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53 | |
54 | @item -m601 | |
23e1d84c | 55 | Generate code for PowerPC 601. |
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56 | |
57 | @item -mppc, -mppc32, -m603, -m604 | |
23e1d84c | 58 | Generate code for PowerPC 603/604. |
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59 | |
60 | @item -m403, -m405 | |
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61 | Generate code for PowerPC 403/405. |
62 | ||
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63 | @item -m440 |
64 | Generate code for PowerPC 440. BookE and some 405 instructions. | |
65 | ||
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66 | @item -m464 |
67 | Generate code for PowerPC 464. | |
68 | ||
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69 | @item -m476 |
70 | Generate code for PowerPC 476. | |
71 | ||
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72 | @item -m7400, -m7410, -m7450, -m7455 |
73 | Generate code for PowerPC 7400/7410/7450/7455. | |
418c1742 | 74 | |
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75 | @item -m750cl |
76 | Generate code for PowerPC 750CL. | |
77 | ||
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78 | @item -m821, -m850, -m860 |
79 | Generate code for PowerPC 821/850/860. | |
80 | ||
418c1742 | 81 | @item -mppc64, -m620 |
23e1d84c | 82 | Generate code for PowerPC 620/625/630. |
418c1742 | 83 | |
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84 | @item -me500, -me500x2 |
85 | Generate code for Motorola e500 core complex. | |
86 | ||
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87 | @item -me500mc |
88 | Generate code for Freescale e500mc core complex. | |
89 | ||
90 | @item -me500mc64 | |
91 | Generate code for Freescale e500mc64 core complex. | |
92 | ||
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93 | @item -me5500 |
94 | Generate code for Freescale e5500 core complex. | |
95 | ||
96 | @item -me6500 | |
97 | Generate code for Freescale e6500 core complex. | |
98 | ||
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99 | @item -mspe |
100 | Generate code for Motorola SPE instructions. | |
101 | ||
74081948 AF |
102 | @item -mspe2 |
103 | Generate code for Freescale SPE2 instructions. | |
104 | ||
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105 | @item -mtitan |
106 | Generate code for AppliedMicro Titan core complex. | |
107 | ||
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108 | @item -mppc64bridge |
109 | Generate code for PowerPC 64, including bridge insns. | |
110 | ||
2f3bb96a | 111 | @item -mbooke |
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112 | Generate code for 32-bit BookE. |
113 | ||
634b50f2 | 114 | @item -ma2 |
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115 | Generate code for A2 architecture. |
116 | ||
36ae0db3 DJ |
117 | @item -me300 |
118 | Generate code for PowerPC e300 family. | |
119 | ||
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120 | @item -maltivec |
121 | Generate code for processors with AltiVec instructions. | |
122 | ||
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123 | @item -mvle |
124 | Generate code for Freescale PowerPC VLE instructions. | |
125 | ||
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126 | @item -mvsx |
127 | Generate code for processors with Vector-Scalar (VSX) instructions. | |
128 | ||
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129 | @item -mhtm |
130 | Generate code for processors with Hardware Transactional Memory instructions. | |
131 | ||
b8b738ac | 132 | @item -mpower4, -mpwr4 |
23e1d84c | 133 | Generate code for Power4 architecture. |
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b8b738ac | 135 | @item -mpower5, -mpwr5, -mpwr5x |
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136 | Generate code for Power5 architecture. |
137 | ||
b8b738ac | 138 | @item -mpower6, -mpwr6 |
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139 | Generate code for Power6 architecture. |
140 | ||
b8b738ac | 141 | @item -mpower7, -mpwr7 |
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142 | Generate code for Power7 architecture. |
143 | ||
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144 | @item -mpower8, -mpwr8 |
145 | Generate code for Power8 architecture. | |
146 | ||
a680de9a PB |
147 | @item -mpower9, -mpwr9 |
148 | Generate code for Power9 architecture. | |
149 | ||
5817ffd1 | 150 | @item -mcell |
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151 | @item -mcell |
152 | Generate code for Cell Broadband Engine architecture. | |
153 | ||
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154 | @item -mcom |
155 | Generate code Power/PowerPC common instructions. | |
156 | ||
157 | @item -many | |
158 | Generate code for any architecture (PWR/PWRX/PPC). | |
159 | ||
160 | @item -mregnames | |
161 | Allow symbolic names for registers. | |
162 | ||
163 | @item -mno-regnames | |
164 | Do not allow symbolic names for registers. | |
165 | ||
166 | @item -mrelocatable | |
b45619c0 | 167 | Support for GCC's -mrelocatable option. |
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168 | |
169 | @item -mrelocatable-lib | |
b45619c0 | 170 | Support for GCC's -mrelocatable-lib option. |
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171 | |
172 | @item -memb | |
173 | Set PPC_EMB bit in ELF flags. | |
174 | ||
b8b738ac | 175 | @item -mlittle, -mlittle-endian, -le |
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176 | Generate code for a little endian machine. |
177 | ||
b8b738ac | 178 | @item -mbig, -mbig-endian, -be |
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179 | Generate code for a big endian machine. |
180 | ||
181 | @item -msolaris | |
182 | Generate code for Solaris. | |
183 | ||
184 | @item -mno-solaris | |
185 | Do not generate code for Solaris. | |
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186 | |
187 | @item -nops=@var{count} | |
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188 | If an alignment directive inserts more than @var{count} nops, put a |
189 | branch at the beginning to skip execution of the nops. | |
418c1742 | 190 | @end table |
b8b738ac | 191 | @c man end |
f22b3caf AM |
192 | |
193 | ||
194 | @node PowerPC-Pseudo | |
195 | @section PowerPC Assembler Directives | |
196 | ||
197 | @cindex directives for PowerPC | |
198 | @cindex PowerPC directives | |
199 | A number of assembler directives are available for PowerPC. The | |
200 | following table is far from complete. | |
201 | ||
202 | @table @code | |
203 | @item .machine "string" | |
204 | This directive allows you to change the machine for which code is | |
205 | generated. @code{"string"} may be any of the -m cpu selection options | |
206 | (without the -m) enclosed in double quotes, @code{"push"}, or | |
207 | @code{"pop"}. @code{.machine "push"} saves the currently selected | |
208 | cpu, which may be restored with @code{.machine "pop"}. | |
209 | @end table | |
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210 | |
211 | @node PowerPC-Syntax | |
212 | @section PowerPC Syntax | |
213 | @menu | |
214 | * PowerPC-Chars:: Special Characters | |
215 | @end menu | |
216 | ||
217 | @node PowerPC-Chars | |
218 | @subsection Special Characters | |
219 | ||
220 | @cindex line comment character, PowerPC | |
221 | @cindex PowerPC line comment character | |
222 | The presence of a @samp{#} on a line indicates the start of a comment | |
223 | that extends to the end of the current line. | |
224 | ||
225 | If a @samp{#} appears as the first character of a line then the whole | |
226 | line is treated as a comment, but in this case the line could also be | |
227 | a logical line number directive (@pxref{Comments}) or a preprocessor | |
228 | control command (@pxref{Preprocessing}). | |
229 | ||
230 | If the assembler has been configured for the ppc-*-solaris* target | |
231 | then the @samp{!} character also acts as a line comment character. | |
232 | This can be disabled via the @option{-mno-solaris} command line | |
233 | option. | |
234 | ||
235 | @cindex line separator, PowerPC | |
236 | @cindex statement separator, PowerPC | |
237 | @cindex PowerPC line separator | |
238 | The @samp{;} character can be used to separate statements on the same | |
239 | line. |