[deliverable/binutils-gdb.git] / gas / doc / c-sh.texi

@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004,
@c 2005, 2008, 2010, 2011  Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH-Dependent
@chapter Renesas / SuperH SH Dependent Features

@cindex SH support
@menu
* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes
@end menu

@node SH Options
@section Options

@cindex SH options
@cindex options, SH
@code{@value{AS}} has following command-line options for the Renesas
(formerly Hitachi) / SuperH SH family.

@table @code
@kindex --little
@kindex --big
@kindex --relax
@kindex --small
@kindex --dsp
@kindex --renesas
@kindex --allow-reg-prefix

@item --little
Generate little endian code.

@item --big
Generate big endian code.

@item --relax
Alter jump instructions for long displacements.

@item --small
Align sections to 4 byte boundaries, not 16.

@item --dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.

@item --renesas
Disable optimization with section symbol for compatibility with
Renesas assembler.

@item --allow-reg-prefix
Allow '$' as a register name prefix.

@kindex --fdpic
@item --fdpic
Generate an FDPIC object file.

@item --isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
@item --isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item --isa=fp
Enable sh2e, sh3e, sh4, and sh4a insn sets.
@item --isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.

@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.

@end table

@node SH Syntax
@section Syntax

@menu
* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes
@end menu

@node SH-Chars
@subsection Special Characters

@cindex line comment character, SH
@cindex SH line comment character
@samp{!} is the line comment character.

@cindex line separator, SH
@cindex statement separator, SH
@cindex SH line separator
You can use @samp{;} instead of a newline to separate statements.

If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).

@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.

@node SH-Regs
@subsection Register Names

@cindex SH registers
@cindex registers, SH
You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
and @samp{r15} to refer to the SH registers.

The SH also has these control registers:

@table @code
@item pr
procedure register (holds return address)

@item pc
program counter

@item mach
@itemx macl
high and low multiply accumulator registers

@item sr
status register

@item gbr
global base register

@item vbr
vector base register (for interrupt vectors)
@end table

@node SH-Addressing
@subsection Addressing Modes

@cindex addressing modes, SH
@cindex SH addressing modes
@code{@value{AS}} understands the following addressing modes for the SH.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.

@table @code
@item R@var{n}
Register direct

@item @@R@var{n}
Register indirect

@item @@-R@var{n}
Register indirect with pre-decrement

@item @@R@var{n}+
Register indirect with post-increment

@item @@(@var{disp}, R@var{n})
Register indirect with displacement

@item @@(R0, R@var{n})
Register indexed

@item @@(@var{disp}, GBR)
@code{GBR} offset

@item @@(R0, GBR)
GBR indexed

@item @var{addr}
@itemx @@(@var{disp}, PC)
PC relative address (for branch or for addressing memory).  The
@code{@value{AS}} implementation allows you to use the simpler form
@var{addr} anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.

@item #@var{imm}
Immediate data
@end table

@node SH Floating Point
@section Floating Point

@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use @code{.float} directive to generate @sc{ieee} 
floating-point numbers. 

SH2E and SH3E support single-precision floating point calculations as 
well as entirely PCAPI compatible emulation of double-precision 
floating point calculations. SH2E and SH3E instructions are a subset of
the floating point calculations conforming to the IEEE754 standard.

In addition to single-precision and double-precision floating-point 
operation capability, the on-chip FPU of SH4 has a 128-bit graphic 
engine that enables 32-bit floating-point data to be processed 128 
bits at a time. It also supports 4 * 4 array operations and inner 
product operations. Also, a superscalar architecture is employed that 
enables simultaneous execution of two instructions (including FPU 
instructions), providing performance of up to twice that of 
conventional architectures at the same frequency.

@node SH Directives
@section SH Machine Directives

@cindex SH machine directives
@cindex machine directives, SH
@cindex @code{uaword} directive, SH
@cindex @code{ualong} directive, SH

@table @code
@item uaword
@itemx ualong
@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
@code{.long} directive is used.  You may use @code{.uaword} or
@code{.ualong} to indicate that the value is intentionally misaligned.
@end table

@node SH Opcodes
@section Opcodes

@cindex SH opcode summary
@cindex opcode summary, SH
@cindex mnemonics, SH
@cindex instruction summary, SH
For detailed information on the SH machine instruction set, see
@cite{SH-Microcomputer User's Manual} (Renesas) or
@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).

@code{@value{AS}} implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because @code{@value{AS}} supports a simpler form of PC-relative
addressing, you may simply write (for example)

@example
mov.l  bar,r0
@end example

@noindent
where other assemblers might require an explicit displacement to
@code{bar} from the program counter:

@example
mov.l  @@(@var{disp}, PC)
@end example

@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook.  See comments below "@set SMALL" near top of this file.

Here is a summary of SH opcodes:

@page
@smallexample
@i{Legend:}
Rn        @r{a numbered register}
Rm        @r{another numbered register}
#imm      @r{immediate data}
disp      @r{displacement}
disp8     @r{8-bit displacement}
disp12    @r{12-bit displacement}

add #imm,Rn                    lds.l @@Rn+,PR              
add Rm,Rn                      mac.w @@Rm+,@@Rn+           
addc Rm,Rn                     mov #imm,Rn                 
addv Rm,Rn                     mov Rm,Rn                   
and #imm,R0                    mov.b Rm,@@(R0,Rn)          
and Rm,Rn                      mov.b Rm,@@-Rn              
and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn               
bf disp8                       mov.b @@(disp,Rm),R0        
bra disp12                     mov.b @@(disp,GBR),R0       
bsr disp12                     mov.b @@(R0,Rm),Rn          
bt disp8                       mov.b @@Rm+,Rn              
clrmac                         mov.b @@Rm,Rn               
clrt                           mov.b R0,@@(disp,Rm)        
cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)       
cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)        
cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)          
cmp/gt Rm,Rn                   mov.l Rm,@@-Rn              
cmp/hi Rm,Rn                   mov.l Rm,@@Rn               
cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm        
cmp/pl Rn                      mov.l @@(disp,GBR),R0       
cmp/pz Rn                      mov.l @@(disp,PC),Rn        
cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn          
div0s Rm,Rn                    mov.l @@Rm+,Rn              
div0u                          mov.l @@Rm,Rn               
div1 Rm,Rn                     mov.l R0,@@(disp,GBR)       
exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)          
exts.w Rm,Rn                   mov.w Rm,@@-Rn              
extu.b Rm,Rn                   mov.w Rm,@@Rn               
extu.w Rm,Rn                   mov.w @@(disp,Rm),R0        
jmp @@Rn                        mov.w @@(disp,GBR),R0       
jsr @@Rn                        mov.w @@(disp,PC),Rn        
ldc Rn,GBR                     mov.w @@(R0,Rm),Rn          
ldc Rn,SR                      mov.w @@Rm+,Rn              
ldc Rn,VBR                     mov.w @@Rm,Rn               
ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)        
ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)       
ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0         
lds Rn,MACH                    movt Rn                     
lds Rn,MACL                    muls Rm,Rn                  
lds Rn,PR                      mulu Rm,Rn                  
lds.l @@Rn+,MACH                neg Rm,Rn                   
lds.l @@Rn+,MACL                negc Rm,Rn                  
@page
nop                            stc VBR,Rn                
not Rm,Rn                      stc.l GBR,@@-Rn           
or #imm,R0                     stc.l SR,@@-Rn            
or Rm,Rn                       stc.l VBR,@@-Rn           
or.b #imm,@@(R0,GBR)            sts MACH,Rn               
rotcl Rn                       sts MACL,Rn               
rotcr Rn                       sts PR,Rn                 
rotl Rn                        sts.l MACH,@@-Rn          
rotr Rn                        sts.l MACL,@@-Rn          
rte                            sts.l PR,@@-Rn            
rts                            sub Rm,Rn                 
sett                           subc Rm,Rn                
shal Rn                        subv Rm,Rn                
shar Rn                        swap.b Rm,Rn              
shll Rn                        swap.w Rm,Rn              
shll16 Rn                      tas.b @@Rn                
shll2 Rn                       trapa #imm                
shll8 Rn                       tst #imm,R0               
shlr Rn                        tst Rm,Rn                 
shlr16 Rn                      tst.b #imm,@@(R0,GBR)     
shlr2 Rn                       xor #imm,R0               
shlr8 Rn                       xor Rm,Rn                 
sleep                          xor.b #imm,@@(R0,GBR)     
stc GBR,Rn                     xtrct Rm,Rn               
stc SR,Rn
@end smallexample
@end ifset

@ifset Renesas-all
@ifclear GENERIC
@raisesections
@end ifclear
@end ifset
Commit	Line	Data
8e45593f	1	@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004,
7c31ae13	2	@c 2005, 2008, 2010, 2011 Free Software Foundation, Inc.
252b5132 RH	3	@c This is part of the GAS manual.
	4	@c For copying conditions, see the file as.texinfo.
	5	@page
	6	@node SH-Dependent
ef230218	7	@chapter Renesas / SuperH SH Dependent Features
252b5132 RH	8
	9	@cindex SH support
	10	@menu
	11	* SH Options:: Options
	12	* SH Syntax:: Syntax
	13	* SH Floating Point:: Floating Point
	14	* SH Directives:: SH Machine Directives
	15	* SH Opcodes:: Opcodes
	16	@end menu
	17
	18	@node SH Options
	19	@section Options
	20
7649aa50 NC	21	@cindex SH options
7649aa50 NC	22	@cindex options, SH
c2dcd04e	23	@code{@value{AS}} has following command-line options for the Renesas
ef230218	24	(formerly Hitachi) / SuperH SH family.
252b5132	25
7649aa50	26	@table @code
37dedf66 NC	27	@kindex --little
	28	@kindex --big
	29	@kindex --relax
	30	@kindex --small
	31	@kindex --dsp
	32	@kindex --renesas
	33	@kindex --allow-reg-prefix
	34
	35	@item --little
7649aa50 NC	36	Generate little endian code.
7649aa50 NC	37
37dedf66	38	@item --big
7649aa50 NC	39	Generate big endian code.
7649aa50 NC	40
37dedf66	41	@item --relax
7649aa50 NC	42	Alter jump instructions for long displacements.
7649aa50 NC	43
37dedf66	44	@item --small
7649aa50 NC	45	Align sections to 4 byte boundaries, not 16.
7649aa50 NC	46
37dedf66	47	@item --dsp
7649aa50 NC	48	Enable sh-dsp insns, and disable sh3e / sh4 insns.
7649aa50 NC	49
37dedf66	50	@item --renesas
f55629b8 KK	51	Disable optimization with section symbol for compatibility with
	52	Renesas assembler.
	53
37dedf66 NC	54	@item --allow-reg-prefix
	55	Allow '$' as a register name prefix.
	56
8e45593f NC	57	@kindex --fdpic
	58	@item --fdpic
	59	Generate an FDPIC object file.
	60
37dedf66	61	@item --isa=sh4 \| sh4a
88da98f3	62	Specify the sh4 or sh4a instruction set.
37dedf66	63	@item --isa=dsp
88da98f3	64	Enable sh-dsp insns, and disable sh3e / sh4 insns.
37dedf66	65	@item --isa=fp
88da98f3	66	Enable sh2e, sh3e, sh4, and sh4a insn sets.
37dedf66	67	@item --isa=all
88da98f3 MS	68	Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
88da98f3 MS	69
6fd4f6cc DD	70	@item -h-tick-hex
	71	Support H'00 style hex constants in addition to 0x00 style.
	72
7649aa50 NC	73	@end table
7649aa50 NC	74
252b5132 RH	75	@node SH Syntax
	76	@section Syntax
	77
	78	@menu
	79	* SH-Chars:: Special Characters
	80	* SH-Regs:: Register Names
	81	* SH-Addressing:: Addressing Modes
	82	@end menu
	83
	84	@node SH-Chars
	85	@subsection Special Characters
	86
	87	@cindex line comment character, SH
	88	@cindex SH line comment character
	89	@samp{!} is the line comment character.
	90
	91	@cindex line separator, SH
	92	@cindex statement separator, SH
	93	@cindex SH line separator
	94	You can use @samp{;} instead of a newline to separate statements.
	95
7c31ae13 NC	96	If a @samp{#} appears as the first character of a line then the whole
	97	line is treated as a comment, but in this case the line could also be
	98	a logical line number directive (@pxref{Comments}) or a preprocessor
	99	control command (@pxref{Preprocessing}).
	100
252b5132 RH	101	@cindex symbol names, @samp{$} in
	102	@cindex @code{$} in symbol names
	103	Since @samp{$} has no special meaning, you may use it in symbol names.
	104
	105	@node SH-Regs
	106	@subsection Register Names
	107
	108	@cindex SH registers
	109	@cindex registers, SH
	110	You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
	111	@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
	112	@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
	113	and @samp{r15} to refer to the SH registers.
	114
	115	The SH also has these control registers:
	116
	117	@table @code
	118	@item pr
	119	procedure register (holds return address)
	120
	121	@item pc
	122	program counter
	123
	124	@item mach
	125	@itemx macl
	126	high and low multiply accumulator registers
	127
	128	@item sr
	129	status register
	130
	131	@item gbr
	132	global base register
	133
	134	@item vbr
	135	vector base register (for interrupt vectors)
	136	@end table
	137
	138	@node SH-Addressing
	139	@subsection Addressing Modes
	140
	141	@cindex addressing modes, SH
	142	@cindex SH addressing modes
	143	@code{@value{AS}} understands the following addressing modes for the SH.
	144	@code{R@var{n}} in the following refers to any of the numbered
	145	registers, but @emph{not} the control registers.
	146
	147	@table @code
	148	@item R@var{n}
	149	Register direct
	150
	151	@item @@R@var{n}
	152	Register indirect
	153
	154	@item @@-R@var{n}
	155	Register indirect with pre-decrement
	156
	157	@item @@R@var{n}+
	158	Register indirect with post-increment
	159
	160	@item @@(@var{disp}, R@var{n})
	161	Register indirect with displacement
	162
	163	@item @@(R0, R@var{n})
	164	Register indexed
165
166	@item @@(@var{disp}, GBR)
167	@code{GBR} offset
168
169	@item @@(R0, GBR)
170	GBR indexed
171
172	@item @var{addr}
173	@itemx @@(@var{disp}, PC)
174	PC relative address (for branch or for addressing memory). The
175	@code{@value{AS}} implementation allows you to use the simpler form
176	@var{addr} anywhere a PC relative address is called for; the alternate
177	form is supported for compatibility with other assemblers.
178
179	@item #@var{imm}
180	Immediate data
181	@end table
182
183	@node SH Floating Point
184	@section Floating Point
185
186	@cindex floating point, SH (@sc{ieee})
187	@cindex SH floating point (@sc{ieee})
303e7b79 NC	188	SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
	189	SH groups can use @code{.float} directive to generate @sc{ieee}
	190	floating-point numbers.
	191
	192	SH2E and SH3E support single-precision floating point calculations as
	193	well as entirely PCAPI compatible emulation of double-precision
	194	floating point calculations. SH2E and SH3E instructions are a subset of
	195	the floating point calculations conforming to the IEEE754 standard.
	196
	197	In addition to single-precision and double-precision floating-point
	198	operation capability, the on-chip FPU of SH4 has a 128-bit graphic
	199	engine that enables 32-bit floating-point data to be processed 128
	200	bits at a time. It also supports 4 * 4 array operations and inner
	201	product operations. Also, a superscalar architecture is employed that
	202	enables simultaneous execution of two instructions (including FPU
	203	instructions), providing performance of up to twice that of
	204	conventional architectures at the same frequency.
252b5132 RH	205
	206	@node SH Directives
	207	@section SH Machine Directives
	208
	209	@cindex SH machine directives
	210	@cindex machine directives, SH
	211	@cindex @code{uaword} directive, SH
	212	@cindex @code{ualong} directive, SH
	213
	214	@table @code
	215	@item uaword
	216	@itemx ualong
	217	@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
	218	@code{.long} directive is used. You may use @code{.uaword} or
	219	@code{.ualong} to indicate that the value is intentionally misaligned.
	220	@end table
	221
	222	@node SH Opcodes
	223	@section Opcodes
	224
	225	@cindex SH opcode summary
	226	@cindex opcode summary, SH
	227	@cindex mnemonics, SH
	228	@cindex instruction summary, SH
	229	For detailed information on the SH machine instruction set, see
ef230218 JR	230	@cite{SH-Microcomputer User's Manual} (Renesas) or
	231	@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
	232	@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
252b5132 RH	233
	234	@code{@value{AS}} implements all the standard SH opcodes. No additional
	235	pseudo-instructions are needed on this family. Note, however, that
	236	because @code{@value{AS}} supports a simpler form of PC-relative
	237	addressing, you may simply write (for example)
	238
	239	@example
	240	mov.l bar,r0
	241	@end example
	242
	243	@noindent
	244	where other assemblers might require an explicit displacement to
	245	@code{bar} from the program counter:
	246
	247	@example
	248	mov.l @@(@var{disp}, PC)
	249	@end example
	250
	251	@ifset SMALL
	252	@c this table, due to the multi-col faking and hardcoded order, looks silly
	253	@c except in smallbook. See comments below "@set SMALL" near top of this file.
	254
	255	Here is a summary of SH opcodes:
	256
	257	@page
	258	@smallexample
	259	@i{Legend:}
	260	Rn @r{a numbered register}
	261	Rm @r{another numbered register}
	262	#imm @r{immediate data}
	263	disp @r{displacement}
	264	disp8 @r{8-bit displacement}
	265	disp12 @r{12-bit displacement}
	266
	267	add #imm,Rn lds.l @@Rn+,PR
	268	add Rm,Rn mac.w @@Rm+,@@Rn+
	269	addc Rm,Rn mov #imm,Rn
	270	addv Rm,Rn mov Rm,Rn
	271	and #imm,R0 mov.b Rm,@@(R0,Rn)
	272	and Rm,Rn mov.b Rm,@@-Rn
	273	and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
	274	bf disp8 mov.b @@(disp,Rm),R0
	275	bra disp12 mov.b @@(disp,GBR),R0
	276	bsr disp12 mov.b @@(R0,Rm),Rn
	277	bt disp8 mov.b @@Rm+,Rn
	278	clrmac mov.b @@Rm,Rn
	279	clrt mov.b R0,@@(disp,Rm)
	280	cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
	281	cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
	282	cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
	283	cmp/gt Rm,Rn mov.l Rm,@@-Rn
	284	cmp/hi Rm,Rn mov.l Rm,@@Rn
	285	cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
	286	cmp/pl Rn mov.l @@(disp,GBR),R0
	287	cmp/pz Rn mov.l @@(disp,PC),Rn
	288	cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
	289	div0s Rm,Rn mov.l @@Rm+,Rn
	290	div0u mov.l @@Rm,Rn
	291	div1 Rm,Rn mov.l R0,@@(disp,GBR)
	292	exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
	293	exts.w Rm,Rn mov.w Rm,@@-Rn
	294	extu.b Rm,Rn mov.w Rm,@@Rn
	295	extu.w Rm,Rn mov.w @@(disp,Rm),R0
	296	jmp @@Rn mov.w @@(disp,GBR),R0
297	jsr @@Rn mov.w @@(disp,PC),Rn
298	ldc Rn,GBR mov.w @@(R0,Rm),Rn
299	ldc Rn,SR mov.w @@Rm+,Rn
300	ldc Rn,VBR mov.w @@Rm,Rn
301	ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
302	ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
303	ldc.l @@Rn+,VBR mova @@(disp,PC),R0
304	lds Rn,MACH movt Rn
305	lds Rn,MACL muls Rm,Rn
306	lds Rn,PR mulu Rm,Rn
307	lds.l @@Rn+,MACH neg Rm,Rn
308	lds.l @@Rn+,MACL negc Rm,Rn
309	@page
310	nop stc VBR,Rn
311	not Rm,Rn stc.l GBR,@@-Rn
312	or #imm,R0 stc.l SR,@@-Rn
313	or Rm,Rn stc.l VBR,@@-Rn
314	or.b #imm,@@(R0,GBR) sts MACH,Rn
315	rotcl Rn sts MACL,Rn
316	rotcr Rn sts PR,Rn
317	rotl Rn sts.l MACH,@@-Rn
318	rotr Rn sts.l MACL,@@-Rn
319	rte sts.l PR,@@-Rn
320	rts sub Rm,Rn
321	sett subc Rm,Rn
322	shal Rn subv Rm,Rn
323	shar Rn swap.b Rm,Rn
324	shll Rn swap.w Rm,Rn
325	shll16 Rn tas.b @@Rn
326	shll2 Rn trapa #imm
327	shll8 Rn tst #imm,R0
328	shlr Rn tst Rm,Rn
329	shlr16 Rn tst.b #imm,@@(R0,GBR)
330	shlr2 Rn xor #imm,R0
331	shlr8 Rn xor Rm,Rn
332	sleep xor.b #imm,@@(R0,GBR)
333	stc GBR,Rn xtrct Rm,Rn
334	stc SR,Rn
335	@end smallexample
336	@end ifset
337
c2dcd04e	338	@ifset Renesas-all
252b5132 RH	339	@ifclear GENERIC
	340	@raisesections
	341	@end ifclear
	342	@end ifset
	343