Commit | Line | Data |
---|---|---|
2da5c037 | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004 |
f7e42eb4 | 2 | @c Free Software Foundation, Inc. |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @page | |
6 | @node SH-Dependent | |
ef230218 | 7 | @chapter Renesas / SuperH SH Dependent Features |
252b5132 RH |
8 | |
9 | @cindex SH support | |
10 | @menu | |
11 | * SH Options:: Options | |
12 | * SH Syntax:: Syntax | |
13 | * SH Floating Point:: Floating Point | |
14 | * SH Directives:: SH Machine Directives | |
15 | * SH Opcodes:: Opcodes | |
16 | @end menu | |
17 | ||
18 | @node SH Options | |
19 | @section Options | |
20 | ||
7649aa50 NC |
21 | @cindex SH options |
22 | @cindex options, SH | |
c2dcd04e | 23 | @code{@value{AS}} has following command-line options for the Renesas |
ef230218 | 24 | (formerly Hitachi) / SuperH SH family. |
252b5132 | 25 | |
7649aa50 NC |
26 | @table @code |
27 | @kindex -little | |
28 | @kindex -big | |
29 | @kindex -relax | |
30 | @kindex -small | |
31 | @kindex -dsp | |
f55629b8 | 32 | @kindex -renesas |
7649aa50 NC |
33 | |
34 | @item -little | |
35 | Generate little endian code. | |
36 | ||
37 | @item -big | |
38 | Generate big endian code. | |
39 | ||
40 | @item -relax | |
41 | Alter jump instructions for long displacements. | |
42 | ||
43 | @item -small | |
44 | Align sections to 4 byte boundaries, not 16. | |
45 | ||
46 | @item -dsp | |
47 | Enable sh-dsp insns, and disable sh3e / sh4 insns. | |
48 | ||
f55629b8 KK |
49 | @item -renesas |
50 | Disable optimization with section symbol for compatibility with | |
51 | Renesas assembler. | |
52 | ||
88da98f3 MS |
53 | @item -isa=sh4 | sh4a |
54 | Specify the sh4 or sh4a instruction set. | |
55 | @item -isa=dsp | |
56 | Enable sh-dsp insns, and disable sh3e / sh4 insns. | |
57 | @item -isa=fp | |
58 | Enable sh2e, sh3e, sh4, and sh4a insn sets. | |
59 | @item -isa=all | |
60 | Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. | |
61 | ||
7649aa50 NC |
62 | @end table |
63 | ||
252b5132 RH |
64 | @node SH Syntax |
65 | @section Syntax | |
66 | ||
67 | @menu | |
68 | * SH-Chars:: Special Characters | |
69 | * SH-Regs:: Register Names | |
70 | * SH-Addressing:: Addressing Modes | |
71 | @end menu | |
72 | ||
73 | @node SH-Chars | |
74 | @subsection Special Characters | |
75 | ||
76 | @cindex line comment character, SH | |
77 | @cindex SH line comment character | |
78 | @samp{!} is the line comment character. | |
79 | ||
80 | @cindex line separator, SH | |
81 | @cindex statement separator, SH | |
82 | @cindex SH line separator | |
83 | You can use @samp{;} instead of a newline to separate statements. | |
84 | ||
85 | @cindex symbol names, @samp{$} in | |
86 | @cindex @code{$} in symbol names | |
87 | Since @samp{$} has no special meaning, you may use it in symbol names. | |
88 | ||
89 | @node SH-Regs | |
90 | @subsection Register Names | |
91 | ||
92 | @cindex SH registers | |
93 | @cindex registers, SH | |
94 | You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, | |
95 | @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, | |
96 | @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, | |
97 | and @samp{r15} to refer to the SH registers. | |
98 | ||
99 | The SH also has these control registers: | |
100 | ||
101 | @table @code | |
102 | @item pr | |
103 | procedure register (holds return address) | |
104 | ||
105 | @item pc | |
106 | program counter | |
107 | ||
108 | @item mach | |
109 | @itemx macl | |
110 | high and low multiply accumulator registers | |
111 | ||
112 | @item sr | |
113 | status register | |
114 | ||
115 | @item gbr | |
116 | global base register | |
117 | ||
118 | @item vbr | |
119 | vector base register (for interrupt vectors) | |
120 | @end table | |
121 | ||
122 | @node SH-Addressing | |
123 | @subsection Addressing Modes | |
124 | ||
125 | @cindex addressing modes, SH | |
126 | @cindex SH addressing modes | |
127 | @code{@value{AS}} understands the following addressing modes for the SH. | |
128 | @code{R@var{n}} in the following refers to any of the numbered | |
129 | registers, but @emph{not} the control registers. | |
130 | ||
131 | @table @code | |
132 | @item R@var{n} | |
133 | Register direct | |
134 | ||
135 | @item @@R@var{n} | |
136 | Register indirect | |
137 | ||
138 | @item @@-R@var{n} | |
139 | Register indirect with pre-decrement | |
140 | ||
141 | @item @@R@var{n}+ | |
142 | Register indirect with post-increment | |
143 | ||
144 | @item @@(@var{disp}, R@var{n}) | |
145 | Register indirect with displacement | |
146 | ||
147 | @item @@(R0, R@var{n}) | |
148 | Register indexed | |
149 | ||
150 | @item @@(@var{disp}, GBR) | |
151 | @code{GBR} offset | |
152 | ||
153 | @item @@(R0, GBR) | |
154 | GBR indexed | |
155 | ||
156 | @item @var{addr} | |
157 | @itemx @@(@var{disp}, PC) | |
158 | PC relative address (for branch or for addressing memory). The | |
159 | @code{@value{AS}} implementation allows you to use the simpler form | |
160 | @var{addr} anywhere a PC relative address is called for; the alternate | |
161 | form is supported for compatibility with other assemblers. | |
162 | ||
163 | @item #@var{imm} | |
164 | Immediate data | |
165 | @end table | |
166 | ||
167 | @node SH Floating Point | |
168 | @section Floating Point | |
169 | ||
170 | @cindex floating point, SH (@sc{ieee}) | |
171 | @cindex SH floating point (@sc{ieee}) | |
303e7b79 NC |
172 | SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other |
173 | SH groups can use @code{.float} directive to generate @sc{ieee} | |
174 | floating-point numbers. | |
175 | ||
176 | SH2E and SH3E support single-precision floating point calculations as | |
177 | well as entirely PCAPI compatible emulation of double-precision | |
178 | floating point calculations. SH2E and SH3E instructions are a subset of | |
179 | the floating point calculations conforming to the IEEE754 standard. | |
180 | ||
181 | In addition to single-precision and double-precision floating-point | |
182 | operation capability, the on-chip FPU of SH4 has a 128-bit graphic | |
183 | engine that enables 32-bit floating-point data to be processed 128 | |
184 | bits at a time. It also supports 4 * 4 array operations and inner | |
185 | product operations. Also, a superscalar architecture is employed that | |
186 | enables simultaneous execution of two instructions (including FPU | |
187 | instructions), providing performance of up to twice that of | |
188 | conventional architectures at the same frequency. | |
252b5132 RH |
189 | |
190 | @node SH Directives | |
191 | @section SH Machine Directives | |
192 | ||
193 | @cindex SH machine directives | |
194 | @cindex machine directives, SH | |
195 | @cindex @code{uaword} directive, SH | |
196 | @cindex @code{ualong} directive, SH | |
197 | ||
198 | @table @code | |
199 | @item uaword | |
200 | @itemx ualong | |
201 | @code{@value{AS}} will issue a warning when a misaligned @code{.word} or | |
202 | @code{.long} directive is used. You may use @code{.uaword} or | |
203 | @code{.ualong} to indicate that the value is intentionally misaligned. | |
204 | @end table | |
205 | ||
206 | @node SH Opcodes | |
207 | @section Opcodes | |
208 | ||
209 | @cindex SH opcode summary | |
210 | @cindex opcode summary, SH | |
211 | @cindex mnemonics, SH | |
212 | @cindex instruction summary, SH | |
213 | For detailed information on the SH machine instruction set, see | |
ef230218 JR |
214 | @cite{SH-Microcomputer User's Manual} (Renesas) or |
215 | @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and | |
216 | @cite{SuperH (SH) 64-Bit RISC Series} (SuperH). | |
252b5132 RH |
217 | |
218 | @code{@value{AS}} implements all the standard SH opcodes. No additional | |
219 | pseudo-instructions are needed on this family. Note, however, that | |
220 | because @code{@value{AS}} supports a simpler form of PC-relative | |
221 | addressing, you may simply write (for example) | |
222 | ||
223 | @example | |
224 | mov.l bar,r0 | |
225 | @end example | |
226 | ||
227 | @noindent | |
228 | where other assemblers might require an explicit displacement to | |
229 | @code{bar} from the program counter: | |
230 | ||
231 | @example | |
232 | mov.l @@(@var{disp}, PC) | |
233 | @end example | |
234 | ||
235 | @ifset SMALL | |
236 | @c this table, due to the multi-col faking and hardcoded order, looks silly | |
237 | @c except in smallbook. See comments below "@set SMALL" near top of this file. | |
238 | ||
239 | Here is a summary of SH opcodes: | |
240 | ||
241 | @page | |
242 | @smallexample | |
243 | @i{Legend:} | |
244 | Rn @r{a numbered register} | |
245 | Rm @r{another numbered register} | |
246 | #imm @r{immediate data} | |
247 | disp @r{displacement} | |
248 | disp8 @r{8-bit displacement} | |
249 | disp12 @r{12-bit displacement} | |
250 | ||
251 | add #imm,Rn lds.l @@Rn+,PR | |
252 | add Rm,Rn mac.w @@Rm+,@@Rn+ | |
253 | addc Rm,Rn mov #imm,Rn | |
254 | addv Rm,Rn mov Rm,Rn | |
255 | and #imm,R0 mov.b Rm,@@(R0,Rn) | |
256 | and Rm,Rn mov.b Rm,@@-Rn | |
257 | and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn | |
258 | bf disp8 mov.b @@(disp,Rm),R0 | |
259 | bra disp12 mov.b @@(disp,GBR),R0 | |
260 | bsr disp12 mov.b @@(R0,Rm),Rn | |
261 | bt disp8 mov.b @@Rm+,Rn | |
262 | clrmac mov.b @@Rm,Rn | |
263 | clrt mov.b R0,@@(disp,Rm) | |
264 | cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) | |
265 | cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) | |
266 | cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) | |
267 | cmp/gt Rm,Rn mov.l Rm,@@-Rn | |
268 | cmp/hi Rm,Rn mov.l Rm,@@Rn | |
269 | cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm | |
270 | cmp/pl Rn mov.l @@(disp,GBR),R0 | |
271 | cmp/pz Rn mov.l @@(disp,PC),Rn | |
272 | cmp/str Rm,Rn mov.l @@(R0,Rm),Rn | |
273 | div0s Rm,Rn mov.l @@Rm+,Rn | |
274 | div0u mov.l @@Rm,Rn | |
275 | div1 Rm,Rn mov.l R0,@@(disp,GBR) | |
276 | exts.b Rm,Rn mov.w Rm,@@(R0,Rn) | |
277 | exts.w Rm,Rn mov.w Rm,@@-Rn | |
278 | extu.b Rm,Rn mov.w Rm,@@Rn | |
279 | extu.w Rm,Rn mov.w @@(disp,Rm),R0 | |
280 | jmp @@Rn mov.w @@(disp,GBR),R0 | |
281 | jsr @@Rn mov.w @@(disp,PC),Rn | |
282 | ldc Rn,GBR mov.w @@(R0,Rm),Rn | |
283 | ldc Rn,SR mov.w @@Rm+,Rn | |
284 | ldc Rn,VBR mov.w @@Rm,Rn | |
285 | ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) | |
286 | ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) | |
287 | ldc.l @@Rn+,VBR mova @@(disp,PC),R0 | |
288 | lds Rn,MACH movt Rn | |
289 | lds Rn,MACL muls Rm,Rn | |
290 | lds Rn,PR mulu Rm,Rn | |
291 | lds.l @@Rn+,MACH neg Rm,Rn | |
292 | lds.l @@Rn+,MACL negc Rm,Rn | |
293 | @page | |
294 | nop stc VBR,Rn | |
295 | not Rm,Rn stc.l GBR,@@-Rn | |
296 | or #imm,R0 stc.l SR,@@-Rn | |
297 | or Rm,Rn stc.l VBR,@@-Rn | |
298 | or.b #imm,@@(R0,GBR) sts MACH,Rn | |
299 | rotcl Rn sts MACL,Rn | |
300 | rotcr Rn sts PR,Rn | |
301 | rotl Rn sts.l MACH,@@-Rn | |
302 | rotr Rn sts.l MACL,@@-Rn | |
303 | rte sts.l PR,@@-Rn | |
304 | rts sub Rm,Rn | |
305 | sett subc Rm,Rn | |
306 | shal Rn subv Rm,Rn | |
307 | shar Rn swap.b Rm,Rn | |
308 | shll Rn swap.w Rm,Rn | |
309 | shll16 Rn tas.b @@Rn | |
310 | shll2 Rn trapa #imm | |
311 | shll8 Rn tst #imm,R0 | |
312 | shlr Rn tst Rm,Rn | |
313 | shlr16 Rn tst.b #imm,@@(R0,GBR) | |
314 | shlr2 Rn xor #imm,R0 | |
315 | shlr8 Rn xor Rm,Rn | |
316 | sleep xor.b #imm,@@(R0,GBR) | |
317 | stc GBR,Rn xtrct Rm,Rn | |
318 | stc SR,Rn | |
319 | @end smallexample | |
320 | @end ifset | |
321 | ||
c2dcd04e | 322 | @ifset Renesas-all |
252b5132 RH |
323 | @ifclear GENERIC |
324 | @raisesections | |
325 | @end ifclear | |
326 | @end ifset | |
327 |