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8e45593f | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, |
32b9ff0d | 2 | @c 2005, 2008, 2010, 2011, 2012 Free Software Foundation, Inc. |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @page | |
6 | @node SH-Dependent | |
ef230218 | 7 | @chapter Renesas / SuperH SH Dependent Features |
252b5132 RH |
8 | |
9 | @cindex SH support | |
10 | @menu | |
11 | * SH Options:: Options | |
12 | * SH Syntax:: Syntax | |
13 | * SH Floating Point:: Floating Point | |
14 | * SH Directives:: SH Machine Directives | |
15 | * SH Opcodes:: Opcodes | |
16 | @end menu | |
17 | ||
18 | @node SH Options | |
19 | @section Options | |
20 | ||
7649aa50 NC |
21 | @cindex SH options |
22 | @cindex options, SH | |
c2dcd04e | 23 | @code{@value{AS}} has following command-line options for the Renesas |
ef230218 | 24 | (formerly Hitachi) / SuperH SH family. |
252b5132 | 25 | |
7649aa50 | 26 | @table @code |
37dedf66 NC |
27 | @kindex --little |
28 | @kindex --big | |
29 | @kindex --relax | |
30 | @kindex --small | |
31 | @kindex --dsp | |
32 | @kindex --renesas | |
33 | @kindex --allow-reg-prefix | |
34 | ||
35 | @item --little | |
7649aa50 NC |
36 | Generate little endian code. |
37 | ||
37dedf66 | 38 | @item --big |
7649aa50 NC |
39 | Generate big endian code. |
40 | ||
37dedf66 | 41 | @item --relax |
7649aa50 NC |
42 | Alter jump instructions for long displacements. |
43 | ||
37dedf66 | 44 | @item --small |
7649aa50 NC |
45 | Align sections to 4 byte boundaries, not 16. |
46 | ||
37dedf66 | 47 | @item --dsp |
7649aa50 NC |
48 | Enable sh-dsp insns, and disable sh3e / sh4 insns. |
49 | ||
37dedf66 | 50 | @item --renesas |
f55629b8 KK |
51 | Disable optimization with section symbol for compatibility with |
52 | Renesas assembler. | |
53 | ||
37dedf66 NC |
54 | @item --allow-reg-prefix |
55 | Allow '$' as a register name prefix. | |
56 | ||
8e45593f NC |
57 | @kindex --fdpic |
58 | @item --fdpic | |
59 | Generate an FDPIC object file. | |
60 | ||
37dedf66 | 61 | @item --isa=sh4 | sh4a |
88da98f3 | 62 | Specify the sh4 or sh4a instruction set. |
37dedf66 | 63 | @item --isa=dsp |
88da98f3 | 64 | Enable sh-dsp insns, and disable sh3e / sh4 insns. |
37dedf66 | 65 | @item --isa=fp |
88da98f3 | 66 | Enable sh2e, sh3e, sh4, and sh4a insn sets. |
37dedf66 | 67 | @item --isa=all |
88da98f3 MS |
68 | Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. |
69 | ||
6fd4f6cc DD |
70 | @item -h-tick-hex |
71 | Support H'00 style hex constants in addition to 0x00 style. | |
72 | ||
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73 | @end table |
74 | ||
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75 | @node SH Syntax |
76 | @section Syntax | |
77 | ||
78 | @menu | |
79 | * SH-Chars:: Special Characters | |
80 | * SH-Regs:: Register Names | |
81 | * SH-Addressing:: Addressing Modes | |
82 | @end menu | |
83 | ||
84 | @node SH-Chars | |
85 | @subsection Special Characters | |
86 | ||
87 | @cindex line comment character, SH | |
88 | @cindex SH line comment character | |
89 | @samp{!} is the line comment character. | |
90 | ||
91 | @cindex line separator, SH | |
92 | @cindex statement separator, SH | |
93 | @cindex SH line separator | |
94 | You can use @samp{;} instead of a newline to separate statements. | |
95 | ||
7c31ae13 NC |
96 | If a @samp{#} appears as the first character of a line then the whole |
97 | line is treated as a comment, but in this case the line could also be | |
98 | a logical line number directive (@pxref{Comments}) or a preprocessor | |
99 | control command (@pxref{Preprocessing}). | |
100 | ||
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101 | @cindex symbol names, @samp{$} in |
102 | @cindex @code{$} in symbol names | |
103 | Since @samp{$} has no special meaning, you may use it in symbol names. | |
104 | ||
105 | @node SH-Regs | |
106 | @subsection Register Names | |
107 | ||
108 | @cindex SH registers | |
109 | @cindex registers, SH | |
110 | You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, | |
111 | @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, | |
112 | @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, | |
113 | and @samp{r15} to refer to the SH registers. | |
114 | ||
115 | The SH also has these control registers: | |
116 | ||
117 | @table @code | |
118 | @item pr | |
119 | procedure register (holds return address) | |
120 | ||
121 | @item pc | |
122 | program counter | |
123 | ||
124 | @item mach | |
125 | @itemx macl | |
126 | high and low multiply accumulator registers | |
127 | ||
128 | @item sr | |
129 | status register | |
130 | ||
131 | @item gbr | |
132 | global base register | |
133 | ||
134 | @item vbr | |
135 | vector base register (for interrupt vectors) | |
136 | @end table | |
137 | ||
138 | @node SH-Addressing | |
139 | @subsection Addressing Modes | |
140 | ||
141 | @cindex addressing modes, SH | |
142 | @cindex SH addressing modes | |
143 | @code{@value{AS}} understands the following addressing modes for the SH. | |
144 | @code{R@var{n}} in the following refers to any of the numbered | |
145 | registers, but @emph{not} the control registers. | |
146 | ||
147 | @table @code | |
148 | @item R@var{n} | |
149 | Register direct | |
150 | ||
151 | @item @@R@var{n} | |
152 | Register indirect | |
153 | ||
154 | @item @@-R@var{n} | |
155 | Register indirect with pre-decrement | |
156 | ||
157 | @item @@R@var{n}+ | |
158 | Register indirect with post-increment | |
159 | ||
160 | @item @@(@var{disp}, R@var{n}) | |
161 | Register indirect with displacement | |
162 | ||
163 | @item @@(R0, R@var{n}) | |
164 | Register indexed | |
165 | ||
166 | @item @@(@var{disp}, GBR) | |
167 | @code{GBR} offset | |
168 | ||
169 | @item @@(R0, GBR) | |
170 | GBR indexed | |
171 | ||
172 | @item @var{addr} | |
173 | @itemx @@(@var{disp}, PC) | |
174 | PC relative address (for branch or for addressing memory). The | |
175 | @code{@value{AS}} implementation allows you to use the simpler form | |
176 | @var{addr} anywhere a PC relative address is called for; the alternate | |
177 | form is supported for compatibility with other assemblers. | |
178 | ||
179 | @item #@var{imm} | |
180 | Immediate data | |
181 | @end table | |
182 | ||
183 | @node SH Floating Point | |
184 | @section Floating Point | |
185 | ||
186 | @cindex floating point, SH (@sc{ieee}) | |
187 | @cindex SH floating point (@sc{ieee}) | |
303e7b79 NC |
188 | SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other |
189 | SH groups can use @code{.float} directive to generate @sc{ieee} | |
190 | floating-point numbers. | |
191 | ||
192 | SH2E and SH3E support single-precision floating point calculations as | |
193 | well as entirely PCAPI compatible emulation of double-precision | |
194 | floating point calculations. SH2E and SH3E instructions are a subset of | |
195 | the floating point calculations conforming to the IEEE754 standard. | |
196 | ||
197 | In addition to single-precision and double-precision floating-point | |
198 | operation capability, the on-chip FPU of SH4 has a 128-bit graphic | |
199 | engine that enables 32-bit floating-point data to be processed 128 | |
200 | bits at a time. It also supports 4 * 4 array operations and inner | |
201 | product operations. Also, a superscalar architecture is employed that | |
202 | enables simultaneous execution of two instructions (including FPU | |
203 | instructions), providing performance of up to twice that of | |
204 | conventional architectures at the same frequency. | |
252b5132 RH |
205 | |
206 | @node SH Directives | |
207 | @section SH Machine Directives | |
208 | ||
209 | @cindex SH machine directives | |
210 | @cindex machine directives, SH | |
211 | @cindex @code{uaword} directive, SH | |
212 | @cindex @code{ualong} directive, SH | |
32b9ff0d | 213 | @cindex @code{uaquad} directive, SH |
252b5132 RH |
214 | |
215 | @table @code | |
216 | @item uaword | |
217 | @itemx ualong | |
32b9ff0d TS |
218 | @itemx uaquad |
219 | @code{@value{AS}} will issue a warning when a misaligned @code{.word}, | |
220 | @code{.long}, or @code{.quad} directive is used. You may use | |
221 | @code{.uaword}, @code{.ualong}, or @code{.uaquad} to indicate that the | |
222 | value is intentionally misaligned. | |
252b5132 RH |
223 | @end table |
224 | ||
225 | @node SH Opcodes | |
226 | @section Opcodes | |
227 | ||
228 | @cindex SH opcode summary | |
229 | @cindex opcode summary, SH | |
230 | @cindex mnemonics, SH | |
231 | @cindex instruction summary, SH | |
232 | For detailed information on the SH machine instruction set, see | |
ef230218 JR |
233 | @cite{SH-Microcomputer User's Manual} (Renesas) or |
234 | @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and | |
235 | @cite{SuperH (SH) 64-Bit RISC Series} (SuperH). | |
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236 | |
237 | @code{@value{AS}} implements all the standard SH opcodes. No additional | |
238 | pseudo-instructions are needed on this family. Note, however, that | |
239 | because @code{@value{AS}} supports a simpler form of PC-relative | |
240 | addressing, you may simply write (for example) | |
241 | ||
242 | @example | |
243 | mov.l bar,r0 | |
244 | @end example | |
245 | ||
246 | @noindent | |
247 | where other assemblers might require an explicit displacement to | |
248 | @code{bar} from the program counter: | |
249 | ||
250 | @example | |
251 | mov.l @@(@var{disp}, PC) | |
252 | @end example | |
253 | ||
254 | @ifset SMALL | |
255 | @c this table, due to the multi-col faking and hardcoded order, looks silly | |
256 | @c except in smallbook. See comments below "@set SMALL" near top of this file. | |
257 | ||
258 | Here is a summary of SH opcodes: | |
259 | ||
260 | @page | |
261 | @smallexample | |
262 | @i{Legend:} | |
263 | Rn @r{a numbered register} | |
264 | Rm @r{another numbered register} | |
265 | #imm @r{immediate data} | |
266 | disp @r{displacement} | |
267 | disp8 @r{8-bit displacement} | |
268 | disp12 @r{12-bit displacement} | |
269 | ||
270 | add #imm,Rn lds.l @@Rn+,PR | |
271 | add Rm,Rn mac.w @@Rm+,@@Rn+ | |
272 | addc Rm,Rn mov #imm,Rn | |
273 | addv Rm,Rn mov Rm,Rn | |
274 | and #imm,R0 mov.b Rm,@@(R0,Rn) | |
275 | and Rm,Rn mov.b Rm,@@-Rn | |
276 | and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn | |
277 | bf disp8 mov.b @@(disp,Rm),R0 | |
278 | bra disp12 mov.b @@(disp,GBR),R0 | |
279 | bsr disp12 mov.b @@(R0,Rm),Rn | |
280 | bt disp8 mov.b @@Rm+,Rn | |
281 | clrmac mov.b @@Rm,Rn | |
282 | clrt mov.b R0,@@(disp,Rm) | |
283 | cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) | |
284 | cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) | |
285 | cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) | |
286 | cmp/gt Rm,Rn mov.l Rm,@@-Rn | |
287 | cmp/hi Rm,Rn mov.l Rm,@@Rn | |
288 | cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm | |
289 | cmp/pl Rn mov.l @@(disp,GBR),R0 | |
290 | cmp/pz Rn mov.l @@(disp,PC),Rn | |
291 | cmp/str Rm,Rn mov.l @@(R0,Rm),Rn | |
292 | div0s Rm,Rn mov.l @@Rm+,Rn | |
293 | div0u mov.l @@Rm,Rn | |
294 | div1 Rm,Rn mov.l R0,@@(disp,GBR) | |
295 | exts.b Rm,Rn mov.w Rm,@@(R0,Rn) | |
296 | exts.w Rm,Rn mov.w Rm,@@-Rn | |
297 | extu.b Rm,Rn mov.w Rm,@@Rn | |
298 | extu.w Rm,Rn mov.w @@(disp,Rm),R0 | |
299 | jmp @@Rn mov.w @@(disp,GBR),R0 | |
300 | jsr @@Rn mov.w @@(disp,PC),Rn | |
301 | ldc Rn,GBR mov.w @@(R0,Rm),Rn | |
302 | ldc Rn,SR mov.w @@Rm+,Rn | |
303 | ldc Rn,VBR mov.w @@Rm,Rn | |
304 | ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) | |
305 | ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) | |
306 | ldc.l @@Rn+,VBR mova @@(disp,PC),R0 | |
307 | lds Rn,MACH movt Rn | |
308 | lds Rn,MACL muls Rm,Rn | |
309 | lds Rn,PR mulu Rm,Rn | |
310 | lds.l @@Rn+,MACH neg Rm,Rn | |
311 | lds.l @@Rn+,MACL negc Rm,Rn | |
312 | @page | |
313 | nop stc VBR,Rn | |
314 | not Rm,Rn stc.l GBR,@@-Rn | |
315 | or #imm,R0 stc.l SR,@@-Rn | |
316 | or Rm,Rn stc.l VBR,@@-Rn | |
317 | or.b #imm,@@(R0,GBR) sts MACH,Rn | |
318 | rotcl Rn sts MACL,Rn | |
319 | rotcr Rn sts PR,Rn | |
320 | rotl Rn sts.l MACH,@@-Rn | |
321 | rotr Rn sts.l MACL,@@-Rn | |
322 | rte sts.l PR,@@-Rn | |
323 | rts sub Rm,Rn | |
324 | sett subc Rm,Rn | |
325 | shal Rn subv Rm,Rn | |
326 | shar Rn swap.b Rm,Rn | |
327 | shll Rn swap.w Rm,Rn | |
328 | shll16 Rn tas.b @@Rn | |
329 | shll2 Rn trapa #imm | |
330 | shll8 Rn tst #imm,R0 | |
331 | shlr Rn tst Rm,Rn | |
332 | shlr16 Rn tst.b #imm,@@(R0,GBR) | |
333 | shlr2 Rn xor #imm,R0 | |
334 | shlr8 Rn xor Rm,Rn | |
335 | sleep xor.b #imm,@@(R0,GBR) | |
336 | stc GBR,Rn xtrct Rm,Rn | |
337 | stc SR,Rn | |
338 | @end smallexample | |
339 | @end ifset | |
340 | ||
c2dcd04e | 341 | @ifset Renesas-all |
252b5132 RH |
342 | @ifclear GENERIC |
343 | @raisesections | |
344 | @end ifclear | |
345 | @end ifset | |
346 |