[deliverable/binutils-gdb.git] / gas / doc / c-sh.texi

@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH-Dependent
@chapter Hitachi SH Dependent Features

@cindex SH support
@menu
* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes
@end menu

@node SH Options
@section Options

@cindex SH options (none)
@cindex options, SH (none)
@code{@value{AS}} has no additional command-line options for the Hitachi
SH family.

@node SH Syntax
@section Syntax

@menu
* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes
@end menu

@node SH-Chars
@subsection Special Characters

@cindex line comment character, SH
@cindex SH line comment character
@samp{!} is the line comment character.

@cindex line separator, SH
@cindex statement separator, SH
@cindex SH line separator
You can use @samp{;} instead of a newline to separate statements.

@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.

@node SH-Regs
@subsection Register Names

@cindex SH registers
@cindex registers, SH
You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
and @samp{r15} to refer to the SH registers.

The SH also has these control registers:

@table @code
@item pr
procedure register (holds return address)

@item pc
program counter

@item mach
@itemx macl
high and low multiply accumulator registers

@item sr
status register

@item gbr
global base register

@item vbr
vector base register (for interrupt vectors)
@end table

@node SH-Addressing
@subsection Addressing Modes

@cindex addressing modes, SH
@cindex SH addressing modes
@code{@value{AS}} understands the following addressing modes for the SH.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.

@table @code
@item R@var{n}
Register direct

@item @@R@var{n}
Register indirect

@item @@-R@var{n}
Register indirect with pre-decrement

@item @@R@var{n}+
Register indirect with post-increment

@item @@(@var{disp}, R@var{n})
Register indirect with displacement

@item @@(R0, R@var{n})
Register indexed

@item @@(@var{disp}, GBR)
@code{GBR} offset

@item @@(R0, GBR)
GBR indexed

@item @var{addr}
@itemx @@(@var{disp}, PC)
PC relative address (for branch or for addressing memory).  The
@code{@value{AS}} implementation allows you to use the simpler form
@var{addr} anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.

@item #@var{imm}
Immediate data
@end table

@node SH Floating Point
@section Floating Point

@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
The SH family has no hardware floating point, but the @code{.float}
directive generates @sc{ieee} floating-point numbers for compatibility
with other development tools.

@node SH Directives
@section SH Machine Directives

@cindex SH machine directives (none)
@cindex machine directives, SH (none)
@cindex @code{word} directive, SH
@cindex @code{int} directive, SH
@code{@value{AS}} has no machine-dependent directives for the SH.

@node SH Opcodes
@section Opcodes

@cindex SH opcode summary
@cindex opcode summary, SH
@cindex mnemonics, SH
@cindex instruction summary, SH
For detailed information on the SH machine instruction set, see
@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).

@code{@value{AS}} implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because @code{@value{AS}} supports a simpler form of PC-relative
addressing, you may simply write (for example)

@example
mov.l  bar,r0
@end example

@noindent
where other assemblers might require an explicit displacement to
@code{bar} from the program counter:

@example
mov.l  @@(@var{disp}, PC)
@end example

@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook.  See comments below "@set SMALL" near top of this file.

Here is a summary of SH opcodes:

@page
@smallexample
@i{Legend:}
Rn        @r{a numbered register}
Rm        @r{another numbered register}
#imm      @r{immediate data}
disp      @r{displacement}
disp8     @r{8-bit displacement}
disp12    @r{12-bit displacement}

add #imm,Rn                    lds.l @@Rn+,PR              
add Rm,Rn                      mac.w @@Rm+,@@Rn+           
addc Rm,Rn                     mov #imm,Rn                 
addv Rm,Rn                     mov Rm,Rn                   
and #imm,R0                    mov.b Rm,@@(R0,Rn)          
and Rm,Rn                      mov.b Rm,@@-Rn              
and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn               
bf disp8                       mov.b @@(disp,Rm),R0        
bra disp12                     mov.b @@(disp,GBR),R0       
bsr disp12                     mov.b @@(R0,Rm),Rn          
bt disp8                       mov.b @@Rm+,Rn              
clrmac                         mov.b @@Rm,Rn               
clrt                           mov.b R0,@@(disp,Rm)        
cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)       
cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)        
cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)          
cmp/gt Rm,Rn                   mov.l Rm,@@-Rn              
cmp/hi Rm,Rn                   mov.l Rm,@@Rn               
cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm        
cmp/pl Rn                      mov.l @@(disp,GBR),R0       
cmp/pz Rn                      mov.l @@(disp,PC),Rn        
cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn          
div0s Rm,Rn                    mov.l @@Rm+,Rn              
div0u                          mov.l @@Rm,Rn               
div1 Rm,Rn                     mov.l R0,@@(disp,GBR)       
exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)          
exts.w Rm,Rn                   mov.w Rm,@@-Rn              
extu.b Rm,Rn                   mov.w Rm,@@Rn               
extu.w Rm,Rn                   mov.w @@(disp,Rm),R0        
jmp @@Rn                        mov.w @@(disp,GBR),R0       
jsr @@Rn                        mov.w @@(disp,PC),Rn        
ldc Rn,GBR                     mov.w @@(R0,Rm),Rn          
ldc Rn,SR                      mov.w @@Rm+,Rn              
ldc Rn,VBR                     mov.w @@Rm,Rn               
ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)        
ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)       
ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0         
lds Rn,MACH                    movt Rn                     
lds Rn,MACL                    muls Rm,Rn                  
lds Rn,PR                      mulu Rm,Rn                  
lds.l @@Rn+,MACH                neg Rm,Rn                   
lds.l @@Rn+,MACL                negc Rm,Rn                  
@page
nop                            stc VBR,Rn                
not Rm,Rn                      stc.l GBR,@@-Rn           
or #imm,R0                     stc.l SR,@@-Rn            
or Rm,Rn                       stc.l VBR,@@-Rn           
or.b #imm,@@(R0,GBR)            sts MACH,Rn               
rotcl Rn                       sts MACL,Rn               
rotcr Rn                       sts PR,Rn                 
rotl Rn                        sts.l MACH,@@-Rn          
rotr Rn                        sts.l MACL,@@-Rn          
rte                            sts.l PR,@@-Rn            
rts                            sub Rm,Rn                 
sett                           subc Rm,Rn                
shal Rn                        subv Rm,Rn                
shar Rn                        swap.b Rm,Rn              
shll Rn                        swap.w Rm,Rn              
shll16 Rn                      tas.b @@Rn                
shll2 Rn                       trapa #imm                
shll8 Rn                       tst #imm,R0               
shlr Rn                        tst Rm,Rn                 
shlr16 Rn                      tst.b #imm,@@(R0,GBR)     
shlr2 Rn                       xor #imm,R0               
shlr8 Rn                       xor Rm,Rn                 
sleep                          xor.b #imm,@@(R0,GBR)     
stc GBR,Rn                     xtrct Rm,Rn               
stc SR,Rn
@end smallexample
@end ifset

@ifset Hitachi-all
@ifclear GENERIC
@raisesections
@end ifclear
@end ifset
Commit	Line	Data
db8e56dc KR	1	@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
	2	@c This is part of the GAS manual.
	3	@c For copying conditions, see the file as.texinfo.
	4	@page
	5	@node SH-Dependent
	6	@chapter Hitachi SH Dependent Features
	7
	8	@cindex SH support
	9	@menu
	10	* SH Options:: Options
	11	* SH Syntax:: Syntax
	12	* SH Floating Point:: Floating Point
	13	* SH Directives:: SH Machine Directives
	14	* SH Opcodes:: Opcodes
	15	@end menu
	16
	17	@node SH Options
	18	@section Options
	19
	20	@cindex SH options (none)
	21	@cindex options, SH (none)
	22	@code{@value{AS}} has no additional command-line options for the Hitachi
	23	SH family.
	24
	25	@node SH Syntax
	26	@section Syntax
	27
	28	@menu
	29	* SH-Chars:: Special Characters
	30	* SH-Regs:: Register Names
	31	* SH-Addressing:: Addressing Modes
	32	@end menu
	33
	34	@node SH-Chars
	35	@subsection Special Characters
	36
	37	@cindex line comment character, SH
	38	@cindex SH line comment character
	39	@samp{!} is the line comment character.
	40
	41	@cindex line separator, SH
	42	@cindex statement separator, SH
	43	@cindex SH line separator
	44	You can use @samp{;} instead of a newline to separate statements.
	45
	46	@cindex symbol names, @samp{$} in
	47	@cindex @code{$} in symbol names
	48	Since @samp{$} has no special meaning, you may use it in symbol names.
	49
	50	@node SH-Regs
	51	@subsection Register Names
	52
	53	@cindex SH registers
	54	@cindex registers, SH
	55	You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
	56	@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
	57	@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
	58	and @samp{r15} to refer to the SH registers.
	59
	60	The SH also has these control registers:
	61
	62	@table @code
	63	@item pr
	64	procedure register (holds return address)
65
66	@item pc
67	program counter
68
69	@item mach
70	@itemx macl
71	high and low multiply accumulator registers
72
73	@item sr
74	status register
75
76	@item gbr
77	global base register
78
79	@item vbr
80	vector base register (for interrupt vectors)
81	@end table
82
83	@node SH-Addressing
84	@subsection Addressing Modes
85
86	@cindex addressing modes, SH
87	@cindex SH addressing modes
88	@code{@value{AS}} understands the following addressing modes for the SH.
89	@code{R@var{n}} in the following refers to any of the numbered
90	registers, but @emph{not} the control registers.
91
92	@table @code
93	@item R@var{n}
94	Register direct
95
96	@item @@R@var{n}
97	Register indirect
98
99	@item @@-R@var{n}
100	Register indirect with pre-decrement
101
102	@item @@R@var{n}+
103	Register indirect with post-increment
104
105	@item @@(@var{disp}, R@var{n})
106	Register indirect with displacement
107
108	@item @@(R0, R@var{n})
109	Register indexed
110
111	@item @@(@var{disp}, GBR)
112	@code{GBR} offset
113
114	@item @@(R0, GBR)
115	GBR indexed
116
117	@item @var{addr}
118	@itemx @@(@var{disp}, PC)
119	PC relative address (for branch or for addressing memory). The
120	@code{@value{AS}} implementation allows you to use the simpler form
121	@var{addr} anywhere a PC relative address is called for; the alternate
122	form is supported for compatibility with other assemblers.
123
124	@item #@var{imm}
125	Immediate data
126	@end table
127
128	@node SH Floating Point
129	@section Floating Point
130
131	@cindex floating point, SH (@sc{ieee})
132	@cindex SH floating point (@sc{ieee})
133	The SH family has no hardware floating point, but the @code{.float}
134	directive generates @sc{ieee} floating-point numbers for compatibility
135	with other development tools.
136
137	@node SH Directives
138	@section SH Machine Directives
139
140	@cindex SH machine directives (none)
141	@cindex machine directives, SH (none)
142	@cindex @code{word} directive, SH
143	@cindex @code{int} directive, SH
144	@code{@value{AS}} has no machine-dependent directives for the SH.
145
146	@node SH Opcodes
147	@section Opcodes
148
149	@cindex SH opcode summary
150	@cindex opcode summary, SH
151	@cindex mnemonics, SH
152	@cindex instruction summary, SH
153	For detailed information on the SH machine instruction set, see
154	@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).
155
156	@code{@value{AS}} implements all the standard SH opcodes. No additional
157	pseudo-instructions are needed on this family. Note, however, that
158	because @code{@value{AS}} supports a simpler form of PC-relative
159	addressing, you may simply write (for example)
160
161	@example
162	mov.l bar,r0
163	@end example
164
165	@noindent
166	where other assemblers might require an explicit displacement to
167	@code{bar} from the program counter:
168
169	@example
170	mov.l @@(@var{disp}, PC)
171	@end example
172
173	@ifset SMALL
174	@c this table, due to the multi-col faking and hardcoded order, looks silly
175	@c except in smallbook. See comments below "@set SMALL" near top of this file.
176
177	Here is a summary of SH opcodes:
178
179	@page
180	@smallexample
181	@i{Legend:}
182	Rn @r{a numbered register}
183	Rm @r{another numbered register}
184	#imm @r{immediate data}
185	disp @r{displacement}
186	disp8 @r{8-bit displacement}
187	disp12 @r{12-bit displacement}
188
189	add #imm,Rn lds.l @@Rn+,PR
190	add Rm,Rn mac.w @@Rm+,@@Rn+
191	addc Rm,Rn mov #imm,Rn
192	addv Rm,Rn mov Rm,Rn
193	and #imm,R0 mov.b Rm,@@(R0,Rn)
194	and Rm,Rn mov.b Rm,@@-Rn
195	and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
196	bf disp8 mov.b @@(disp,Rm),R0
197	bra disp12 mov.b @@(disp,GBR),R0
198	bsr disp12 mov.b @@(R0,Rm),Rn
199	bt disp8 mov.b @@Rm+,Rn
200	clrmac mov.b @@Rm,Rn
201	clrt mov.b R0,@@(disp,Rm)
202	cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
203	cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
204	cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
205	cmp/gt Rm,Rn mov.l Rm,@@-Rn
206	cmp/hi Rm,Rn mov.l Rm,@@Rn
207	cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
208	cmp/pl Rn mov.l @@(disp,GBR),R0
209	cmp/pz Rn mov.l @@(disp,PC),Rn
210	cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
211	div0s Rm,Rn mov.l @@Rm+,Rn
212	div0u mov.l @@Rm,Rn
213	div1 Rm,Rn mov.l R0,@@(disp,GBR)
214	exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
215	exts.w Rm,Rn mov.w Rm,@@-Rn
216	extu.b Rm,Rn mov.w Rm,@@Rn
217	extu.w Rm,Rn mov.w @@(disp,Rm),R0
218	jmp @@Rn mov.w @@(disp,GBR),R0
219	jsr @@Rn mov.w @@(disp,PC),Rn
220	ldc Rn,GBR mov.w @@(R0,Rm),Rn
221	ldc Rn,SR mov.w @@Rm+,Rn
222	ldc Rn,VBR mov.w @@Rm,Rn
223	ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
224	ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
225	ldc.l @@Rn+,VBR mova @@(disp,PC),R0
226	lds Rn,MACH movt Rn
227	lds Rn,MACL muls Rm,Rn
228	lds Rn,PR mulu Rm,Rn
229	lds.l @@Rn+,MACH neg Rm,Rn
230	lds.l @@Rn+,MACL negc Rm,Rn
231	@page
232	nop stc VBR,Rn
233	not Rm,Rn stc.l GBR,@@-Rn
234	or #imm,R0 stc.l SR,@@-Rn
235	or Rm,Rn stc.l VBR,@@-Rn
236	or.b #imm,@@(R0,GBR) sts MACH,Rn
237	rotcl Rn sts MACL,Rn
238	rotcr Rn sts PR,Rn
239	rotl Rn sts.l MACH,@@-Rn
240	rotr Rn sts.l MACL,@@-Rn
241	rte sts.l PR,@@-Rn
242	rts sub Rm,Rn
243	sett subc Rm,Rn
244	shal Rn subv Rm,Rn
245	shar Rn swap.b Rm,Rn
246	shll Rn swap.w Rm,Rn
247	shll16 Rn tas.b @@Rn
248	shll2 Rn trapa #imm
249	shll8 Rn tst #imm,R0
250	shlr Rn tst Rm,Rn
251	shlr16 Rn tst.b #imm,@@(R0,GBR)
252	shlr2 Rn xor #imm,R0
253	shlr8 Rn xor Rm,Rn
254	sleep xor.b #imm,@@(R0,GBR)
255	stc GBR,Rn xtrct Rm,Rn
256	stc SR,Rn
257	@end smallexample
258	@end ifset
259
260	@ifset Hitachi-all
261	@ifclear GENERIC
262	@raisesections
263	@end ifclear
264	@end ifset
265