[deliverable/binutils-gdb.git] / gas / doc / c-sh.texi

@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, 2005
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH-Dependent
@chapter Renesas / SuperH SH Dependent Features

@cindex SH support
@menu
* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes
@end menu

@node SH Options
@section Options

@cindex SH options
@cindex options, SH
@code{@value{AS}} has following command-line options for the Renesas
(formerly Hitachi) / SuperH SH family.

@table @code
@kindex --little
@kindex --big
@kindex --relax
@kindex --small
@kindex --dsp
@kindex --renesas
@kindex --allow-reg-prefix

@item --little
Generate little endian code.

@item --big
Generate big endian code.

@item --relax
Alter jump instructions for long displacements.

@item --small
Align sections to 4 byte boundaries, not 16.

@item --dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.

@item --renesas
Disable optimization with section symbol for compatibility with
Renesas assembler.

@item --allow-reg-prefix
Allow '$' as a register name prefix.

@item --isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
@item --isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item --isa=fp
Enable sh2e, sh3e, sh4, and sh4a insn sets.
@item --isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.

@end table

@node SH Syntax
@section Syntax

@menu
* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes
@end menu

@node SH-Chars
@subsection Special Characters

@cindex line comment character, SH
@cindex SH line comment character
@samp{!} is the line comment character.

@cindex line separator, SH
@cindex statement separator, SH
@cindex SH line separator
You can use @samp{;} instead of a newline to separate statements.

@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.

@node SH-Regs
@subsection Register Names

@cindex SH registers
@cindex registers, SH
You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
and @samp{r15} to refer to the SH registers.

The SH also has these control registers:

@table @code
@item pr
procedure register (holds return address)

@item pc
program counter

@item mach
@itemx macl
high and low multiply accumulator registers

@item sr
status register

@item gbr
global base register

@item vbr
vector base register (for interrupt vectors)
@end table

@node SH-Addressing
@subsection Addressing Modes

@cindex addressing modes, SH
@cindex SH addressing modes
@code{@value{AS}} understands the following addressing modes for the SH.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.

@table @code
@item R@var{n}
Register direct

@item @@R@var{n}
Register indirect

@item @@-R@var{n}
Register indirect with pre-decrement

@item @@R@var{n}+
Register indirect with post-increment

@item @@(@var{disp}, R@var{n})
Register indirect with displacement

@item @@(R0, R@var{n})
Register indexed

@item @@(@var{disp}, GBR)
@code{GBR} offset

@item @@(R0, GBR)
GBR indexed

@item @var{addr}
@itemx @@(@var{disp}, PC)
PC relative address (for branch or for addressing memory).  The
@code{@value{AS}} implementation allows you to use the simpler form
@var{addr} anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.

@item #@var{imm}
Immediate data
@end table

@node SH Floating Point
@section Floating Point

@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use @code{.float} directive to generate @sc{ieee} 
floating-point numbers. 

SH2E and SH3E support single-precision floating point calculations as 
well as entirely PCAPI compatible emulation of double-precision 
floating point calculations. SH2E and SH3E instructions are a subset of
the floating point calculations conforming to the IEEE754 standard.

In addition to single-precision and double-precision floating-point 
operation capability, the on-chip FPU of SH4 has a 128-bit graphic 
engine that enables 32-bit floating-point data to be processed 128 
bits at a time. It also supports 4 * 4 array operations and inner 
product operations. Also, a superscalar architecture is employed that 
enables simultaneous execution of two instructions (including FPU 
instructions), providing performance of up to twice that of 
conventional architectures at the same frequency.

@node SH Directives
@section SH Machine Directives

@cindex SH machine directives
@cindex machine directives, SH
@cindex @code{uaword} directive, SH
@cindex @code{ualong} directive, SH

@table @code
@item uaword
@itemx ualong
@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
@code{.long} directive is used.  You may use @code{.uaword} or
@code{.ualong} to indicate that the value is intentionally misaligned.
@end table

@node SH Opcodes
@section Opcodes

@cindex SH opcode summary
@cindex opcode summary, SH
@cindex mnemonics, SH
@cindex instruction summary, SH
For detailed information on the SH machine instruction set, see
@cite{SH-Microcomputer User's Manual} (Renesas) or
@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).

@code{@value{AS}} implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because @code{@value{AS}} supports a simpler form of PC-relative
addressing, you may simply write (for example)

@example
mov.l  bar,r0
@end example

@noindent
where other assemblers might require an explicit displacement to
@code{bar} from the program counter:

@example
mov.l  @@(@var{disp}, PC)
@end example

@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook.  See comments below "@set SMALL" near top of this file.

Here is a summary of SH opcodes:

@page
@smallexample
@i{Legend:}
Rn        @r{a numbered register}
Rm        @r{another numbered register}
#imm      @r{immediate data}
disp      @r{displacement}
disp8     @r{8-bit displacement}
disp12    @r{12-bit displacement}

add #imm,Rn                    lds.l @@Rn+,PR              
add Rm,Rn                      mac.w @@Rm+,@@Rn+           
addc Rm,Rn                     mov #imm,Rn                 
addv Rm,Rn                     mov Rm,Rn                   
and #imm,R0                    mov.b Rm,@@(R0,Rn)          
and Rm,Rn                      mov.b Rm,@@-Rn              
and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn               
bf disp8                       mov.b @@(disp,Rm),R0        
bra disp12                     mov.b @@(disp,GBR),R0       
bsr disp12                     mov.b @@(R0,Rm),Rn          
bt disp8                       mov.b @@Rm+,Rn              
clrmac                         mov.b @@Rm,Rn               
clrt                           mov.b R0,@@(disp,Rm)        
cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)       
cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)        
cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)          
cmp/gt Rm,Rn                   mov.l Rm,@@-Rn              
cmp/hi Rm,Rn                   mov.l Rm,@@Rn               
cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm        
cmp/pl Rn                      mov.l @@(disp,GBR),R0       
cmp/pz Rn                      mov.l @@(disp,PC),Rn        
cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn          
div0s Rm,Rn                    mov.l @@Rm+,Rn              
div0u                          mov.l @@Rm,Rn               
div1 Rm,Rn                     mov.l R0,@@(disp,GBR)       
exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)          
exts.w Rm,Rn                   mov.w Rm,@@-Rn              
extu.b Rm,Rn                   mov.w Rm,@@Rn               
extu.w Rm,Rn                   mov.w @@(disp,Rm),R0        
jmp @@Rn                        mov.w @@(disp,GBR),R0       
jsr @@Rn                        mov.w @@(disp,PC),Rn        
ldc Rn,GBR                     mov.w @@(R0,Rm),Rn          
ldc Rn,SR                      mov.w @@Rm+,Rn              
ldc Rn,VBR                     mov.w @@Rm,Rn               
ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)        
ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)       
ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0         
lds Rn,MACH                    movt Rn                     
lds Rn,MACL                    muls Rm,Rn                  
lds Rn,PR                      mulu Rm,Rn                  
lds.l @@Rn+,MACH                neg Rm,Rn                   
lds.l @@Rn+,MACL                negc Rm,Rn                  
@page
nop                            stc VBR,Rn                
not Rm,Rn                      stc.l GBR,@@-Rn           
or #imm,R0                     stc.l SR,@@-Rn            
or Rm,Rn                       stc.l VBR,@@-Rn           
or.b #imm,@@(R0,GBR)            sts MACH,Rn               
rotcl Rn                       sts MACL,Rn               
rotcr Rn                       sts PR,Rn                 
rotl Rn                        sts.l MACH,@@-Rn          
rotr Rn                        sts.l MACL,@@-Rn          
rte                            sts.l PR,@@-Rn            
rts                            sub Rm,Rn                 
sett                           subc Rm,Rn                
shal Rn                        subv Rm,Rn                
shar Rn                        swap.b Rm,Rn              
shll Rn                        swap.w Rm,Rn              
shll16 Rn                      tas.b @@Rn                
shll2 Rn                       trapa #imm                
shll8 Rn                       tst #imm,R0               
shlr Rn                        tst Rm,Rn                 
shlr16 Rn                      tst.b #imm,@@(R0,GBR)     
shlr2 Rn                       xor #imm,R0               
shlr8 Rn                       xor Rm,Rn                 
sleep                          xor.b #imm,@@(R0,GBR)     
stc GBR,Rn                     xtrct Rm,Rn               
stc SR,Rn
@end smallexample
@end ifset

@ifset Renesas-all
@ifclear GENERIC
@raisesections
@end ifclear
@end ifset
Commit	Line	Data
37dedf66	1	@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, 2005
f7e42eb4	2	@c Free Software Foundation, Inc.
252b5132 RH	3	@c This is part of the GAS manual.
	4	@c For copying conditions, see the file as.texinfo.
	5	@page
	6	@node SH-Dependent
ef230218	7	@chapter Renesas / SuperH SH Dependent Features
252b5132 RH	8
	9	@cindex SH support
	10	@menu
	11	* SH Options:: Options
	12	* SH Syntax:: Syntax
	13	* SH Floating Point:: Floating Point
	14	* SH Directives:: SH Machine Directives
	15	* SH Opcodes:: Opcodes
	16	@end menu
	17
	18	@node SH Options
	19	@section Options
	20
7649aa50 NC	21	@cindex SH options
7649aa50 NC	22	@cindex options, SH
c2dcd04e	23	@code{@value{AS}} has following command-line options for the Renesas
ef230218	24	(formerly Hitachi) / SuperH SH family.
252b5132	25
7649aa50	26	@table @code
37dedf66 NC	27	@kindex --little
	28	@kindex --big
	29	@kindex --relax
	30	@kindex --small
	31	@kindex --dsp
	32	@kindex --renesas
	33	@kindex --allow-reg-prefix
	34
	35	@item --little
7649aa50 NC	36	Generate little endian code.
7649aa50 NC	37
37dedf66	38	@item --big
7649aa50 NC	39	Generate big endian code.
7649aa50 NC	40
37dedf66	41	@item --relax
7649aa50 NC	42	Alter jump instructions for long displacements.
7649aa50 NC	43
37dedf66	44	@item --small
7649aa50 NC	45	Align sections to 4 byte boundaries, not 16.
7649aa50 NC	46
37dedf66	47	@item --dsp
7649aa50 NC	48	Enable sh-dsp insns, and disable sh3e / sh4 insns.
7649aa50 NC	49
37dedf66	50	@item --renesas
f55629b8 KK	51	Disable optimization with section symbol for compatibility with
	52	Renesas assembler.
	53
37dedf66 NC	54	@item --allow-reg-prefix
	55	Allow '$' as a register name prefix.
	56
	57	@item --isa=sh4 \| sh4a
88da98f3	58	Specify the sh4 or sh4a instruction set.
37dedf66	59	@item --isa=dsp
88da98f3	60	Enable sh-dsp insns, and disable sh3e / sh4 insns.
37dedf66	61	@item --isa=fp
88da98f3	62	Enable sh2e, sh3e, sh4, and sh4a insn sets.
37dedf66	63	@item --isa=all
88da98f3 MS	64	Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
88da98f3 MS	65
7649aa50 NC	66	@end table
7649aa50 NC	67
252b5132 RH	68	@node SH Syntax
	69	@section Syntax
	70
	71	@menu
	72	* SH-Chars:: Special Characters
	73	* SH-Regs:: Register Names
	74	* SH-Addressing:: Addressing Modes
	75	@end menu
	76
	77	@node SH-Chars
	78	@subsection Special Characters
	79
	80	@cindex line comment character, SH
	81	@cindex SH line comment character
	82	@samp{!} is the line comment character.
	83
	84	@cindex line separator, SH
	85	@cindex statement separator, SH
	86	@cindex SH line separator
	87	You can use @samp{;} instead of a newline to separate statements.
	88
	89	@cindex symbol names, @samp{$} in
	90	@cindex @code{$} in symbol names
	91	Since @samp{$} has no special meaning, you may use it in symbol names.
	92
	93	@node SH-Regs
	94	@subsection Register Names
	95
	96	@cindex SH registers
	97	@cindex registers, SH
	98	You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
	99	@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
	100	@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
	101	and @samp{r15} to refer to the SH registers.
	102
	103	The SH also has these control registers:
	104
	105	@table @code
	106	@item pr
	107	procedure register (holds return address)
	108
	109	@item pc
	110	program counter
	111
	112	@item mach
	113	@itemx macl
	114	high and low multiply accumulator registers
	115
	116	@item sr
	117	status register
	118
	119	@item gbr
	120	global base register
	121
	122	@item vbr
	123	vector base register (for interrupt vectors)
	124	@end table
	125
	126	@node SH-Addressing
	127	@subsection Addressing Modes
	128
	129	@cindex addressing modes, SH
	130	@cindex SH addressing modes
	131	@code{@value{AS}} understands the following addressing modes for the SH.
132	@code{R@var{n}} in the following refers to any of the numbered
133	registers, but @emph{not} the control registers.
134
135	@table @code
136	@item R@var{n}
137	Register direct
138
139	@item @@R@var{n}
140	Register indirect
141
142	@item @@-R@var{n}
143	Register indirect with pre-decrement
144
145	@item @@R@var{n}+
146	Register indirect with post-increment
147
148	@item @@(@var{disp}, R@var{n})
149	Register indirect with displacement
150
151	@item @@(R0, R@var{n})
152	Register indexed
153
154	@item @@(@var{disp}, GBR)
155	@code{GBR} offset
156
157	@item @@(R0, GBR)
158	GBR indexed
159
160	@item @var{addr}
161	@itemx @@(@var{disp}, PC)
162	PC relative address (for branch or for addressing memory). The
163	@code{@value{AS}} implementation allows you to use the simpler form
164	@var{addr} anywhere a PC relative address is called for; the alternate
165	form is supported for compatibility with other assemblers.
166
167	@item #@var{imm}
168	Immediate data
169	@end table
170
171	@node SH Floating Point
172	@section Floating Point
173
174	@cindex floating point, SH (@sc{ieee})
175	@cindex SH floating point (@sc{ieee})
303e7b79 NC	176	SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
	177	SH groups can use @code{.float} directive to generate @sc{ieee}
	178	floating-point numbers.
	179
	180	SH2E and SH3E support single-precision floating point calculations as
	181	well as entirely PCAPI compatible emulation of double-precision
	182	floating point calculations. SH2E and SH3E instructions are a subset of
	183	the floating point calculations conforming to the IEEE754 standard.
	184
	185	In addition to single-precision and double-precision floating-point
	186	operation capability, the on-chip FPU of SH4 has a 128-bit graphic
	187	engine that enables 32-bit floating-point data to be processed 128
	188	bits at a time. It also supports 4 * 4 array operations and inner
	189	product operations. Also, a superscalar architecture is employed that
	190	enables simultaneous execution of two instructions (including FPU
	191	instructions), providing performance of up to twice that of
	192	conventional architectures at the same frequency.
252b5132 RH	193
	194	@node SH Directives
	195	@section SH Machine Directives
	196
	197	@cindex SH machine directives
	198	@cindex machine directives, SH
	199	@cindex @code{uaword} directive, SH
	200	@cindex @code{ualong} directive, SH
	201
	202	@table @code
	203	@item uaword
	204	@itemx ualong
	205	@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
	206	@code{.long} directive is used. You may use @code{.uaword} or
	207	@code{.ualong} to indicate that the value is intentionally misaligned.
	208	@end table
	209
	210	@node SH Opcodes
	211	@section Opcodes
	212
	213	@cindex SH opcode summary
	214	@cindex opcode summary, SH
	215	@cindex mnemonics, SH
	216	@cindex instruction summary, SH
	217	For detailed information on the SH machine instruction set, see
ef230218 JR	218	@cite{SH-Microcomputer User's Manual} (Renesas) or
	219	@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
	220	@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
252b5132 RH	221
	222	@code{@value{AS}} implements all the standard SH opcodes. No additional
	223	pseudo-instructions are needed on this family. Note, however, that
	224	because @code{@value{AS}} supports a simpler form of PC-relative
	225	addressing, you may simply write (for example)
	226
	227	@example
	228	mov.l bar,r0
	229	@end example
	230
	231	@noindent
	232	where other assemblers might require an explicit displacement to
	233	@code{bar} from the program counter:
	234
	235	@example
	236	mov.l @@(@var{disp}, PC)
	237	@end example
	238
	239	@ifset SMALL
	240	@c this table, due to the multi-col faking and hardcoded order, looks silly
	241	@c except in smallbook. See comments below "@set SMALL" near top of this file.
	242
	243	Here is a summary of SH opcodes:
	244
	245	@page
	246	@smallexample
	247	@i{Legend:}
	248	Rn @r{a numbered register}
	249	Rm @r{another numbered register}
	250	#imm @r{immediate data}
	251	disp @r{displacement}
	252	disp8 @r{8-bit displacement}
	253	disp12 @r{12-bit displacement}
	254
	255	add #imm,Rn lds.l @@Rn+,PR
	256	add Rm,Rn mac.w @@Rm+,@@Rn+
	257	addc Rm,Rn mov #imm,Rn
	258	addv Rm,Rn mov Rm,Rn
	259	and #imm,R0 mov.b Rm,@@(R0,Rn)
	260	and Rm,Rn mov.b Rm,@@-Rn
	261	and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
	262	bf disp8 mov.b @@(disp,Rm),R0
	263	bra disp12 mov.b @@(disp,GBR),R0
	264	bsr disp12 mov.b @@(R0,Rm),Rn
	265	bt disp8 mov.b @@Rm+,Rn
	266	clrmac mov.b @@Rm,Rn
	267	clrt mov.b R0,@@(disp,Rm)
	268	cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
	269	cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
	270	cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
	271	cmp/gt Rm,Rn mov.l Rm,@@-Rn
	272	cmp/hi Rm,Rn mov.l Rm,@@Rn
	273	cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
	274	cmp/pl Rn mov.l @@(disp,GBR),R0
	275	cmp/pz Rn mov.l @@(disp,PC),Rn
	276	cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
	277	div0s Rm,Rn mov.l @@Rm+,Rn
	278	div0u mov.l @@Rm,Rn
	279	div1 Rm,Rn mov.l R0,@@(disp,GBR)
	280	exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
	281	exts.w Rm,Rn mov.w Rm,@@-Rn
	282	extu.b Rm,Rn mov.w Rm,@@Rn
	283	extu.w Rm,Rn mov.w @@(disp,Rm),R0
	284	jmp @@Rn mov.w @@(disp,GBR),R0
285	jsr @@Rn mov.w @@(disp,PC),Rn
286	ldc Rn,GBR mov.w @@(R0,Rm),Rn
287	ldc Rn,SR mov.w @@Rm+,Rn
288	ldc Rn,VBR mov.w @@Rm,Rn
289	ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
290	ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
291	ldc.l @@Rn+,VBR mova @@(disp,PC),R0
292	lds Rn,MACH movt Rn
293	lds Rn,MACL muls Rm,Rn
294	lds Rn,PR mulu Rm,Rn
295	lds.l @@Rn+,MACH neg Rm,Rn
296	lds.l @@Rn+,MACL negc Rm,Rn
297	@page
298	nop stc VBR,Rn
299	not Rm,Rn stc.l GBR,@@-Rn
300	or #imm,R0 stc.l SR,@@-Rn
301	or Rm,Rn stc.l VBR,@@-Rn
302	or.b #imm,@@(R0,GBR) sts MACH,Rn
303	rotcl Rn sts MACL,Rn
304	rotcr Rn sts PR,Rn
305	rotl Rn sts.l MACH,@@-Rn
306	rotr Rn sts.l MACL,@@-Rn
307	rte sts.l PR,@@-Rn
308	rts sub Rm,Rn
309	sett subc Rm,Rn
310	shal Rn subv Rm,Rn
311	shar Rn swap.b Rm,Rn
312	shll Rn swap.w Rm,Rn
313	shll16 Rn tas.b @@Rn
314	shll2 Rn trapa #imm
315	shll8 Rn tst #imm,R0
316	shlr Rn tst Rm,Rn
317	shlr16 Rn tst.b #imm,@@(R0,GBR)
318	shlr2 Rn xor #imm,R0
319	shlr8 Rn xor Rm,Rn
320	sleep xor.b #imm,@@(R0,GBR)
321	stc GBR,Rn xtrct Rm,Rn
322	stc SR,Rn
323	@end smallexample
324	@end ifset
325
c2dcd04e	326	@ifset Renesas-all
252b5132 RH	327	@ifclear GENERIC
	328	@raisesections
	329	@end ifclear
	330	@end ifset
	331