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7c31ae13 NC |
1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008, |
2 | @c 2011 | |
f7e42eb4 | 3 | @c Free Software Foundation, Inc. |
252b5132 RH |
4 | @c This is part of the GAS manual. |
5 | @c For copying conditions, see the file as.texinfo. | |
6 | @ifset GENERIC | |
7 | @page | |
8 | @node Sparc-Dependent | |
9 | @chapter SPARC Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter SPARC Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex SPARC support | |
17 | @menu | |
18 | * Sparc-Opts:: Options | |
19 | * Sparc-Aligned-Data:: Option to enforce aligned data | |
c15295d5 | 20 | * Sparc-Syntax:: Syntax |
252b5132 RH |
21 | * Sparc-Float:: Floating Point |
22 | * Sparc-Directives:: Sparc Machine Directives | |
23 | @end menu | |
24 | ||
25 | @node Sparc-Opts | |
26 | @section Options | |
27 | ||
28 | @cindex options for SPARC | |
29 | @cindex SPARC options | |
30 | @cindex architectures, SPARC | |
31 | @cindex SPARC architectures | |
f04d18b7 | 32 | The SPARC chip family includes several successive versions, using the same |
252b5132 | 33 | core instruction set, but including a few additional instructions at |
f04d18b7 | 34 | each version. There are exceptions to this however. For details on what |
252b5132 RH |
35 | instructions each variant supports, please see the chip's architecture |
36 | reference manual. | |
37 | ||
38 | By default, @code{@value{AS}} assumes the core instruction set (SPARC | |
39 | v6), but ``bumps'' the architecture level as needed: it switches to | |
40 | successively higher architectures as it encounters instructions that | |
41 | only exist in the higher levels. | |
42 | ||
43 | If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump | |
f04d18b7 | 44 | past sparclite by default, an option must be passed to enable the |
252b5132 RH |
45 | v9 instructions. |
46 | ||
47 | GAS treats sparclite as being compatible with v8, unless an architecture | |
48 | is explicitly requested. SPARC v9 is always incompatible with sparclite. | |
49 | ||
50 | @c The order here is the same as the order of enum sparc_opcode_arch_val | |
51 | @c to give the user a sense of the order of the "bumping". | |
52 | ||
53 | @table @code | |
54 | @kindex -Av6 | |
4bafe00e | 55 | @kindex -Av7 |
252b5132 RH |
56 | @kindex -Av8 |
57 | @kindex -Asparclet | |
58 | @kindex -Asparclite | |
59 | @kindex -Av9 | |
60 | @kindex -Av9a | |
4bafe00e DM |
61 | @kindex -Av9b |
62 | @kindex -Av9c | |
63 | @kindex -Av9d | |
64 | @kindex -Av9v | |
65 | @kindex -Asparc | |
66 | @kindex -Asparcvis | |
67 | @kindex -Asparcvis2 | |
68 | @kindex -Asparcfmaf | |
69 | @kindex -Asparcima | |
70 | @kindex -Asparcvis3 | |
71 | @kindex -Asparcvis3r | |
252b5132 | 72 | @item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite |
4bafe00e DM |
73 | @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv |
74 | @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v | |
75 | @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima | |
76 | @itemx -Asparcvis3 | -Asparcvis3r | |
252b5132 RH |
77 | Use one of the @samp{-A} options to select one of the SPARC |
78 | architectures explicitly. If you select an architecture explicitly, | |
79 | @code{@value{AS}} reports a fatal error if it encounters an instruction | |
80 | or feature requiring an incompatible or higher level. | |
81 | ||
4bafe00e DM |
82 | @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc}, |
83 | @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment. | |
252b5132 | 84 | |
4bafe00e DM |
85 | @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and |
86 | @samp{-Av9v} select a 64 bit environment and are not available unless GAS | |
87 | is explicitly configured with 64 bit environment support. | |
252b5132 RH |
88 | |
89 | @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with | |
4bafe00e | 90 | UltraSPARC VIS 1.0 extensions. |
252b5132 | 91 | |
4bafe00e DM |
92 | @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions, |
93 | as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}. | |
94 | ||
95 | @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions, | |
96 | as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}. | |
97 | ||
98 | @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused | |
99 | multiply-add, VIS 3.0, and HPC extension instructions, as well as the | |
100 | instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}. | |
101 | ||
102 | @samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional | |
103 | memory, floating point unfused multiply-add, integer multiply-add, and | |
104 | cache sparing store instructions, as well as the instructions enabled | |
105 | by @samp{-Av8plusd} and @samp{-Av9d}. | |
106 | ||
107 | @samp{-Asparc} specifies a v9 environment. It is equivalent to | |
108 | @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise. | |
109 | ||
110 | @samp{-Asparcvis} specifies a v9a environment. It is equivalent to | |
111 | @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise. | |
112 | ||
113 | @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to | |
114 | @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise. | |
115 | ||
116 | @samp{-Asparcfmaf} specifies a v9b environment with the floating point | |
117 | fused multiply-add instructions enabled. | |
118 | ||
119 | @samp{-Asparcima} specifies a v9b environment with the integer | |
120 | multiply-add instructions enabled. | |
121 | ||
122 | @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0, | |
123 | HPC , and floating point fused multiply-add instructions enabled. | |
124 | ||
125 | @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, | |
126 | HPC, transactional memory, random, and floating point unfused multiply-add | |
127 | instructions enabled. | |
128 | ||
129 | @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc | |
130 | @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a | |
131 | @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v | |
132 | @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2 | |
133 | @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3 | |
134 | @itemx -xarch=sparcvis3r | |
f04d18b7 | 135 | For compatibility with the SunOS v9 assembler. These options are |
4bafe00e DM |
136 | equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, |
137 | -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis, | |
138 | -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r, | |
139 | respectively. | |
252b5132 RH |
140 | |
141 | @item -bump | |
142 | Warn whenever it is necessary to switch to another level. | |
143 | If an architecture level is explicitly requested, GAS will not issue | |
144 | warnings until that level is reached, and will then bump the level | |
145 | as required (except between incompatible levels). | |
146 | ||
147 | @item -32 | -64 | |
148 | Select the word size, either 32 bits or 64 bits. | |
149 | These options are only available with the ELF object file format, | |
150 | and require that the necessary BFD support has been included. | |
151 | @end table | |
152 | ||
153 | @node Sparc-Aligned-Data | |
154 | @section Enforcing aligned data | |
155 | ||
156 | @cindex data alignment on SPARC | |
157 | @cindex SPARC data alignment | |
158 | SPARC GAS normally permits data to be misaligned. For example, it | |
159 | permits the @code{.long} pseudo-op to be used on a byte boundary. | |
f04d18b7 DM |
160 | However, the native SunOS assemblers issue an error when they see |
161 | misaligned data. | |
252b5132 RH |
162 | |
163 | @kindex --enforce-aligned-data | |
164 | You can use the @code{--enforce-aligned-data} option to make SPARC GAS | |
f04d18b7 | 165 | also issue an error about misaligned data, just as the SunOS |
252b5132 RH |
166 | assemblers do. |
167 | ||
168 | The @code{--enforce-aligned-data} option is not the default because gcc | |
169 | issues misaligned data pseudo-ops when it initializes certain packed | |
170 | data structures (structures defined using the @code{packed} attribute). | |
171 | You may have to assemble with GAS in order to initialize packed data | |
172 | structures in your own code. | |
173 | ||
c15295d5 DM |
174 | @cindex SPARC syntax |
175 | @cindex syntax, SPARC | |
176 | @node Sparc-Syntax | |
177 | @section Sparc Syntax | |
178 | The assembler syntax closely follows The Sparc Architecture Manual, | |
179 | versions 8 and 9, as well as most extensions defined by Sun | |
180 | for their UltraSPARC and Niagara line of processors. | |
181 | ||
182 | @menu | |
183 | * Sparc-Chars:: Special Characters | |
184 | * Sparc-Regs:: Register Names | |
1a6b486f | 185 | * Sparc-Constants:: Constant Names |
c15295d5 | 186 | * Sparc-Relocs:: Relocations |
f04d18b7 | 187 | * Sparc-Size-Translations:: Size Translations |
c15295d5 DM |
188 | @end menu |
189 | ||
190 | @node Sparc-Chars | |
191 | @subsection Special Characters | |
192 | ||
193 | @cindex line comment character, Sparc | |
194 | @cindex Sparc line comment character | |
7c31ae13 NC |
195 | A @samp{!} character appearing anywhere on a line indicates the start |
196 | of a comment that extends to the end of that line. | |
197 | ||
198 | If a @samp{#} appears as the first character of a line then the whole | |
199 | line is treated as a comment, but in this case the line could also be | |
200 | a logical line number directive (@pxref{Comments}) or a preprocessor | |
201 | control command (@pxref{Preprocessing}). | |
c15295d5 DM |
202 | |
203 | @cindex line separator, Sparc | |
204 | @cindex statement separator, Sparc | |
205 | @cindex Sparc line separator | |
206 | @samp{;} can be used instead of a newline to separate statements. | |
207 | ||
208 | @node Sparc-Regs | |
209 | @subsection Register Names | |
210 | @cindex Sparc registers | |
211 | @cindex register names, Sparc | |
212 | ||
213 | The Sparc integer register file is broken down into global, | |
214 | outgoing, local, and incoming. | |
215 | ||
216 | @itemize @bullet | |
217 | @item | |
218 | The 8 global registers are referred to as @samp{%g@var{n}}. | |
219 | ||
220 | @item | |
221 | The 8 outgoing registers are referred to as @samp{%o@var{n}}. | |
222 | ||
223 | @item | |
224 | The 8 local registers are referred to as @samp{%l@var{n}}. | |
225 | ||
226 | @item | |
227 | The 8 incoming registers are referred to as @samp{%i@var{n}}. | |
228 | ||
229 | @item | |
230 | The frame pointer register @samp{%i6} can be referenced using | |
231 | the alias @samp{%fp}. | |
232 | ||
233 | @item | |
234 | The stack pointer register @samp{%o6} can be referenced using | |
235 | the alias @samp{%sp}. | |
236 | @end itemize | |
237 | ||
238 | Floating point registers are simply referred to as @samp{%f@var{n}}. | |
239 | When assembling for pre-V9, only 32 floating point registers | |
240 | are available. For V9 and later there are 64, but there are | |
241 | restrictions when referencing the upper 32 registers. They | |
242 | can only be accessed as double or quad, and thus only even | |
243 | or quad numbered accesses are allowed. For example, @samp{%f34} | |
244 | is a legal floating point register, but @samp{%f35} is not. | |
245 | ||
246 | Certain V9 instructions allow access to ancillary state registers. | |
247 | Most simply they can be referred to as @samp{%asr@var{n}} where | |
f04d18b7 | 248 | @var{n} can be from 16 to 31. However, there are some aliases |
c15295d5 DM |
249 | defined to reference ASR registers defined for various UltraSPARC |
250 | processors: | |
251 | ||
252 | @itemize @bullet | |
253 | @item | |
254 | The tick compare register is referred to as @samp{%tick_cmpr}. | |
255 | ||
256 | @item | |
1a6b486f DM |
257 | The system tick register is referred to as @samp{%stick}. An alias, |
258 | @samp{%sys_tick}, exists but is deprecated and should not be used | |
259 | by new software. | |
c15295d5 DM |
260 | |
261 | @item | |
1a6b486f DM |
262 | The system tick compare register is referred to as @samp{%stick_cmpr}. |
263 | An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should | |
264 | not be used by new software. | |
c15295d5 DM |
265 | |
266 | @item | |
267 | The software interrupt register is referred to as @samp{%softint}. | |
268 | ||
269 | @item | |
270 | The set software interrupt register is referred to as @samp{%set_softint}. | |
f04d18b7 | 271 | The mnemonic @samp{%softint_set} is provided as an alias. |
c15295d5 DM |
272 | |
273 | @item | |
274 | The clear software interrupt register is referred to as | |
f04d18b7 DM |
275 | @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided |
276 | as an alias. | |
c15295d5 DM |
277 | |
278 | @item | |
279 | The performance instrumentation counters register is referred to as | |
280 | @samp{%pic}. | |
281 | ||
282 | @item | |
283 | The performance control register is referred to as @samp{%pcr}. | |
284 | ||
285 | @item | |
286 | The graphics status register is referred to as @samp{%gsr}. | |
287 | ||
288 | @item | |
f04d18b7 | 289 | The V9 dispatch control register is referred to as @samp{%dcr}. |
c15295d5 DM |
290 | @end itemize |
291 | ||
292 | Various V9 branch and conditional move instructions allow | |
293 | specification of which set of integer condition codes to | |
294 | test. These are referred to as @samp{%xcc} and @samp{%icc}. | |
295 | ||
296 | In V9, there are 4 sets of floating point condition codes | |
297 | which are referred to as @samp{%fcc@var{n}}. | |
298 | ||
299 | Several special privileged and non-privileged registers | |
300 | exist: | |
301 | ||
302 | @itemize @bullet | |
303 | @item | |
304 | The V9 address space identifier register is referred to as @samp{%asi}. | |
305 | ||
306 | @item | |
307 | The V9 restorable windows register is referred to as @samp{%canrestore}. | |
308 | ||
309 | @item | |
310 | The V9 savable windows register is referred to as @samp{%cansave}. | |
311 | ||
312 | @item | |
313 | The V9 clean windows register is referred to as @samp{%cleanwin}. | |
314 | ||
315 | @item | |
316 | The V9 current window pointer register is referred to as @samp{%cwp}. | |
317 | ||
318 | @item | |
319 | The floating-point queue register is referred to as @samp{%fq}. | |
320 | ||
321 | @item | |
f04d18b7 | 322 | The V8 co-processor queue register is referred to as @samp{%cq}. |
c15295d5 DM |
323 | |
324 | @item | |
325 | The floating point status register is referred to as @samp{%fsr}. | |
326 | ||
327 | @item | |
328 | The other windows register is referred to as @samp{%otherwin}. | |
329 | ||
330 | @item | |
331 | The V9 program counter register is referred to as @samp{%pc}. | |
332 | ||
333 | @item | |
334 | The V9 next program counter register is referred to as @samp{%npc}. | |
335 | ||
336 | @item | |
337 | The V9 processor interrupt level register is referred to as @samp{%pil}. | |
338 | ||
339 | @item | |
340 | The V9 processor state register is referred to as @samp{%pstate}. | |
341 | ||
342 | @item | |
343 | The trap base address register is referred to as @samp{%tba}. | |
344 | ||
345 | @item | |
346 | The V9 tick register is referred to as @samp{%tick}. | |
347 | ||
348 | @item | |
349 | The V9 trap level is referred to as @samp{%tl}. | |
350 | ||
351 | @item | |
352 | The V9 trap program counter is referred to as @samp{%tpc}. | |
353 | ||
354 | @item | |
355 | The V9 trap next program counter is referred to as @samp{%tnpc}. | |
356 | ||
357 | @item | |
358 | The V9 trap state is referred to as @samp{%tstate}. | |
359 | ||
360 | @item | |
361 | The V9 trap type is referred to as @samp{%tt}. | |
362 | ||
363 | @item | |
364 | The V9 condition codes is referred to as @samp{%ccr}. | |
365 | ||
366 | @item | |
367 | The V9 floating-point registers state is referred to as @samp{%fprs}. | |
368 | ||
369 | @item | |
370 | The V9 version register is referred to as @samp{%ver}. | |
371 | ||
372 | @item | |
373 | The V9 window state register is referred to as @samp{%wstate}. | |
374 | ||
375 | @item | |
376 | The Y register is referred to as @samp{%y}. | |
377 | ||
378 | @item | |
379 | The V8 window invalid mask register is referred to as @samp{%wim}. | |
380 | ||
381 | @item | |
382 | The V8 processor state register is referred to as @samp{%psr}. | |
383 | ||
384 | @item | |
f04d18b7 | 385 | The V9 global register level register is referred to as @samp{%gl}. |
c15295d5 DM |
386 | @end itemize |
387 | ||
388 | Several special register names exist for hypervisor mode code: | |
389 | ||
390 | @itemize @bullet | |
391 | @item | |
392 | The hyperprivileged processor state register is referred to as | |
393 | @samp{%hpstate}. | |
394 | ||
395 | @item | |
396 | The hyperprivileged trap state register is referred to as @samp{%htstate}. | |
397 | ||
398 | @item | |
399 | The hyperprivileged interrupt pending register is referred to as | |
400 | @samp{%hintp}. | |
401 | ||
402 | @item | |
403 | The hyperprivileged trap base address register is referred to as | |
404 | @samp{%htba}. | |
405 | ||
406 | @item | |
407 | The hyperprivileged implementation version register is referred | |
408 | to as @samp{%hver}. | |
409 | ||
410 | @item | |
411 | The hyperprivileged system tick compare register is referred | |
1a6b486f DM |
412 | to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick} |
413 | register, the normal @samp{%stick} is used. | |
414 | @end itemize | |
415 | ||
416 | @node Sparc-Constants | |
417 | @subsection Constants | |
418 | @cindex Sparc constants | |
419 | @cindex constants, Sparc | |
420 | ||
421 | Several Sparc instructions take an immediate operand field for | |
422 | which mnemonic names exist. Two such examples are @samp{membar} | |
423 | and @samp{prefetch}. Another example are the set of V9 | |
424 | memory access instruction that allow specification of an | |
425 | address space identifier. | |
426 | ||
427 | The @samp{membar} instruction specifies a memory barrier that is | |
428 | the defined by the operand which is a bitmask. The supported | |
429 | mask mnemonics are: | |
430 | ||
431 | @itemize @bullet | |
432 | @item | |
433 | @samp{#Sync} requests that all operations (including nonmemory | |
434 | reference operations) appearing prior to the @code{membar} must have | |
435 | been performed and the effects of any exceptions become visible before | |
436 | any instructions after the @code{membar} may be initiated. This | |
437 | corresponds to @code{membar} cmask field bit 2. | |
438 | ||
439 | @item | |
440 | @samp{#MemIssue} requests that all memory reference operations | |
441 | appearing prior to the @code{membar} must have been performed before | |
442 | any memory operation after the @code{membar} may be initiated. This | |
443 | corresponds to @code{membar} cmask field bit 1. | |
444 | ||
445 | @item | |
446 | @samp{#Lookaside} requests that a store appearing prior to the | |
447 | @code{membar} must complete before any load following the | |
448 | @code{membar} referencing the same address can be initiated. This | |
449 | corresponds to @code{membar} cmask field bit 0. | |
450 | ||
451 | @item | |
452 | @samp{#StoreStore} defines that the effects of all stores appearing | |
453 | prior to the @code{membar} instruction must be visible to all | |
454 | processors before the effect of any stores following the | |
455 | @code{membar}. Equivalent to the deprecated @code{stbar} instruction. | |
456 | This corresponds to @code{membar} mmask field bit 3. | |
457 | ||
458 | @item | |
459 | @samp{#LoadStore} defines all loads appearing prior to the | |
460 | @code{membar} instruction must have been performed before the effect | |
461 | of any stores following the @code{membar} is visible to any other | |
462 | processor. This corresponds to @code{membar} mmask field bit 2. | |
463 | ||
464 | @item | |
465 | @samp{#StoreLoad} defines that the effects of all stores appearing | |
466 | prior to the @code{membar} instruction must be visible to all | |
467 | processors before loads following the @code{membar} may be performed. | |
468 | This corresponds to @code{membar} mmask field bit 1. | |
469 | ||
470 | @item | |
471 | @samp{#LoadLoad} defines that all loads appearing prior to the | |
472 | @code{membar} instruction must have been performed before any loads | |
473 | following the @code{membar} may be performed. This corresponds to | |
474 | @code{membar} mmask field bit 0. | |
475 | ||
476 | @end itemize | |
477 | ||
478 | These values can be ored together, for example: | |
479 | ||
480 | @example | |
481 | membar #Sync | |
482 | membar #StoreLoad | #LoadLoad | |
483 | membar #StoreLoad | #StoreStore | |
484 | @end example | |
485 | ||
486 | The @code{prefetch} and @code{prefetcha} instructions take a prefetch | |
487 | function code. The following prefetch function code constant | |
488 | mnemonics are available: | |
489 | ||
490 | @itemize @bullet | |
491 | @item | |
492 | @samp{#n_reads} requests a prefetch for several reads, and corresponds | |
493 | to a prefetch function code of 0. | |
494 | ||
495 | @samp{#one_read} requests a prefetch for one read, and corresponds | |
496 | to a prefetch function code of 1. | |
497 | ||
498 | @samp{#n_writes} requests a prefetch for several writes (and possibly | |
499 | reads), and corresponds to a prefetch function code of 2. | |
500 | ||
501 | @samp{#one_write} requests a prefetch for one write, and corresponds | |
502 | to a prefetch function code of 3. | |
503 | ||
504 | @samp{#page} requests a prefetch page, and corresponds to a prefetch | |
505 | function code of 4. | |
506 | ||
507 | @samp{#invalidate} requests a prefetch invalidate, and corresponds to | |
508 | a prefetch function code of 16. | |
509 | ||
510 | @samp{#unified} requests a prefetch to the nearest unified cache, and | |
511 | corresponds to a prefetch function code of 17. | |
512 | ||
513 | @samp{#n_reads_strong} requests a strong prefetch for several reads, | |
514 | and corresponds to a prefetch function code of 20. | |
515 | ||
516 | @samp{#one_read_strong} requests a strong prefetch for one read, | |
517 | and corresponds to a prefetch function code of 21. | |
518 | ||
519 | @samp{#n_writes_strong} requests a strong prefetch for several writes, | |
520 | and corresponds to a prefetch function code of 22. | |
521 | ||
522 | @samp{#one_write_strong} requests a strong prefetch for one write, | |
523 | and corresponds to a prefetch function code of 23. | |
524 | ||
525 | Onle one prefetch code may be specified. Here are some examples: | |
526 | ||
527 | @example | |
528 | prefetch [%l0 + %l2], #one_read | |
529 | prefetch [%g2 + 8], #n_writes | |
530 | prefetcha [%g1] 0x8, #unified | |
531 | prefetcha [%o0 + 0x10] %asi, #n_reads | |
532 | @end example | |
533 | ||
534 | The actual behavior of a given prefetch function code is processor | |
535 | specific. If a processor does not implement a given prefetch | |
536 | function code, it will treat the prefetch instruction as a nop. | |
537 | ||
538 | For instructions that accept an immediate address space identifier, | |
539 | @code{@value{AS}} provides many mnemonics corresponding to | |
540 | V9 defined as well as UltraSPARC and Niagara extended values. | |
541 | For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}. | |
542 | See the V9 and processor specific manuals for details. | |
543 | ||
c15295d5 DM |
544 | @end itemize |
545 | ||
546 | @node Sparc-Relocs | |
547 | @subsection Relocations | |
548 | @cindex Sparc relocations | |
549 | @cindex relocations, Sparc | |
550 | ||
551 | ELF relocations are available as defined in the 32-bit and 64-bit | |
552 | Sparc ELF specifications. | |
553 | ||
554 | @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10} | |
555 | is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is | |
556 | obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained | |
557 | using @samp{%lox}. For example: | |
558 | ||
559 | @example | |
560 | sethi %hi(symbol), %g1 | |
561 | or %g1, %lo(symbol), %g1 | |
562 | ||
563 | sethi %hix(symbol), %g1 | |
564 | xor %g1, %lox(symbol), %g1 | |
565 | @end example | |
566 | ||
567 | These ``high'' mnemonics extract bits 31:10 of their operand, | |
568 | and the ``low'' mnemonics extract bits 9:0 of their operand. | |
569 | ||
570 | V9 code model relocations can be requested as follows: | |
571 | ||
572 | @itemize @bullet | |
573 | @item | |
574 | @code{R_SPARC_HH22} is requested using @samp{%hh}. It can | |
575 | also be generated using @samp{%uhi}. | |
576 | @item | |
577 | @code{R_SPARC_HM10} is requested using @samp{%hm}. It can | |
578 | also be generated using @samp{%ulo}. | |
579 | @item | |
580 | @code{R_SPARC_LM22} is requested using @samp{%lm}. | |
581 | ||
582 | @item | |
583 | @code{R_SPARC_H44} is requested using @samp{%h44}. | |
584 | @item | |
585 | @code{R_SPARC_M44} is requested using @samp{%m44}. | |
586 | @item | |
587 | @code{R_SPARC_L44} is requested using @samp{%l44}. | |
588 | @end itemize | |
589 | ||
590 | The PC relative relocation @code{R_SPARC_PC22} can be obtained by | |
591 | enclosing an operand inside of @samp{%pc22}. Likewise, the | |
592 | @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}. | |
593 | These are mostly used when assembling PIC code. For example, the | |
594 | standard PIC sequence on Sparc to get the base of the global offset | |
595 | table, PC relative, into a register, can be performed as: | |
596 | ||
597 | @example | |
598 | sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 | |
599 | add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 | |
600 | @end example | |
601 | ||
602 | Several relocations exist to allow the link editor to potentially | |
603 | optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22} | |
604 | relocation can obtained by enclosing an operand inside of | |
605 | @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10} | |
606 | relocation can obtained by enclosing an operand inside of | |
607 | @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be | |
608 | obtained by enclosing an operand inside of @samp{%gdop}. | |
609 | For example, assuming the GOT base is in register @code{%l7}: | |
610 | ||
611 | @example | |
612 | sethi %gdop_hix22(symbol), %l1 | |
613 | xor %l1, %gdop_lox10(symbol), %l1 | |
614 | ld [%l7 + %l1], %l2, %gdop(symbol) | |
615 | @end example | |
616 | ||
617 | There are many relocations that can be requested for access to | |
618 | thread local storage variables. All of the Sparc TLS mnemonics | |
619 | are supported: | |
620 | ||
621 | @itemize @bullet | |
622 | @item | |
623 | @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}. | |
624 | @item | |
625 | @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}. | |
626 | @item | |
627 | @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}. | |
628 | @item | |
629 | @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}. | |
630 | ||
631 | @item | |
632 | @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}. | |
633 | @item | |
634 | @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}. | |
635 | @item | |
636 | @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}. | |
637 | @item | |
638 | @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}. | |
639 | ||
640 | @item | |
641 | @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}. | |
642 | @item | |
643 | @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}. | |
644 | @item | |
645 | @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}. | |
646 | ||
647 | @item | |
648 | @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}. | |
649 | @item | |
650 | @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}. | |
651 | @item | |
652 | @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}. | |
653 | @item | |
654 | @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}. | |
655 | @item | |
656 | @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}. | |
657 | ||
658 | @item | |
659 | @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}. | |
660 | @item | |
661 | @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}. | |
662 | @end itemize | |
663 | ||
664 | Here are some example TLS model sequences. | |
665 | ||
666 | First, General Dynamic: | |
667 | ||
668 | @example | |
669 | sethi %tgd_hi22(symbol), %l1 | |
670 | add %l1, %tgd_lo10(symbol), %l1 | |
671 | add %l7, %l1, %o0, %tgd_add(symbol) | |
672 | call __tls_get_addr, %tgd_call(symbol) | |
673 | nop | |
674 | @end example | |
675 | ||
676 | Local Dynamic: | |
677 | ||
678 | @example | |
679 | sethi %tldm_hi22(symbol), %l1 | |
680 | add %l1, %tldm_lo10(symbol), %l1 | |
681 | add %l7, %l1, %o0, %tldm_add(symbol) | |
682 | call __tls_get_addr, %tldm_call(symbol) | |
683 | nop | |
684 | ||
685 | sethi %tldo_hix22(symbol), %l1 | |
686 | xor %l1, %tldo_lox10(symbol), %l1 | |
687 | add %o0, %l1, %l1, %tldo_add(symbol) | |
688 | @end example | |
689 | ||
690 | Initial Exec: | |
691 | ||
692 | @example | |
693 | sethi %tie_hi22(symbol), %l1 | |
694 | add %l1, %tie_lo10(symbol), %l1 | |
695 | ld [%l7 + %l1], %o0, %tie_ld(symbol) | |
696 | add %g7, %o0, %o0, %tie_add(symbol) | |
697 | ||
698 | sethi %tie_hi22(symbol), %l1 | |
699 | add %l1, %tie_lo10(symbol), %l1 | |
700 | ldx [%l7 + %l1], %o0, %tie_ldx(symbol) | |
701 | add %g7, %o0, %o0, %tie_add(symbol) | |
702 | @end example | |
703 | ||
704 | And finally, Local Exec: | |
705 | ||
706 | @example | |
707 | sethi %tle_hix22(symbol), %l1 | |
708 | add %l1, %tle_lox10(symbol), %l1 | |
709 | add %g7, %l1, %l1 | |
710 | @end example | |
711 | ||
712 | When assembling for 64-bit, and a secondary constant addend is | |
713 | specified in an address expression that would normally generate | |
714 | an @code{R_SPARC_LO10} relocation, the assembler will emit an | |
715 | @code{R_SPARC_OLO10} instead. | |
252b5132 | 716 | |
f04d18b7 DM |
717 | @node Sparc-Size-Translations |
718 | @subsection Size Translations | |
719 | @cindex Sparc size translations | |
720 | @cindex size, translations, Sparc | |
721 | ||
722 | Often it is desirable to write code in an operand size agnostic | |
723 | manner. @code{@value{AS}} provides support for this via | |
724 | operand size opcode translations. Translations are supported | |
725 | for loads, stores, shifts, compare-and-swap atomics, and the | |
726 | @samp{clr} synthetic instruction. | |
727 | ||
728 | If generating 32-bit code, @code{@value{AS}} will generate the | |
729 | 32-bit opcode. Whereas if 64-bit code is being generated, | |
730 | the 64-bit opcode will be emitted. For example @code{ldn} | |
731 | will be transformed into @code{ld} for 32-bit code and | |
732 | @code{ldx} for 64-bit code. | |
733 | ||
734 | Here is an example meant to demonstrate all the supported | |
735 | opcode translations: | |
736 | ||
737 | @example | |
738 | ldn [%o0], %o1 | |
739 | ldna [%o0] %asi, %o2 | |
740 | stn %o1, [%o0] | |
741 | stna %o2, [%o0] %asi | |
742 | slln %o3, 3, %o3 | |
743 | srln %o4, 8, %o4 | |
744 | sran %o5, 12, %o5 | |
745 | casn [%o0], %o1, %o2 | |
746 | casna [%o0] %asi, %o1, %o2 | |
747 | clrn %g1 | |
748 | @end example | |
749 | ||
750 | In 32-bit mode @code{@value{AS}} will emit: | |
751 | ||
752 | @example | |
753 | ld [%o0], %o1 | |
754 | lda [%o0] %asi, %o2 | |
755 | st %o1, [%o0] | |
756 | sta %o2, [%o0] %asi | |
757 | sll %o3, 3, %o3 | |
758 | srl %o4, 8, %o4 | |
759 | sra %o5, 12, %o5 | |
760 | cas [%o0], %o1, %o2 | |
761 | casa [%o0] %asi, %o1, %o2 | |
762 | clr %g1 | |
763 | @end example | |
764 | ||
765 | And in 64-bit mode @code{@value{AS}} will emit: | |
766 | ||
767 | @example | |
768 | ldx [%o0], %o1 | |
769 | ldxa [%o0] %asi, %o2 | |
770 | stx %o1, [%o0] | |
771 | stxa %o2, [%o0] %asi | |
772 | sllx %o3, 3, %o3 | |
773 | srlx %o4, 8, %o4 | |
774 | srax %o5, 12, %o5 | |
775 | casx [%o0], %o1, %o2 | |
776 | casxa [%o0] %asi, %o1, %o2 | |
777 | clrx %g1 | |
778 | @end example | |
779 | ||
780 | Finally, the @samp{.nword} translating directive is supported | |
781 | as well. It is documented in the section on Sparc machine | |
782 | directives. | |
783 | ||
252b5132 RH |
784 | @node Sparc-Float |
785 | @section Floating Point | |
786 | ||
787 | @cindex floating point, SPARC (@sc{ieee}) | |
788 | @cindex SPARC floating point (@sc{ieee}) | |
789 | The Sparc uses @sc{ieee} floating-point numbers. | |
790 | ||
791 | @node Sparc-Directives | |
792 | @section Sparc Machine Directives | |
793 | ||
794 | @cindex SPARC machine directives | |
795 | @cindex machine directives, SPARC | |
796 | The Sparc version of @code{@value{AS}} supports the following additional | |
797 | machine directives: | |
798 | ||
799 | @table @code | |
800 | @cindex @code{align} directive, SPARC | |
801 | @item .align | |
802 | This must be followed by the desired alignment in bytes. | |
803 | ||
804 | @cindex @code{common} directive, SPARC | |
805 | @item .common | |
806 | This must be followed by a symbol name, a positive number, and | |
807 | @code{"bss"}. This behaves somewhat like @code{.comm}, but the | |
808 | syntax is different. | |
809 | ||
810 | @cindex @code{half} directive, SPARC | |
811 | @item .half | |
812 | This is functionally identical to @code{.short}. | |
813 | ||
e06510e6 RH |
814 | @cindex @code{nword} directive, SPARC |
815 | @item .nword | |
816 | On the Sparc, the @code{.nword} directive produces native word sized value, | |
817 | ie. if assembling with -32 it is equivalent to @code{.word}, if assembling | |
818 | with -64 it is equivalent to @code{.xword}. | |
819 | ||
252b5132 RH |
820 | @cindex @code{proc} directive, SPARC |
821 | @item .proc | |
822 | This directive is ignored. Any text following it on the same | |
823 | line is also ignored. | |
824 | ||
e06510e6 RH |
825 | @cindex @code{register} directive, SPARC |
826 | @item .register | |
827 | This directive declares use of a global application or system register. | |
828 | It must be followed by a register name %g2, %g3, %g6 or %g7, comma and | |
6d8809aa | 829 | the symbol name for that register. If symbol name is @code{#scratch}, |
062b7c0c | 830 | it is a scratch register, if it is @code{#ignore}, it just suppresses any |
6d8809aa RH |
831 | errors about using undeclared global register, but does not emit any |
832 | information about it into the object file. This can be useful e.g. if you | |
833 | save the register before use and restore it after. | |
e06510e6 | 834 | |
252b5132 RH |
835 | @cindex @code{reserve} directive, SPARC |
836 | @item .reserve | |
837 | This must be followed by a symbol name, a positive number, and | |
838 | @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the | |
839 | syntax is different. | |
840 | ||
841 | @cindex @code{seg} directive, SPARC | |
842 | @item .seg | |
843 | This must be followed by @code{"text"}, @code{"data"}, or | |
844 | @code{"data1"}. It behaves like @code{.text}, @code{.data}, or | |
845 | @code{.data 1}. | |
846 | ||
847 | @cindex @code{skip} directive, SPARC | |
848 | @item .skip | |
849 | This is functionally identical to the @code{.space} directive. | |
850 | ||
851 | @cindex @code{word} directive, SPARC | |
852 | @item .word | |
853 | On the Sparc, the @code{.word} directive produces 32 bit values, | |
854 | instead of the 16 bit values it produces on many other machines. | |
855 | ||
856 | @cindex @code{xword} directive, SPARC | |
857 | @item .xword | |
858 | On the Sparc V9 processor, the @code{.xword} directive produces | |
859 | 64 bit values. | |
860 | @end table |