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aa820537 | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008 |
f7e42eb4 | 2 | @c Free Software Foundation, Inc. |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @ifset GENERIC | |
6 | @page | |
7 | @node Sparc-Dependent | |
8 | @chapter SPARC Dependent Features | |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter SPARC Dependent Features | |
13 | @end ifclear | |
14 | ||
15 | @cindex SPARC support | |
16 | @menu | |
17 | * Sparc-Opts:: Options | |
18 | * Sparc-Aligned-Data:: Option to enforce aligned data | |
c15295d5 | 19 | * Sparc-Syntax:: Syntax |
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20 | * Sparc-Float:: Floating Point |
21 | * Sparc-Directives:: Sparc Machine Directives | |
22 | @end menu | |
23 | ||
24 | @node Sparc-Opts | |
25 | @section Options | |
26 | ||
27 | @cindex options for SPARC | |
28 | @cindex SPARC options | |
29 | @cindex architectures, SPARC | |
30 | @cindex SPARC architectures | |
f04d18b7 | 31 | The SPARC chip family includes several successive versions, using the same |
252b5132 | 32 | core instruction set, but including a few additional instructions at |
f04d18b7 | 33 | each version. There are exceptions to this however. For details on what |
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34 | instructions each variant supports, please see the chip's architecture |
35 | reference manual. | |
36 | ||
37 | By default, @code{@value{AS}} assumes the core instruction set (SPARC | |
38 | v6), but ``bumps'' the architecture level as needed: it switches to | |
39 | successively higher architectures as it encounters instructions that | |
40 | only exist in the higher levels. | |
41 | ||
42 | If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump | |
f04d18b7 | 43 | past sparclite by default, an option must be passed to enable the |
252b5132 RH |
44 | v9 instructions. |
45 | ||
46 | GAS treats sparclite as being compatible with v8, unless an architecture | |
47 | is explicitly requested. SPARC v9 is always incompatible with sparclite. | |
48 | ||
49 | @c The order here is the same as the order of enum sparc_opcode_arch_val | |
50 | @c to give the user a sense of the order of the "bumping". | |
51 | ||
52 | @table @code | |
53 | @kindex -Av6 | |
54 | @kindex Av7 | |
55 | @kindex -Av8 | |
56 | @kindex -Asparclet | |
57 | @kindex -Asparclite | |
58 | @kindex -Av9 | |
59 | @kindex -Av9a | |
60 | @item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite | |
61 | @itemx -Av8plus | -Av8plusa | -Av9 | -Av9a | |
62 | Use one of the @samp{-A} options to select one of the SPARC | |
63 | architectures explicitly. If you select an architecture explicitly, | |
64 | @code{@value{AS}} reports a fatal error if it encounters an instruction | |
65 | or feature requiring an incompatible or higher level. | |
66 | ||
67 | @samp{-Av8plus} and @samp{-Av8plusa} select a 32 bit environment. | |
68 | ||
69 | @samp{-Av9} and @samp{-Av9a} select a 64 bit environment and are not | |
70 | available unless GAS is explicitly configured with 64 bit environment | |
71 | support. | |
72 | ||
73 | @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with | |
74 | UltraSPARC extensions. | |
75 | ||
76 | @item -xarch=v8plus | -xarch=v8plusa | |
f04d18b7 | 77 | For compatibility with the SunOS v9 assembler. These options are |
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78 | equivalent to -Av8plus and -Av8plusa, respectively. |
79 | ||
80 | @item -bump | |
81 | Warn whenever it is necessary to switch to another level. | |
82 | If an architecture level is explicitly requested, GAS will not issue | |
83 | warnings until that level is reached, and will then bump the level | |
84 | as required (except between incompatible levels). | |
85 | ||
86 | @item -32 | -64 | |
87 | Select the word size, either 32 bits or 64 bits. | |
88 | These options are only available with the ELF object file format, | |
89 | and require that the necessary BFD support has been included. | |
90 | @end table | |
91 | ||
92 | @node Sparc-Aligned-Data | |
93 | @section Enforcing aligned data | |
94 | ||
95 | @cindex data alignment on SPARC | |
96 | @cindex SPARC data alignment | |
97 | SPARC GAS normally permits data to be misaligned. For example, it | |
98 | permits the @code{.long} pseudo-op to be used on a byte boundary. | |
f04d18b7 DM |
99 | However, the native SunOS assemblers issue an error when they see |
100 | misaligned data. | |
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101 | |
102 | @kindex --enforce-aligned-data | |
103 | You can use the @code{--enforce-aligned-data} option to make SPARC GAS | |
f04d18b7 | 104 | also issue an error about misaligned data, just as the SunOS |
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105 | assemblers do. |
106 | ||
107 | The @code{--enforce-aligned-data} option is not the default because gcc | |
108 | issues misaligned data pseudo-ops when it initializes certain packed | |
109 | data structures (structures defined using the @code{packed} attribute). | |
110 | You may have to assemble with GAS in order to initialize packed data | |
111 | structures in your own code. | |
112 | ||
c15295d5 DM |
113 | @cindex SPARC syntax |
114 | @cindex syntax, SPARC | |
115 | @node Sparc-Syntax | |
116 | @section Sparc Syntax | |
117 | The assembler syntax closely follows The Sparc Architecture Manual, | |
118 | versions 8 and 9, as well as most extensions defined by Sun | |
119 | for their UltraSPARC and Niagara line of processors. | |
120 | ||
121 | @menu | |
122 | * Sparc-Chars:: Special Characters | |
123 | * Sparc-Regs:: Register Names | |
1a6b486f | 124 | * Sparc-Constants:: Constant Names |
c15295d5 | 125 | * Sparc-Relocs:: Relocations |
f04d18b7 | 126 | * Sparc-Size-Translations:: Size Translations |
c15295d5 DM |
127 | @end menu |
128 | ||
129 | @node Sparc-Chars | |
130 | @subsection Special Characters | |
131 | ||
132 | @cindex line comment character, Sparc | |
133 | @cindex Sparc line comment character | |
134 | @samp{#} is the line comment character. | |
135 | ||
136 | @cindex line separator, Sparc | |
137 | @cindex statement separator, Sparc | |
138 | @cindex Sparc line separator | |
139 | @samp{;} can be used instead of a newline to separate statements. | |
140 | ||
141 | @node Sparc-Regs | |
142 | @subsection Register Names | |
143 | @cindex Sparc registers | |
144 | @cindex register names, Sparc | |
145 | ||
146 | The Sparc integer register file is broken down into global, | |
147 | outgoing, local, and incoming. | |
148 | ||
149 | @itemize @bullet | |
150 | @item | |
151 | The 8 global registers are referred to as @samp{%g@var{n}}. | |
152 | ||
153 | @item | |
154 | The 8 outgoing registers are referred to as @samp{%o@var{n}}. | |
155 | ||
156 | @item | |
157 | The 8 local registers are referred to as @samp{%l@var{n}}. | |
158 | ||
159 | @item | |
160 | The 8 incoming registers are referred to as @samp{%i@var{n}}. | |
161 | ||
162 | @item | |
163 | The frame pointer register @samp{%i6} can be referenced using | |
164 | the alias @samp{%fp}. | |
165 | ||
166 | @item | |
167 | The stack pointer register @samp{%o6} can be referenced using | |
168 | the alias @samp{%sp}. | |
169 | @end itemize | |
170 | ||
171 | Floating point registers are simply referred to as @samp{%f@var{n}}. | |
172 | When assembling for pre-V9, only 32 floating point registers | |
173 | are available. For V9 and later there are 64, but there are | |
174 | restrictions when referencing the upper 32 registers. They | |
175 | can only be accessed as double or quad, and thus only even | |
176 | or quad numbered accesses are allowed. For example, @samp{%f34} | |
177 | is a legal floating point register, but @samp{%f35} is not. | |
178 | ||
179 | Certain V9 instructions allow access to ancillary state registers. | |
180 | Most simply they can be referred to as @samp{%asr@var{n}} where | |
f04d18b7 | 181 | @var{n} can be from 16 to 31. However, there are some aliases |
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182 | defined to reference ASR registers defined for various UltraSPARC |
183 | processors: | |
184 | ||
185 | @itemize @bullet | |
186 | @item | |
187 | The tick compare register is referred to as @samp{%tick_cmpr}. | |
188 | ||
189 | @item | |
1a6b486f DM |
190 | The system tick register is referred to as @samp{%stick}. An alias, |
191 | @samp{%sys_tick}, exists but is deprecated and should not be used | |
192 | by new software. | |
c15295d5 DM |
193 | |
194 | @item | |
1a6b486f DM |
195 | The system tick compare register is referred to as @samp{%stick_cmpr}. |
196 | An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should | |
197 | not be used by new software. | |
c15295d5 DM |
198 | |
199 | @item | |
200 | The software interrupt register is referred to as @samp{%softint}. | |
201 | ||
202 | @item | |
203 | The set software interrupt register is referred to as @samp{%set_softint}. | |
f04d18b7 | 204 | The mnemonic @samp{%softint_set} is provided as an alias. |
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205 | |
206 | @item | |
207 | The clear software interrupt register is referred to as | |
f04d18b7 DM |
208 | @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided |
209 | as an alias. | |
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210 | |
211 | @item | |
212 | The performance instrumentation counters register is referred to as | |
213 | @samp{%pic}. | |
214 | ||
215 | @item | |
216 | The performance control register is referred to as @samp{%pcr}. | |
217 | ||
218 | @item | |
219 | The graphics status register is referred to as @samp{%gsr}. | |
220 | ||
221 | @item | |
f04d18b7 | 222 | The V9 dispatch control register is referred to as @samp{%dcr}. |
c15295d5 DM |
223 | @end itemize |
224 | ||
225 | Various V9 branch and conditional move instructions allow | |
226 | specification of which set of integer condition codes to | |
227 | test. These are referred to as @samp{%xcc} and @samp{%icc}. | |
228 | ||
229 | In V9, there are 4 sets of floating point condition codes | |
230 | which are referred to as @samp{%fcc@var{n}}. | |
231 | ||
232 | Several special privileged and non-privileged registers | |
233 | exist: | |
234 | ||
235 | @itemize @bullet | |
236 | @item | |
237 | The V9 address space identifier register is referred to as @samp{%asi}. | |
238 | ||
239 | @item | |
240 | The V9 restorable windows register is referred to as @samp{%canrestore}. | |
241 | ||
242 | @item | |
243 | The V9 savable windows register is referred to as @samp{%cansave}. | |
244 | ||
245 | @item | |
246 | The V9 clean windows register is referred to as @samp{%cleanwin}. | |
247 | ||
248 | @item | |
249 | The V9 current window pointer register is referred to as @samp{%cwp}. | |
250 | ||
251 | @item | |
252 | The floating-point queue register is referred to as @samp{%fq}. | |
253 | ||
254 | @item | |
f04d18b7 | 255 | The V8 co-processor queue register is referred to as @samp{%cq}. |
c15295d5 DM |
256 | |
257 | @item | |
258 | The floating point status register is referred to as @samp{%fsr}. | |
259 | ||
260 | @item | |
261 | The other windows register is referred to as @samp{%otherwin}. | |
262 | ||
263 | @item | |
264 | The V9 program counter register is referred to as @samp{%pc}. | |
265 | ||
266 | @item | |
267 | The V9 next program counter register is referred to as @samp{%npc}. | |
268 | ||
269 | @item | |
270 | The V9 processor interrupt level register is referred to as @samp{%pil}. | |
271 | ||
272 | @item | |
273 | The V9 processor state register is referred to as @samp{%pstate}. | |
274 | ||
275 | @item | |
276 | The trap base address register is referred to as @samp{%tba}. | |
277 | ||
278 | @item | |
279 | The V9 tick register is referred to as @samp{%tick}. | |
280 | ||
281 | @item | |
282 | The V9 trap level is referred to as @samp{%tl}. | |
283 | ||
284 | @item | |
285 | The V9 trap program counter is referred to as @samp{%tpc}. | |
286 | ||
287 | @item | |
288 | The V9 trap next program counter is referred to as @samp{%tnpc}. | |
289 | ||
290 | @item | |
291 | The V9 trap state is referred to as @samp{%tstate}. | |
292 | ||
293 | @item | |
294 | The V9 trap type is referred to as @samp{%tt}. | |
295 | ||
296 | @item | |
297 | The V9 condition codes is referred to as @samp{%ccr}. | |
298 | ||
299 | @item | |
300 | The V9 floating-point registers state is referred to as @samp{%fprs}. | |
301 | ||
302 | @item | |
303 | The V9 version register is referred to as @samp{%ver}. | |
304 | ||
305 | @item | |
306 | The V9 window state register is referred to as @samp{%wstate}. | |
307 | ||
308 | @item | |
309 | The Y register is referred to as @samp{%y}. | |
310 | ||
311 | @item | |
312 | The V8 window invalid mask register is referred to as @samp{%wim}. | |
313 | ||
314 | @item | |
315 | The V8 processor state register is referred to as @samp{%psr}. | |
316 | ||
317 | @item | |
f04d18b7 | 318 | The V9 global register level register is referred to as @samp{%gl}. |
c15295d5 DM |
319 | @end itemize |
320 | ||
321 | Several special register names exist for hypervisor mode code: | |
322 | ||
323 | @itemize @bullet | |
324 | @item | |
325 | The hyperprivileged processor state register is referred to as | |
326 | @samp{%hpstate}. | |
327 | ||
328 | @item | |
329 | The hyperprivileged trap state register is referred to as @samp{%htstate}. | |
330 | ||
331 | @item | |
332 | The hyperprivileged interrupt pending register is referred to as | |
333 | @samp{%hintp}. | |
334 | ||
335 | @item | |
336 | The hyperprivileged trap base address register is referred to as | |
337 | @samp{%htba}. | |
338 | ||
339 | @item | |
340 | The hyperprivileged implementation version register is referred | |
341 | to as @samp{%hver}. | |
342 | ||
343 | @item | |
344 | The hyperprivileged system tick compare register is referred | |
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345 | to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick} |
346 | register, the normal @samp{%stick} is used. | |
347 | @end itemize | |
348 | ||
349 | @node Sparc-Constants | |
350 | @subsection Constants | |
351 | @cindex Sparc constants | |
352 | @cindex constants, Sparc | |
353 | ||
354 | Several Sparc instructions take an immediate operand field for | |
355 | which mnemonic names exist. Two such examples are @samp{membar} | |
356 | and @samp{prefetch}. Another example are the set of V9 | |
357 | memory access instruction that allow specification of an | |
358 | address space identifier. | |
359 | ||
360 | The @samp{membar} instruction specifies a memory barrier that is | |
361 | the defined by the operand which is a bitmask. The supported | |
362 | mask mnemonics are: | |
363 | ||
364 | @itemize @bullet | |
365 | @item | |
366 | @samp{#Sync} requests that all operations (including nonmemory | |
367 | reference operations) appearing prior to the @code{membar} must have | |
368 | been performed and the effects of any exceptions become visible before | |
369 | any instructions after the @code{membar} may be initiated. This | |
370 | corresponds to @code{membar} cmask field bit 2. | |
371 | ||
372 | @item | |
373 | @samp{#MemIssue} requests that all memory reference operations | |
374 | appearing prior to the @code{membar} must have been performed before | |
375 | any memory operation after the @code{membar} may be initiated. This | |
376 | corresponds to @code{membar} cmask field bit 1. | |
377 | ||
378 | @item | |
379 | @samp{#Lookaside} requests that a store appearing prior to the | |
380 | @code{membar} must complete before any load following the | |
381 | @code{membar} referencing the same address can be initiated. This | |
382 | corresponds to @code{membar} cmask field bit 0. | |
383 | ||
384 | @item | |
385 | @samp{#StoreStore} defines that the effects of all stores appearing | |
386 | prior to the @code{membar} instruction must be visible to all | |
387 | processors before the effect of any stores following the | |
388 | @code{membar}. Equivalent to the deprecated @code{stbar} instruction. | |
389 | This corresponds to @code{membar} mmask field bit 3. | |
390 | ||
391 | @item | |
392 | @samp{#LoadStore} defines all loads appearing prior to the | |
393 | @code{membar} instruction must have been performed before the effect | |
394 | of any stores following the @code{membar} is visible to any other | |
395 | processor. This corresponds to @code{membar} mmask field bit 2. | |
396 | ||
397 | @item | |
398 | @samp{#StoreLoad} defines that the effects of all stores appearing | |
399 | prior to the @code{membar} instruction must be visible to all | |
400 | processors before loads following the @code{membar} may be performed. | |
401 | This corresponds to @code{membar} mmask field bit 1. | |
402 | ||
403 | @item | |
404 | @samp{#LoadLoad} defines that all loads appearing prior to the | |
405 | @code{membar} instruction must have been performed before any loads | |
406 | following the @code{membar} may be performed. This corresponds to | |
407 | @code{membar} mmask field bit 0. | |
408 | ||
409 | @end itemize | |
410 | ||
411 | These values can be ored together, for example: | |
412 | ||
413 | @example | |
414 | membar #Sync | |
415 | membar #StoreLoad | #LoadLoad | |
416 | membar #StoreLoad | #StoreStore | |
417 | @end example | |
418 | ||
419 | The @code{prefetch} and @code{prefetcha} instructions take a prefetch | |
420 | function code. The following prefetch function code constant | |
421 | mnemonics are available: | |
422 | ||
423 | @itemize @bullet | |
424 | @item | |
425 | @samp{#n_reads} requests a prefetch for several reads, and corresponds | |
426 | to a prefetch function code of 0. | |
427 | ||
428 | @samp{#one_read} requests a prefetch for one read, and corresponds | |
429 | to a prefetch function code of 1. | |
430 | ||
431 | @samp{#n_writes} requests a prefetch for several writes (and possibly | |
432 | reads), and corresponds to a prefetch function code of 2. | |
433 | ||
434 | @samp{#one_write} requests a prefetch for one write, and corresponds | |
435 | to a prefetch function code of 3. | |
436 | ||
437 | @samp{#page} requests a prefetch page, and corresponds to a prefetch | |
438 | function code of 4. | |
439 | ||
440 | @samp{#invalidate} requests a prefetch invalidate, and corresponds to | |
441 | a prefetch function code of 16. | |
442 | ||
443 | @samp{#unified} requests a prefetch to the nearest unified cache, and | |
444 | corresponds to a prefetch function code of 17. | |
445 | ||
446 | @samp{#n_reads_strong} requests a strong prefetch for several reads, | |
447 | and corresponds to a prefetch function code of 20. | |
448 | ||
449 | @samp{#one_read_strong} requests a strong prefetch for one read, | |
450 | and corresponds to a prefetch function code of 21. | |
451 | ||
452 | @samp{#n_writes_strong} requests a strong prefetch for several writes, | |
453 | and corresponds to a prefetch function code of 22. | |
454 | ||
455 | @samp{#one_write_strong} requests a strong prefetch for one write, | |
456 | and corresponds to a prefetch function code of 23. | |
457 | ||
458 | Onle one prefetch code may be specified. Here are some examples: | |
459 | ||
460 | @example | |
461 | prefetch [%l0 + %l2], #one_read | |
462 | prefetch [%g2 + 8], #n_writes | |
463 | prefetcha [%g1] 0x8, #unified | |
464 | prefetcha [%o0 + 0x10] %asi, #n_reads | |
465 | @end example | |
466 | ||
467 | The actual behavior of a given prefetch function code is processor | |
468 | specific. If a processor does not implement a given prefetch | |
469 | function code, it will treat the prefetch instruction as a nop. | |
470 | ||
471 | For instructions that accept an immediate address space identifier, | |
472 | @code{@value{AS}} provides many mnemonics corresponding to | |
473 | V9 defined as well as UltraSPARC and Niagara extended values. | |
474 | For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}. | |
475 | See the V9 and processor specific manuals for details. | |
476 | ||
c15295d5 DM |
477 | @end itemize |
478 | ||
479 | @node Sparc-Relocs | |
480 | @subsection Relocations | |
481 | @cindex Sparc relocations | |
482 | @cindex relocations, Sparc | |
483 | ||
484 | ELF relocations are available as defined in the 32-bit and 64-bit | |
485 | Sparc ELF specifications. | |
486 | ||
487 | @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10} | |
488 | is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is | |
489 | obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained | |
490 | using @samp{%lox}. For example: | |
491 | ||
492 | @example | |
493 | sethi %hi(symbol), %g1 | |
494 | or %g1, %lo(symbol), %g1 | |
495 | ||
496 | sethi %hix(symbol), %g1 | |
497 | xor %g1, %lox(symbol), %g1 | |
498 | @end example | |
499 | ||
500 | These ``high'' mnemonics extract bits 31:10 of their operand, | |
501 | and the ``low'' mnemonics extract bits 9:0 of their operand. | |
502 | ||
503 | V9 code model relocations can be requested as follows: | |
504 | ||
505 | @itemize @bullet | |
506 | @item | |
507 | @code{R_SPARC_HH22} is requested using @samp{%hh}. It can | |
508 | also be generated using @samp{%uhi}. | |
509 | @item | |
510 | @code{R_SPARC_HM10} is requested using @samp{%hm}. It can | |
511 | also be generated using @samp{%ulo}. | |
512 | @item | |
513 | @code{R_SPARC_LM22} is requested using @samp{%lm}. | |
514 | ||
515 | @item | |
516 | @code{R_SPARC_H44} is requested using @samp{%h44}. | |
517 | @item | |
518 | @code{R_SPARC_M44} is requested using @samp{%m44}. | |
519 | @item | |
520 | @code{R_SPARC_L44} is requested using @samp{%l44}. | |
521 | @end itemize | |
522 | ||
523 | The PC relative relocation @code{R_SPARC_PC22} can be obtained by | |
524 | enclosing an operand inside of @samp{%pc22}. Likewise, the | |
525 | @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}. | |
526 | These are mostly used when assembling PIC code. For example, the | |
527 | standard PIC sequence on Sparc to get the base of the global offset | |
528 | table, PC relative, into a register, can be performed as: | |
529 | ||
530 | @example | |
531 | sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 | |
532 | add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 | |
533 | @end example | |
534 | ||
535 | Several relocations exist to allow the link editor to potentially | |
536 | optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22} | |
537 | relocation can obtained by enclosing an operand inside of | |
538 | @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10} | |
539 | relocation can obtained by enclosing an operand inside of | |
540 | @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be | |
541 | obtained by enclosing an operand inside of @samp{%gdop}. | |
542 | For example, assuming the GOT base is in register @code{%l7}: | |
543 | ||
544 | @example | |
545 | sethi %gdop_hix22(symbol), %l1 | |
546 | xor %l1, %gdop_lox10(symbol), %l1 | |
547 | ld [%l7 + %l1], %l2, %gdop(symbol) | |
548 | @end example | |
549 | ||
550 | There are many relocations that can be requested for access to | |
551 | thread local storage variables. All of the Sparc TLS mnemonics | |
552 | are supported: | |
553 | ||
554 | @itemize @bullet | |
555 | @item | |
556 | @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}. | |
557 | @item | |
558 | @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}. | |
559 | @item | |
560 | @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}. | |
561 | @item | |
562 | @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}. | |
563 | ||
564 | @item | |
565 | @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}. | |
566 | @item | |
567 | @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}. | |
568 | @item | |
569 | @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}. | |
570 | @item | |
571 | @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}. | |
572 | ||
573 | @item | |
574 | @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}. | |
575 | @item | |
576 | @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}. | |
577 | @item | |
578 | @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}. | |
579 | ||
580 | @item | |
581 | @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}. | |
582 | @item | |
583 | @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}. | |
584 | @item | |
585 | @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}. | |
586 | @item | |
587 | @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}. | |
588 | @item | |
589 | @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}. | |
590 | ||
591 | @item | |
592 | @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}. | |
593 | @item | |
594 | @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}. | |
595 | @end itemize | |
596 | ||
597 | Here are some example TLS model sequences. | |
598 | ||
599 | First, General Dynamic: | |
600 | ||
601 | @example | |
602 | sethi %tgd_hi22(symbol), %l1 | |
603 | add %l1, %tgd_lo10(symbol), %l1 | |
604 | add %l7, %l1, %o0, %tgd_add(symbol) | |
605 | call __tls_get_addr, %tgd_call(symbol) | |
606 | nop | |
607 | @end example | |
608 | ||
609 | Local Dynamic: | |
610 | ||
611 | @example | |
612 | sethi %tldm_hi22(symbol), %l1 | |
613 | add %l1, %tldm_lo10(symbol), %l1 | |
614 | add %l7, %l1, %o0, %tldm_add(symbol) | |
615 | call __tls_get_addr, %tldm_call(symbol) | |
616 | nop | |
617 | ||
618 | sethi %tldo_hix22(symbol), %l1 | |
619 | xor %l1, %tldo_lox10(symbol), %l1 | |
620 | add %o0, %l1, %l1, %tldo_add(symbol) | |
621 | @end example | |
622 | ||
623 | Initial Exec: | |
624 | ||
625 | @example | |
626 | sethi %tie_hi22(symbol), %l1 | |
627 | add %l1, %tie_lo10(symbol), %l1 | |
628 | ld [%l7 + %l1], %o0, %tie_ld(symbol) | |
629 | add %g7, %o0, %o0, %tie_add(symbol) | |
630 | ||
631 | sethi %tie_hi22(symbol), %l1 | |
632 | add %l1, %tie_lo10(symbol), %l1 | |
633 | ldx [%l7 + %l1], %o0, %tie_ldx(symbol) | |
634 | add %g7, %o0, %o0, %tie_add(symbol) | |
635 | @end example | |
636 | ||
637 | And finally, Local Exec: | |
638 | ||
639 | @example | |
640 | sethi %tle_hix22(symbol), %l1 | |
641 | add %l1, %tle_lox10(symbol), %l1 | |
642 | add %g7, %l1, %l1 | |
643 | @end example | |
644 | ||
645 | When assembling for 64-bit, and a secondary constant addend is | |
646 | specified in an address expression that would normally generate | |
647 | an @code{R_SPARC_LO10} relocation, the assembler will emit an | |
648 | @code{R_SPARC_OLO10} instead. | |
252b5132 | 649 | |
f04d18b7 DM |
650 | @node Sparc-Size-Translations |
651 | @subsection Size Translations | |
652 | @cindex Sparc size translations | |
653 | @cindex size, translations, Sparc | |
654 | ||
655 | Often it is desirable to write code in an operand size agnostic | |
656 | manner. @code{@value{AS}} provides support for this via | |
657 | operand size opcode translations. Translations are supported | |
658 | for loads, stores, shifts, compare-and-swap atomics, and the | |
659 | @samp{clr} synthetic instruction. | |
660 | ||
661 | If generating 32-bit code, @code{@value{AS}} will generate the | |
662 | 32-bit opcode. Whereas if 64-bit code is being generated, | |
663 | the 64-bit opcode will be emitted. For example @code{ldn} | |
664 | will be transformed into @code{ld} for 32-bit code and | |
665 | @code{ldx} for 64-bit code. | |
666 | ||
667 | Here is an example meant to demonstrate all the supported | |
668 | opcode translations: | |
669 | ||
670 | @example | |
671 | ldn [%o0], %o1 | |
672 | ldna [%o0] %asi, %o2 | |
673 | stn %o1, [%o0] | |
674 | stna %o2, [%o0] %asi | |
675 | slln %o3, 3, %o3 | |
676 | srln %o4, 8, %o4 | |
677 | sran %o5, 12, %o5 | |
678 | casn [%o0], %o1, %o2 | |
679 | casna [%o0] %asi, %o1, %o2 | |
680 | clrn %g1 | |
681 | @end example | |
682 | ||
683 | In 32-bit mode @code{@value{AS}} will emit: | |
684 | ||
685 | @example | |
686 | ld [%o0], %o1 | |
687 | lda [%o0] %asi, %o2 | |
688 | st %o1, [%o0] | |
689 | sta %o2, [%o0] %asi | |
690 | sll %o3, 3, %o3 | |
691 | srl %o4, 8, %o4 | |
692 | sra %o5, 12, %o5 | |
693 | cas [%o0], %o1, %o2 | |
694 | casa [%o0] %asi, %o1, %o2 | |
695 | clr %g1 | |
696 | @end example | |
697 | ||
698 | And in 64-bit mode @code{@value{AS}} will emit: | |
699 | ||
700 | @example | |
701 | ldx [%o0], %o1 | |
702 | ldxa [%o0] %asi, %o2 | |
703 | stx %o1, [%o0] | |
704 | stxa %o2, [%o0] %asi | |
705 | sllx %o3, 3, %o3 | |
706 | srlx %o4, 8, %o4 | |
707 | srax %o5, 12, %o5 | |
708 | casx [%o0], %o1, %o2 | |
709 | casxa [%o0] %asi, %o1, %o2 | |
710 | clrx %g1 | |
711 | @end example | |
712 | ||
713 | Finally, the @samp{.nword} translating directive is supported | |
714 | as well. It is documented in the section on Sparc machine | |
715 | directives. | |
716 | ||
252b5132 RH |
717 | @node Sparc-Float |
718 | @section Floating Point | |
719 | ||
720 | @cindex floating point, SPARC (@sc{ieee}) | |
721 | @cindex SPARC floating point (@sc{ieee}) | |
722 | The Sparc uses @sc{ieee} floating-point numbers. | |
723 | ||
724 | @node Sparc-Directives | |
725 | @section Sparc Machine Directives | |
726 | ||
727 | @cindex SPARC machine directives | |
728 | @cindex machine directives, SPARC | |
729 | The Sparc version of @code{@value{AS}} supports the following additional | |
730 | machine directives: | |
731 | ||
732 | @table @code | |
733 | @cindex @code{align} directive, SPARC | |
734 | @item .align | |
735 | This must be followed by the desired alignment in bytes. | |
736 | ||
737 | @cindex @code{common} directive, SPARC | |
738 | @item .common | |
739 | This must be followed by a symbol name, a positive number, and | |
740 | @code{"bss"}. This behaves somewhat like @code{.comm}, but the | |
741 | syntax is different. | |
742 | ||
743 | @cindex @code{half} directive, SPARC | |
744 | @item .half | |
745 | This is functionally identical to @code{.short}. | |
746 | ||
e06510e6 RH |
747 | @cindex @code{nword} directive, SPARC |
748 | @item .nword | |
749 | On the Sparc, the @code{.nword} directive produces native word sized value, | |
750 | ie. if assembling with -32 it is equivalent to @code{.word}, if assembling | |
751 | with -64 it is equivalent to @code{.xword}. | |
752 | ||
252b5132 RH |
753 | @cindex @code{proc} directive, SPARC |
754 | @item .proc | |
755 | This directive is ignored. Any text following it on the same | |
756 | line is also ignored. | |
757 | ||
e06510e6 RH |
758 | @cindex @code{register} directive, SPARC |
759 | @item .register | |
760 | This directive declares use of a global application or system register. | |
761 | It must be followed by a register name %g2, %g3, %g6 or %g7, comma and | |
6d8809aa | 762 | the symbol name for that register. If symbol name is @code{#scratch}, |
062b7c0c | 763 | it is a scratch register, if it is @code{#ignore}, it just suppresses any |
6d8809aa RH |
764 | errors about using undeclared global register, but does not emit any |
765 | information about it into the object file. This can be useful e.g. if you | |
766 | save the register before use and restore it after. | |
e06510e6 | 767 | |
252b5132 RH |
768 | @cindex @code{reserve} directive, SPARC |
769 | @item .reserve | |
770 | This must be followed by a symbol name, a positive number, and | |
771 | @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the | |
772 | syntax is different. | |
773 | ||
774 | @cindex @code{seg} directive, SPARC | |
775 | @item .seg | |
776 | This must be followed by @code{"text"}, @code{"data"}, or | |
777 | @code{"data1"}. It behaves like @code{.text}, @code{.data}, or | |
778 | @code{.data 1}. | |
779 | ||
780 | @cindex @code{skip} directive, SPARC | |
781 | @item .skip | |
782 | This is functionally identical to the @code{.space} directive. | |
783 | ||
784 | @cindex @code{word} directive, SPARC | |
785 | @item .word | |
786 | On the Sparc, the @code{.word} directive produces 32 bit values, | |
787 | instead of the 16 bit values it produces on many other machines. | |
788 | ||
789 | @cindex @code{xword} directive, SPARC | |
790 | @item .xword | |
791 | On the Sparc V9 processor, the @code{.xword} directive produces | |
792 | 64 bit values. | |
793 | @end table |