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6f2750fe | 1 | @c Copyright (C) 1991-2016 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node Sparc-Dependent | |
7 | @chapter SPARC Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter SPARC Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex SPARC support | |
15 | @menu | |
16 | * Sparc-Opts:: Options | |
17 | * Sparc-Aligned-Data:: Option to enforce aligned data | |
c15295d5 | 18 | * Sparc-Syntax:: Syntax |
252b5132 RH |
19 | * Sparc-Float:: Floating Point |
20 | * Sparc-Directives:: Sparc Machine Directives | |
21 | @end menu | |
22 | ||
23 | @node Sparc-Opts | |
24 | @section Options | |
25 | ||
26 | @cindex options for SPARC | |
27 | @cindex SPARC options | |
28 | @cindex architectures, SPARC | |
29 | @cindex SPARC architectures | |
f04d18b7 | 30 | The SPARC chip family includes several successive versions, using the same |
252b5132 | 31 | core instruction set, but including a few additional instructions at |
f04d18b7 | 32 | each version. There are exceptions to this however. For details on what |
252b5132 RH |
33 | instructions each variant supports, please see the chip's architecture |
34 | reference manual. | |
35 | ||
36 | By default, @code{@value{AS}} assumes the core instruction set (SPARC | |
37 | v6), but ``bumps'' the architecture level as needed: it switches to | |
38 | successively higher architectures as it encounters instructions that | |
39 | only exist in the higher levels. | |
40 | ||
41 | If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump | |
f04d18b7 | 42 | past sparclite by default, an option must be passed to enable the |
252b5132 RH |
43 | v9 instructions. |
44 | ||
45 | GAS treats sparclite as being compatible with v8, unless an architecture | |
46 | is explicitly requested. SPARC v9 is always incompatible with sparclite. | |
47 | ||
48 | @c The order here is the same as the order of enum sparc_opcode_arch_val | |
49 | @c to give the user a sense of the order of the "bumping". | |
50 | ||
51 | @table @code | |
52 | @kindex -Av6 | |
4bafe00e | 53 | @kindex -Av7 |
252b5132 | 54 | @kindex -Av8 |
d6787ef9 | 55 | @kindex -Aleon |
252b5132 RH |
56 | @kindex -Asparclet |
57 | @kindex -Asparclite | |
58 | @kindex -Av9 | |
59 | @kindex -Av9a | |
4bafe00e DM |
60 | @kindex -Av9b |
61 | @kindex -Av9c | |
62 | @kindex -Av9d | |
3d68f91c | 63 | @kindex -Av9e |
4bafe00e | 64 | @kindex -Av9v |
3d68f91c | 65 | @kindex -Av9m |
4bafe00e DM |
66 | @kindex -Asparc |
67 | @kindex -Asparcvis | |
68 | @kindex -Asparcvis2 | |
69 | @kindex -Asparcfmaf | |
70 | @kindex -Asparcima | |
71 | @kindex -Asparcvis3 | |
72 | @kindex -Asparcvis3r | |
d6787ef9 | 73 | @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite |
4bafe00e | 74 | @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv |
3d68f91c | 75 | @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m |
4bafe00e DM |
76 | @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima |
77 | @itemx -Asparcvis3 | -Asparcvis3r | |
252b5132 RH |
78 | Use one of the @samp{-A} options to select one of the SPARC |
79 | architectures explicitly. If you select an architecture explicitly, | |
80 | @code{@value{AS}} reports a fatal error if it encounters an instruction | |
81 | or feature requiring an incompatible or higher level. | |
82 | ||
4bafe00e DM |
83 | @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc}, |
84 | @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment. | |
252b5132 | 85 | |
3d68f91c JM |
86 | @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, |
87 | @samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit | |
88 | environment and are not available unless GAS is explicitly configured | |
89 | with 64 bit environment support. | |
252b5132 RH |
90 | |
91 | @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with | |
4bafe00e | 92 | UltraSPARC VIS 1.0 extensions. |
252b5132 | 93 | |
4bafe00e DM |
94 | @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions, |
95 | as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}. | |
96 | ||
97 | @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions, | |
98 | as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}. | |
99 | ||
100 | @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused | |
101 | multiply-add, VIS 3.0, and HPC extension instructions, as well as the | |
102 | instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}. | |
103 | ||
3d68f91c JM |
104 | @samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic |
105 | instructions, as well as the instructions enabled by @samp{-Av8plusd} | |
106 | and @samp{-Av9d}. | |
107 | ||
108 | @samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused | |
109 | multiply-add, and integer multiply-add, as well as the instructions | |
110 | enabled by @samp{-Av8pluse} and @samp{-Av9e}. | |
111 | ||
112 | @samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended, | |
113 | xmpmul, xmontmul and xmontsqr instructions, as well as the instructions | |
114 | enabled by @samp{-Av8plusv} and @samp{-Av9v}. | |
4bafe00e DM |
115 | |
116 | @samp{-Asparc} specifies a v9 environment. It is equivalent to | |
117 | @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise. | |
118 | ||
119 | @samp{-Asparcvis} specifies a v9a environment. It is equivalent to | |
120 | @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise. | |
121 | ||
122 | @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to | |
123 | @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise. | |
124 | ||
125 | @samp{-Asparcfmaf} specifies a v9b environment with the floating point | |
126 | fused multiply-add instructions enabled. | |
127 | ||
128 | @samp{-Asparcima} specifies a v9b environment with the integer | |
129 | multiply-add instructions enabled. | |
130 | ||
131 | @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0, | |
132 | HPC , and floating point fused multiply-add instructions enabled. | |
133 | ||
3d68f91c JM |
134 | @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC, |
135 | and floating point unfused multiply-add instructions enabled. | |
136 | ||
137 | @samp{-Asparc5} is equivalent to @samp{-Av9m}. | |
4bafe00e DM |
138 | |
139 | @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc | |
140 | @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a | |
3d68f91c | 141 | @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m |
4bafe00e DM |
142 | @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2 |
143 | @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3 | |
3d68f91c | 144 | @itemx -xarch=sparcvis3r | -xarch=sparc5 |
f04d18b7 | 145 | For compatibility with the SunOS v9 assembler. These options are |
4bafe00e | 146 | equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, |
3d68f91c JM |
147 | -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m, |
148 | -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima, | |
149 | -Asparcvis3, and -Asparcvis3r, respectively. | |
252b5132 RH |
150 | |
151 | @item -bump | |
152 | Warn whenever it is necessary to switch to another level. | |
153 | If an architecture level is explicitly requested, GAS will not issue | |
154 | warnings until that level is reached, and will then bump the level | |
155 | as required (except between incompatible levels). | |
156 | ||
157 | @item -32 | -64 | |
158 | Select the word size, either 32 bits or 64 bits. | |
159 | These options are only available with the ELF object file format, | |
160 | and require that the necessary BFD support has been included. | |
161 | @end table | |
162 | ||
163 | @node Sparc-Aligned-Data | |
164 | @section Enforcing aligned data | |
165 | ||
166 | @cindex data alignment on SPARC | |
167 | @cindex SPARC data alignment | |
168 | SPARC GAS normally permits data to be misaligned. For example, it | |
169 | permits the @code{.long} pseudo-op to be used on a byte boundary. | |
f04d18b7 DM |
170 | However, the native SunOS assemblers issue an error when they see |
171 | misaligned data. | |
252b5132 RH |
172 | |
173 | @kindex --enforce-aligned-data | |
174 | You can use the @code{--enforce-aligned-data} option to make SPARC GAS | |
f04d18b7 | 175 | also issue an error about misaligned data, just as the SunOS |
252b5132 RH |
176 | assemblers do. |
177 | ||
178 | The @code{--enforce-aligned-data} option is not the default because gcc | |
179 | issues misaligned data pseudo-ops when it initializes certain packed | |
180 | data structures (structures defined using the @code{packed} attribute). | |
181 | You may have to assemble with GAS in order to initialize packed data | |
182 | structures in your own code. | |
183 | ||
c15295d5 DM |
184 | @cindex SPARC syntax |
185 | @cindex syntax, SPARC | |
186 | @node Sparc-Syntax | |
187 | @section Sparc Syntax | |
188 | The assembler syntax closely follows The Sparc Architecture Manual, | |
189 | versions 8 and 9, as well as most extensions defined by Sun | |
190 | for their UltraSPARC and Niagara line of processors. | |
191 | ||
192 | @menu | |
193 | * Sparc-Chars:: Special Characters | |
194 | * Sparc-Regs:: Register Names | |
1a6b486f | 195 | * Sparc-Constants:: Constant Names |
c15295d5 | 196 | * Sparc-Relocs:: Relocations |
f04d18b7 | 197 | * Sparc-Size-Translations:: Size Translations |
c15295d5 DM |
198 | @end menu |
199 | ||
200 | @node Sparc-Chars | |
201 | @subsection Special Characters | |
202 | ||
203 | @cindex line comment character, Sparc | |
204 | @cindex Sparc line comment character | |
7c31ae13 NC |
205 | A @samp{!} character appearing anywhere on a line indicates the start |
206 | of a comment that extends to the end of that line. | |
207 | ||
208 | If a @samp{#} appears as the first character of a line then the whole | |
209 | line is treated as a comment, but in this case the line could also be | |
210 | a logical line number directive (@pxref{Comments}) or a preprocessor | |
211 | control command (@pxref{Preprocessing}). | |
c15295d5 DM |
212 | |
213 | @cindex line separator, Sparc | |
214 | @cindex statement separator, Sparc | |
215 | @cindex Sparc line separator | |
216 | @samp{;} can be used instead of a newline to separate statements. | |
217 | ||
218 | @node Sparc-Regs | |
219 | @subsection Register Names | |
220 | @cindex Sparc registers | |
221 | @cindex register names, Sparc | |
222 | ||
223 | The Sparc integer register file is broken down into global, | |
224 | outgoing, local, and incoming. | |
225 | ||
226 | @itemize @bullet | |
227 | @item | |
228 | The 8 global registers are referred to as @samp{%g@var{n}}. | |
229 | ||
230 | @item | |
231 | The 8 outgoing registers are referred to as @samp{%o@var{n}}. | |
232 | ||
233 | @item | |
234 | The 8 local registers are referred to as @samp{%l@var{n}}. | |
235 | ||
236 | @item | |
237 | The 8 incoming registers are referred to as @samp{%i@var{n}}. | |
238 | ||
239 | @item | |
240 | The frame pointer register @samp{%i6} can be referenced using | |
241 | the alias @samp{%fp}. | |
242 | ||
243 | @item | |
244 | The stack pointer register @samp{%o6} can be referenced using | |
245 | the alias @samp{%sp}. | |
246 | @end itemize | |
247 | ||
248 | Floating point registers are simply referred to as @samp{%f@var{n}}. | |
249 | When assembling for pre-V9, only 32 floating point registers | |
250 | are available. For V9 and later there are 64, but there are | |
251 | restrictions when referencing the upper 32 registers. They | |
252 | can only be accessed as double or quad, and thus only even | |
253 | or quad numbered accesses are allowed. For example, @samp{%f34} | |
254 | is a legal floating point register, but @samp{%f35} is not. | |
255 | ||
7039122d JM |
256 | Floating point registers accessed as double can also be referred using |
257 | the @samp{%d@var{n}} notation, where @var{n} is even. Similarly, | |
258 | floating point registers accessed as quad can be referred using the | |
259 | @samp{%q@var{n}} notation, where @var{n} is a multiple of 4. For | |
260 | example, @samp{%f4} can be denoted as both @samp{%d4} and @samp{%q4}. | |
261 | On the other hand, @samp{%f2} can be denoted as @samp{%d2} but not as | |
262 | @samp{%q2}. | |
263 | ||
c15295d5 DM |
264 | Certain V9 instructions allow access to ancillary state registers. |
265 | Most simply they can be referred to as @samp{%asr@var{n}} where | |
f04d18b7 | 266 | @var{n} can be from 16 to 31. However, there are some aliases |
c15295d5 DM |
267 | defined to reference ASR registers defined for various UltraSPARC |
268 | processors: | |
269 | ||
270 | @itemize @bullet | |
271 | @item | |
272 | The tick compare register is referred to as @samp{%tick_cmpr}. | |
273 | ||
274 | @item | |
1a6b486f DM |
275 | The system tick register is referred to as @samp{%stick}. An alias, |
276 | @samp{%sys_tick}, exists but is deprecated and should not be used | |
277 | by new software. | |
c15295d5 DM |
278 | |
279 | @item | |
1a6b486f DM |
280 | The system tick compare register is referred to as @samp{%stick_cmpr}. |
281 | An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should | |
282 | not be used by new software. | |
c15295d5 DM |
283 | |
284 | @item | |
285 | The software interrupt register is referred to as @samp{%softint}. | |
286 | ||
287 | @item | |
288 | The set software interrupt register is referred to as @samp{%set_softint}. | |
f04d18b7 | 289 | The mnemonic @samp{%softint_set} is provided as an alias. |
c15295d5 DM |
290 | |
291 | @item | |
292 | The clear software interrupt register is referred to as | |
f04d18b7 DM |
293 | @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided |
294 | as an alias. | |
c15295d5 DM |
295 | |
296 | @item | |
297 | The performance instrumentation counters register is referred to as | |
298 | @samp{%pic}. | |
299 | ||
300 | @item | |
301 | The performance control register is referred to as @samp{%pcr}. | |
302 | ||
303 | @item | |
304 | The graphics status register is referred to as @samp{%gsr}. | |
305 | ||
306 | @item | |
f04d18b7 | 307 | The V9 dispatch control register is referred to as @samp{%dcr}. |
c15295d5 DM |
308 | @end itemize |
309 | ||
310 | Various V9 branch and conditional move instructions allow | |
311 | specification of which set of integer condition codes to | |
312 | test. These are referred to as @samp{%xcc} and @samp{%icc}. | |
313 | ||
f9911beb JM |
314 | Additionally, GAS supports the so-called ``natural'' condition codes; |
315 | these are referred to as @samp{%ncc} and reference to @samp{%icc} if | |
316 | the word size is 32, @samp{%xcc} if the word size is 64. | |
317 | ||
c15295d5 DM |
318 | In V9, there are 4 sets of floating point condition codes |
319 | which are referred to as @samp{%fcc@var{n}}. | |
320 | ||
321 | Several special privileged and non-privileged registers | |
322 | exist: | |
323 | ||
324 | @itemize @bullet | |
325 | @item | |
326 | The V9 address space identifier register is referred to as @samp{%asi}. | |
327 | ||
328 | @item | |
329 | The V9 restorable windows register is referred to as @samp{%canrestore}. | |
330 | ||
331 | @item | |
332 | The V9 savable windows register is referred to as @samp{%cansave}. | |
333 | ||
334 | @item | |
335 | The V9 clean windows register is referred to as @samp{%cleanwin}. | |
336 | ||
337 | @item | |
338 | The V9 current window pointer register is referred to as @samp{%cwp}. | |
339 | ||
340 | @item | |
341 | The floating-point queue register is referred to as @samp{%fq}. | |
342 | ||
343 | @item | |
f04d18b7 | 344 | The V8 co-processor queue register is referred to as @samp{%cq}. |
c15295d5 DM |
345 | |
346 | @item | |
347 | The floating point status register is referred to as @samp{%fsr}. | |
348 | ||
349 | @item | |
350 | The other windows register is referred to as @samp{%otherwin}. | |
351 | ||
352 | @item | |
353 | The V9 program counter register is referred to as @samp{%pc}. | |
354 | ||
355 | @item | |
356 | The V9 next program counter register is referred to as @samp{%npc}. | |
357 | ||
358 | @item | |
359 | The V9 processor interrupt level register is referred to as @samp{%pil}. | |
360 | ||
361 | @item | |
362 | The V9 processor state register is referred to as @samp{%pstate}. | |
363 | ||
364 | @item | |
365 | The trap base address register is referred to as @samp{%tba}. | |
366 | ||
367 | @item | |
368 | The V9 tick register is referred to as @samp{%tick}. | |
369 | ||
370 | @item | |
371 | The V9 trap level is referred to as @samp{%tl}. | |
372 | ||
373 | @item | |
374 | The V9 trap program counter is referred to as @samp{%tpc}. | |
375 | ||
376 | @item | |
377 | The V9 trap next program counter is referred to as @samp{%tnpc}. | |
378 | ||
379 | @item | |
380 | The V9 trap state is referred to as @samp{%tstate}. | |
381 | ||
382 | @item | |
383 | The V9 trap type is referred to as @samp{%tt}. | |
384 | ||
385 | @item | |
386 | The V9 condition codes is referred to as @samp{%ccr}. | |
387 | ||
388 | @item | |
389 | The V9 floating-point registers state is referred to as @samp{%fprs}. | |
390 | ||
391 | @item | |
392 | The V9 version register is referred to as @samp{%ver}. | |
393 | ||
394 | @item | |
395 | The V9 window state register is referred to as @samp{%wstate}. | |
396 | ||
397 | @item | |
398 | The Y register is referred to as @samp{%y}. | |
399 | ||
400 | @item | |
401 | The V8 window invalid mask register is referred to as @samp{%wim}. | |
402 | ||
403 | @item | |
404 | The V8 processor state register is referred to as @samp{%psr}. | |
405 | ||
406 | @item | |
f04d18b7 | 407 | The V9 global register level register is referred to as @samp{%gl}. |
c15295d5 DM |
408 | @end itemize |
409 | ||
410 | Several special register names exist for hypervisor mode code: | |
411 | ||
412 | @itemize @bullet | |
413 | @item | |
414 | The hyperprivileged processor state register is referred to as | |
415 | @samp{%hpstate}. | |
416 | ||
417 | @item | |
418 | The hyperprivileged trap state register is referred to as @samp{%htstate}. | |
419 | ||
420 | @item | |
421 | The hyperprivileged interrupt pending register is referred to as | |
422 | @samp{%hintp}. | |
423 | ||
424 | @item | |
425 | The hyperprivileged trap base address register is referred to as | |
426 | @samp{%htba}. | |
427 | ||
428 | @item | |
429 | The hyperprivileged implementation version register is referred | |
430 | to as @samp{%hver}. | |
431 | ||
ec92c392 JM |
432 | @item |
433 | The hyperprivileged system tick offset register is referred to as | |
434 | @samp{%hstick_offset}. Note that there is no @samp{%hstick} register, | |
435 | the normal @samp{%stick} is used. | |
436 | ||
437 | @item | |
438 | The hyperprivileged system tick enable register is referred to as | |
439 | @samp{%hstick_enable}. | |
440 | ||
c15295d5 DM |
441 | @item |
442 | The hyperprivileged system tick compare register is referred | |
ec92c392 | 443 | to as @samp{%hstick_cmpr}. |
1a6b486f DM |
444 | @end itemize |
445 | ||
446 | @node Sparc-Constants | |
447 | @subsection Constants | |
448 | @cindex Sparc constants | |
449 | @cindex constants, Sparc | |
450 | ||
451 | Several Sparc instructions take an immediate operand field for | |
452 | which mnemonic names exist. Two such examples are @samp{membar} | |
453 | and @samp{prefetch}. Another example are the set of V9 | |
454 | memory access instruction that allow specification of an | |
455 | address space identifier. | |
456 | ||
457 | The @samp{membar} instruction specifies a memory barrier that is | |
458 | the defined by the operand which is a bitmask. The supported | |
459 | mask mnemonics are: | |
460 | ||
461 | @itemize @bullet | |
462 | @item | |
463 | @samp{#Sync} requests that all operations (including nonmemory | |
464 | reference operations) appearing prior to the @code{membar} must have | |
465 | been performed and the effects of any exceptions become visible before | |
466 | any instructions after the @code{membar} may be initiated. This | |
467 | corresponds to @code{membar} cmask field bit 2. | |
468 | ||
469 | @item | |
470 | @samp{#MemIssue} requests that all memory reference operations | |
471 | appearing prior to the @code{membar} must have been performed before | |
472 | any memory operation after the @code{membar} may be initiated. This | |
473 | corresponds to @code{membar} cmask field bit 1. | |
474 | ||
475 | @item | |
476 | @samp{#Lookaside} requests that a store appearing prior to the | |
477 | @code{membar} must complete before any load following the | |
478 | @code{membar} referencing the same address can be initiated. This | |
479 | corresponds to @code{membar} cmask field bit 0. | |
480 | ||
481 | @item | |
482 | @samp{#StoreStore} defines that the effects of all stores appearing | |
483 | prior to the @code{membar} instruction must be visible to all | |
484 | processors before the effect of any stores following the | |
485 | @code{membar}. Equivalent to the deprecated @code{stbar} instruction. | |
486 | This corresponds to @code{membar} mmask field bit 3. | |
487 | ||
488 | @item | |
489 | @samp{#LoadStore} defines all loads appearing prior to the | |
490 | @code{membar} instruction must have been performed before the effect | |
491 | of any stores following the @code{membar} is visible to any other | |
492 | processor. This corresponds to @code{membar} mmask field bit 2. | |
493 | ||
494 | @item | |
495 | @samp{#StoreLoad} defines that the effects of all stores appearing | |
496 | prior to the @code{membar} instruction must be visible to all | |
497 | processors before loads following the @code{membar} may be performed. | |
498 | This corresponds to @code{membar} mmask field bit 1. | |
499 | ||
500 | @item | |
501 | @samp{#LoadLoad} defines that all loads appearing prior to the | |
502 | @code{membar} instruction must have been performed before any loads | |
503 | following the @code{membar} may be performed. This corresponds to | |
504 | @code{membar} mmask field bit 0. | |
505 | ||
506 | @end itemize | |
507 | ||
508 | These values can be ored together, for example: | |
509 | ||
510 | @example | |
511 | membar #Sync | |
512 | membar #StoreLoad | #LoadLoad | |
513 | membar #StoreLoad | #StoreStore | |
514 | @end example | |
515 | ||
516 | The @code{prefetch} and @code{prefetcha} instructions take a prefetch | |
517 | function code. The following prefetch function code constant | |
518 | mnemonics are available: | |
519 | ||
520 | @itemize @bullet | |
521 | @item | |
522 | @samp{#n_reads} requests a prefetch for several reads, and corresponds | |
523 | to a prefetch function code of 0. | |
524 | ||
525 | @samp{#one_read} requests a prefetch for one read, and corresponds | |
526 | to a prefetch function code of 1. | |
527 | ||
528 | @samp{#n_writes} requests a prefetch for several writes (and possibly | |
529 | reads), and corresponds to a prefetch function code of 2. | |
530 | ||
531 | @samp{#one_write} requests a prefetch for one write, and corresponds | |
532 | to a prefetch function code of 3. | |
533 | ||
534 | @samp{#page} requests a prefetch page, and corresponds to a prefetch | |
535 | function code of 4. | |
536 | ||
537 | @samp{#invalidate} requests a prefetch invalidate, and corresponds to | |
538 | a prefetch function code of 16. | |
539 | ||
540 | @samp{#unified} requests a prefetch to the nearest unified cache, and | |
541 | corresponds to a prefetch function code of 17. | |
542 | ||
543 | @samp{#n_reads_strong} requests a strong prefetch for several reads, | |
544 | and corresponds to a prefetch function code of 20. | |
545 | ||
546 | @samp{#one_read_strong} requests a strong prefetch for one read, | |
547 | and corresponds to a prefetch function code of 21. | |
548 | ||
549 | @samp{#n_writes_strong} requests a strong prefetch for several writes, | |
550 | and corresponds to a prefetch function code of 22. | |
551 | ||
552 | @samp{#one_write_strong} requests a strong prefetch for one write, | |
553 | and corresponds to a prefetch function code of 23. | |
554 | ||
555 | Onle one prefetch code may be specified. Here are some examples: | |
556 | ||
557 | @example | |
558 | prefetch [%l0 + %l2], #one_read | |
559 | prefetch [%g2 + 8], #n_writes | |
560 | prefetcha [%g1] 0x8, #unified | |
561 | prefetcha [%o0 + 0x10] %asi, #n_reads | |
562 | @end example | |
563 | ||
564 | The actual behavior of a given prefetch function code is processor | |
565 | specific. If a processor does not implement a given prefetch | |
566 | function code, it will treat the prefetch instruction as a nop. | |
567 | ||
568 | For instructions that accept an immediate address space identifier, | |
569 | @code{@value{AS}} provides many mnemonics corresponding to | |
570 | V9 defined as well as UltraSPARC and Niagara extended values. | |
571 | For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}. | |
572 | See the V9 and processor specific manuals for details. | |
573 | ||
c15295d5 DM |
574 | @end itemize |
575 | ||
576 | @node Sparc-Relocs | |
577 | @subsection Relocations | |
578 | @cindex Sparc relocations | |
579 | @cindex relocations, Sparc | |
580 | ||
581 | ELF relocations are available as defined in the 32-bit and 64-bit | |
582 | Sparc ELF specifications. | |
583 | ||
584 | @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10} | |
585 | is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is | |
586 | obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained | |
587 | using @samp{%lox}. For example: | |
588 | ||
589 | @example | |
590 | sethi %hi(symbol), %g1 | |
591 | or %g1, %lo(symbol), %g1 | |
592 | ||
593 | sethi %hix(symbol), %g1 | |
594 | xor %g1, %lox(symbol), %g1 | |
595 | @end example | |
596 | ||
597 | These ``high'' mnemonics extract bits 31:10 of their operand, | |
598 | and the ``low'' mnemonics extract bits 9:0 of their operand. | |
599 | ||
600 | V9 code model relocations can be requested as follows: | |
601 | ||
602 | @itemize @bullet | |
603 | @item | |
604 | @code{R_SPARC_HH22} is requested using @samp{%hh}. It can | |
605 | also be generated using @samp{%uhi}. | |
606 | @item | |
607 | @code{R_SPARC_HM10} is requested using @samp{%hm}. It can | |
608 | also be generated using @samp{%ulo}. | |
609 | @item | |
610 | @code{R_SPARC_LM22} is requested using @samp{%lm}. | |
611 | ||
612 | @item | |
613 | @code{R_SPARC_H44} is requested using @samp{%h44}. | |
614 | @item | |
615 | @code{R_SPARC_M44} is requested using @samp{%m44}. | |
616 | @item | |
2755f698 DM |
617 | @code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}. |
618 | @item | |
619 | @code{R_SPARC_H34} is requested using @samp{%h34}. | |
c15295d5 DM |
620 | @end itemize |
621 | ||
2755f698 DM |
622 | The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it |
623 | calculates the necessary value, and therefore no explicit | |
624 | @code{R_SPARC_L34} relocation needed to be created for this purpose. | |
625 | ||
626 | The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code | |
627 | model. Here is an example abs34 address generation sequence: | |
628 | ||
629 | @example | |
630 | sethi %h34(symbol), %g1 | |
631 | sllx %g1, 2, %g1 | |
632 | or %g1, %l34(symbol), %g1 | |
633 | @end example | |
634 | ||
c15295d5 DM |
635 | The PC relative relocation @code{R_SPARC_PC22} can be obtained by |
636 | enclosing an operand inside of @samp{%pc22}. Likewise, the | |
637 | @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}. | |
638 | These are mostly used when assembling PIC code. For example, the | |
639 | standard PIC sequence on Sparc to get the base of the global offset | |
640 | table, PC relative, into a register, can be performed as: | |
641 | ||
642 | @example | |
643 | sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 | |
644 | add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 | |
645 | @end example | |
646 | ||
647 | Several relocations exist to allow the link editor to potentially | |
648 | optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22} | |
649 | relocation can obtained by enclosing an operand inside of | |
650 | @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10} | |
651 | relocation can obtained by enclosing an operand inside of | |
652 | @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be | |
653 | obtained by enclosing an operand inside of @samp{%gdop}. | |
654 | For example, assuming the GOT base is in register @code{%l7}: | |
655 | ||
656 | @example | |
657 | sethi %gdop_hix22(symbol), %l1 | |
658 | xor %l1, %gdop_lox10(symbol), %l1 | |
659 | ld [%l7 + %l1], %l2, %gdop(symbol) | |
660 | @end example | |
661 | ||
662 | There are many relocations that can be requested for access to | |
663 | thread local storage variables. All of the Sparc TLS mnemonics | |
664 | are supported: | |
665 | ||
666 | @itemize @bullet | |
667 | @item | |
668 | @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}. | |
669 | @item | |
670 | @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}. | |
671 | @item | |
672 | @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}. | |
673 | @item | |
674 | @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}. | |
675 | ||
676 | @item | |
677 | @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}. | |
678 | @item | |
679 | @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}. | |
680 | @item | |
681 | @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}. | |
682 | @item | |
683 | @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}. | |
684 | ||
685 | @item | |
686 | @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}. | |
687 | @item | |
688 | @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}. | |
689 | @item | |
690 | @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}. | |
691 | ||
692 | @item | |
693 | @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}. | |
694 | @item | |
695 | @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}. | |
696 | @item | |
697 | @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}. | |
698 | @item | |
699 | @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}. | |
700 | @item | |
701 | @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}. | |
702 | ||
703 | @item | |
704 | @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}. | |
705 | @item | |
706 | @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}. | |
707 | @end itemize | |
708 | ||
709 | Here are some example TLS model sequences. | |
710 | ||
711 | First, General Dynamic: | |
712 | ||
713 | @example | |
714 | sethi %tgd_hi22(symbol), %l1 | |
715 | add %l1, %tgd_lo10(symbol), %l1 | |
716 | add %l7, %l1, %o0, %tgd_add(symbol) | |
717 | call __tls_get_addr, %tgd_call(symbol) | |
718 | nop | |
719 | @end example | |
720 | ||
721 | Local Dynamic: | |
722 | ||
723 | @example | |
724 | sethi %tldm_hi22(symbol), %l1 | |
725 | add %l1, %tldm_lo10(symbol), %l1 | |
726 | add %l7, %l1, %o0, %tldm_add(symbol) | |
727 | call __tls_get_addr, %tldm_call(symbol) | |
728 | nop | |
729 | ||
730 | sethi %tldo_hix22(symbol), %l1 | |
731 | xor %l1, %tldo_lox10(symbol), %l1 | |
732 | add %o0, %l1, %l1, %tldo_add(symbol) | |
733 | @end example | |
734 | ||
735 | Initial Exec: | |
736 | ||
737 | @example | |
738 | sethi %tie_hi22(symbol), %l1 | |
739 | add %l1, %tie_lo10(symbol), %l1 | |
740 | ld [%l7 + %l1], %o0, %tie_ld(symbol) | |
741 | add %g7, %o0, %o0, %tie_add(symbol) | |
742 | ||
743 | sethi %tie_hi22(symbol), %l1 | |
744 | add %l1, %tie_lo10(symbol), %l1 | |
745 | ldx [%l7 + %l1], %o0, %tie_ldx(symbol) | |
746 | add %g7, %o0, %o0, %tie_add(symbol) | |
747 | @end example | |
748 | ||
749 | And finally, Local Exec: | |
750 | ||
751 | @example | |
752 | sethi %tle_hix22(symbol), %l1 | |
753 | add %l1, %tle_lox10(symbol), %l1 | |
754 | add %g7, %l1, %l1 | |
755 | @end example | |
756 | ||
757 | When assembling for 64-bit, and a secondary constant addend is | |
758 | specified in an address expression that would normally generate | |
759 | an @code{R_SPARC_LO10} relocation, the assembler will emit an | |
760 | @code{R_SPARC_OLO10} instead. | |
252b5132 | 761 | |
f04d18b7 DM |
762 | @node Sparc-Size-Translations |
763 | @subsection Size Translations | |
764 | @cindex Sparc size translations | |
765 | @cindex size, translations, Sparc | |
766 | ||
767 | Often it is desirable to write code in an operand size agnostic | |
768 | manner. @code{@value{AS}} provides support for this via | |
769 | operand size opcode translations. Translations are supported | |
770 | for loads, stores, shifts, compare-and-swap atomics, and the | |
771 | @samp{clr} synthetic instruction. | |
772 | ||
773 | If generating 32-bit code, @code{@value{AS}} will generate the | |
774 | 32-bit opcode. Whereas if 64-bit code is being generated, | |
775 | the 64-bit opcode will be emitted. For example @code{ldn} | |
776 | will be transformed into @code{ld} for 32-bit code and | |
777 | @code{ldx} for 64-bit code. | |
778 | ||
779 | Here is an example meant to demonstrate all the supported | |
780 | opcode translations: | |
781 | ||
782 | @example | |
783 | ldn [%o0], %o1 | |
784 | ldna [%o0] %asi, %o2 | |
785 | stn %o1, [%o0] | |
786 | stna %o2, [%o0] %asi | |
787 | slln %o3, 3, %o3 | |
788 | srln %o4, 8, %o4 | |
789 | sran %o5, 12, %o5 | |
790 | casn [%o0], %o1, %o2 | |
791 | casna [%o0] %asi, %o1, %o2 | |
792 | clrn %g1 | |
793 | @end example | |
794 | ||
795 | In 32-bit mode @code{@value{AS}} will emit: | |
796 | ||
797 | @example | |
798 | ld [%o0], %o1 | |
799 | lda [%o0] %asi, %o2 | |
800 | st %o1, [%o0] | |
801 | sta %o2, [%o0] %asi | |
802 | sll %o3, 3, %o3 | |
803 | srl %o4, 8, %o4 | |
804 | sra %o5, 12, %o5 | |
805 | cas [%o0], %o1, %o2 | |
806 | casa [%o0] %asi, %o1, %o2 | |
807 | clr %g1 | |
808 | @end example | |
809 | ||
810 | And in 64-bit mode @code{@value{AS}} will emit: | |
811 | ||
812 | @example | |
813 | ldx [%o0], %o1 | |
814 | ldxa [%o0] %asi, %o2 | |
815 | stx %o1, [%o0] | |
816 | stxa %o2, [%o0] %asi | |
817 | sllx %o3, 3, %o3 | |
818 | srlx %o4, 8, %o4 | |
819 | srax %o5, 12, %o5 | |
820 | casx [%o0], %o1, %o2 | |
821 | casxa [%o0] %asi, %o1, %o2 | |
822 | clrx %g1 | |
823 | @end example | |
824 | ||
825 | Finally, the @samp{.nword} translating directive is supported | |
826 | as well. It is documented in the section on Sparc machine | |
827 | directives. | |
828 | ||
252b5132 RH |
829 | @node Sparc-Float |
830 | @section Floating Point | |
831 | ||
832 | @cindex floating point, SPARC (@sc{ieee}) | |
833 | @cindex SPARC floating point (@sc{ieee}) | |
834 | The Sparc uses @sc{ieee} floating-point numbers. | |
835 | ||
836 | @node Sparc-Directives | |
837 | @section Sparc Machine Directives | |
838 | ||
839 | @cindex SPARC machine directives | |
840 | @cindex machine directives, SPARC | |
841 | The Sparc version of @code{@value{AS}} supports the following additional | |
842 | machine directives: | |
843 | ||
844 | @table @code | |
845 | @cindex @code{align} directive, SPARC | |
846 | @item .align | |
847 | This must be followed by the desired alignment in bytes. | |
848 | ||
849 | @cindex @code{common} directive, SPARC | |
850 | @item .common | |
851 | This must be followed by a symbol name, a positive number, and | |
852 | @code{"bss"}. This behaves somewhat like @code{.comm}, but the | |
853 | syntax is different. | |
854 | ||
855 | @cindex @code{half} directive, SPARC | |
856 | @item .half | |
857 | This is functionally identical to @code{.short}. | |
858 | ||
e06510e6 RH |
859 | @cindex @code{nword} directive, SPARC |
860 | @item .nword | |
861 | On the Sparc, the @code{.nword} directive produces native word sized value, | |
862 | ie. if assembling with -32 it is equivalent to @code{.word}, if assembling | |
863 | with -64 it is equivalent to @code{.xword}. | |
864 | ||
252b5132 RH |
865 | @cindex @code{proc} directive, SPARC |
866 | @item .proc | |
867 | This directive is ignored. Any text following it on the same | |
868 | line is also ignored. | |
869 | ||
e06510e6 RH |
870 | @cindex @code{register} directive, SPARC |
871 | @item .register | |
872 | This directive declares use of a global application or system register. | |
873 | It must be followed by a register name %g2, %g3, %g6 or %g7, comma and | |
6d8809aa | 874 | the symbol name for that register. If symbol name is @code{#scratch}, |
062b7c0c | 875 | it is a scratch register, if it is @code{#ignore}, it just suppresses any |
6d8809aa RH |
876 | errors about using undeclared global register, but does not emit any |
877 | information about it into the object file. This can be useful e.g. if you | |
878 | save the register before use and restore it after. | |
e06510e6 | 879 | |
252b5132 RH |
880 | @cindex @code{reserve} directive, SPARC |
881 | @item .reserve | |
882 | This must be followed by a symbol name, a positive number, and | |
883 | @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the | |
884 | syntax is different. | |
885 | ||
886 | @cindex @code{seg} directive, SPARC | |
887 | @item .seg | |
888 | This must be followed by @code{"text"}, @code{"data"}, or | |
889 | @code{"data1"}. It behaves like @code{.text}, @code{.data}, or | |
890 | @code{.data 1}. | |
891 | ||
892 | @cindex @code{skip} directive, SPARC | |
893 | @item .skip | |
894 | This is functionally identical to the @code{.space} directive. | |
895 | ||
896 | @cindex @code{word} directive, SPARC | |
897 | @item .word | |
898 | On the Sparc, the @code{.word} directive produces 32 bit values, | |
899 | instead of the 16 bit values it produces on many other machines. | |
900 | ||
901 | @cindex @code{xword} directive, SPARC | |
902 | @item .xword | |
903 | On the Sparc V9 processor, the @code{.xword} directive produces | |
904 | 64 bit values. | |
905 | @end table |