Zero-extend address from 32-bit to 64-bit for ADDR32 prefix
[deliverable/binutils-gdb.git] / gas / doc / c-tilegx.texi
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1@c Copyright 2011
2@c Free Software Foundation, Inc.
3@c This is part of the GAS manual.
4@c For copying conditions, see the file as.texinfo.
5@c man end
6
7@ifset GENERIC
8@page
9@node TILE-Gx-Dependent
10@chapter TILE-Gx Dependent Features
11@end ifset
12@ifclear GENERIC
13@node Machine Dependencies
14@chapter TILE-Gx Dependent Features
15@end ifclear
16
17@cindex TILE-Gx support
18@menu
19* TILE-Gx Options:: TILE-Gx Options
20* TILE-Gx Syntax:: TILE-Gx Syntax
21* TILE-Gx Directives:: TILE-Gx Directives
22@end menu
23
24@node TILE-Gx Options
25@section Options
26
27The following table lists all available TILE-Gx specific options:
28
29@c man begin OPTIONS
30@table @gcctabopt
31@cindex @samp{-m32} option, TILE-Gx
32@cindex @samp{-m64} option, TILE-Gx
33@item -m32 | -m64
34Select the word size, either 32 bits or 64 bits.
35
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36@cindex @samp{-EB} option, TILE-Gx
37@cindex @samp{-EL} option, TILE-Gx
38@item -EB | -EL
39Select the endianness, either big-endian (-EB) or little-endian (-EL).
40
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41@end table
42@c man end
43
44@node TILE-Gx Syntax
45@section Syntax
46@cindex TILE-Gx syntax
47@cindex syntax, TILE-Gx
48
49Block comments are delimited by @samp{/*} and @samp{*/}. End of line
50comments may be introduced by @samp{#}.
51
52Instructions consist of a leading opcode or macro name followed by
53whitespace and an optional comma-separated list of operands:
54
55@smallexample
56@var{opcode} [@var{operand}, @dots{}]
57@end smallexample
58
59Instructions must be separated by a newline or semicolon.
60
61There are two ways to write code: either write naked instructions,
62which the assembler is free to combine into VLIW bundles, or specify
63the VLIW bundles explicitly.
64
65Bundles are specified using curly braces:
66
67@smallexample
68@{ @var{add} r3,r4,r5 ; @var{add} r7,r8,r9 ; @var{lw} r10,r11 @}
69@end smallexample
70
71A bundle can span multiple lines. If you want to put multiple
72instructions on a line, whether in a bundle or not, you need to
73separate them with semicolons as in this example.
74
75A bundle may contain one or more instructions, up to the limit
76specified by the ISA (currently three). If fewer instructions are
77specified than the hardware supports in a bundle, the assembler
78inserts @code{fnop} instructions automatically.
79
80The assembler will prefer to preserve the ordering of instructions
81within the bundle, putting the first instruction in a lower-numbered
82pipeline than the next one, etc. This fact, combined with the
83optional use of explicit @code{fnop} or @code{nop} instructions,
84allows precise control over which pipeline executes each instruction.
85
86If the instructions cannot be bundled in the listed order, the
87assembler will automatically try to find a valid pipeline
88assignment. If there is no way to bundle the instructions together,
89the assembler reports an error.
90
91The assembler does not yet auto-bundle (automatically combine multiple
92instructions into one bundle), but it reserves the right to do so in
93the future. If you want to force an instruction to run by itself, put
94it in a bundle explicitly with curly braces and use @code{nop}
95instructions (not @code{fnop}) to fill the remaining pipeline slots in
96that bundle.
97
98@menu
99* TILE-Gx Opcodes:: Opcode Naming Conventions.
100* TILE-Gx Registers:: Register Naming.
101* TILE-Gx Modifiers:: Symbolic Operand Modifiers.
102@end menu
103
104@node TILE-Gx Opcodes
105@subsection Opcode Names
106@cindex TILE-Gx opcode names
107@cindex opcode names, TILE-Gx
108
109For a complete list of opcodes and descriptions of their semantics,
110see @cite{TILE-Gx Instruction Set Architecture}, available upon
111request at www.tilera.com.
112
113@node TILE-Gx Registers
114@subsection Register Names
115@cindex TILE-Gx register names
116@cindex register names, TILE-Gx
117
118General-purpose registers are represented by predefined symbols of the
119form @samp{r@var{N}}, where @var{N} represents a number between
120@code{0} and @code{63}. However, the following registers have
121canonical names that must be used instead:
122
123@table @code
124@item r54
125sp
126
127@item r55
128lr
129
130@item r56
131sn
132
133@item r57
134idn0
135
136@item r58
137idn1
138
139@item r59
140udn0
141
142@item r60
143udn1
144
145@item r61
146udn2
147
148@item r62
149udn3
150
151@item r63
152zero
153
154@end table
155
156The assembler will emit a warning if a numeric name is used instead of
157the non-numeric name. The @code{.no_require_canonical_reg_names}
158assembler pseudo-op turns off this
159warning. @code{.require_canonical_reg_names} turns it back on.
160
161@node TILE-Gx Modifiers
162@subsection Symbolic Operand Modifiers
163@cindex TILE-Gx modifiers
164@cindex symbol modifiers, TILE-Gx
165
166The assembler supports several modifiers when using symbol addresses
167in TILE-Gx instruction operands. The general syntax is the following:
168
169@smallexample
170modifier(symbol)
171@end smallexample
172
173The following modifiers are supported:
174
175@table @code
176
177@item hw0
178
179This modifier is used to load bits 0-15 of the symbol's address.
180
181@item hw1
182
183This modifier is used to load bits 16-31 of the symbol's address.
184
185@item hw2
186
187This modifier is used to load bits 32-47 of the symbol's address.
188
189@item hw3
190
191This modifier is used to load bits 48-63 of the symbol's address.
192
193@item hw0_last
194
195This modifier yields the same value as @code{hw0}, but it also checks
196that the value does not overflow.
197
198@item hw1_last
199
200This modifier yields the same value as @code{hw1}, but it also checks
201that the value does not overflow.
202
203@item hw2_last
204
205This modifier yields the same value as @code{hw2}, but it also checks
206that the value does not overflow.
207
208A 48-bit symbolic value is constructed by using the following idiom:
209
210@smallexample
211moveli r0, hw2_last(sym)
212shl16insli r0, r0, hw1(sym)
213shl16insli r0, r0, hw0(sym)
214@end smallexample
215
216@item hw0_got
217
218This modifier is used to load bits 0-15 of the symbol's offset in the
219GOT entry corresponding to the symbol.
220
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221@item hw0_last_got
222
223This modifier yields the same value as @code{hw0_got}, but it also
224checks that the value does not overflow.
225
226@item hw1_last_got
227
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228This modifier is used to load bits 16-31 of the symbol's offset in the
229GOT entry corresponding to the symbol, and it also checks that the
230value does not overflow.
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231
232@item plt
233
234This modifier is used for function symbols. It causes a
235@emph{procedure linkage table}, an array of code stubs, to be created
236at the time the shared object is created or linked against, together
237with a global offset table entry. The value is a pc-relative offset
238to the corresponding stub code in the procedure linkage table. This
239arrangement causes the run-time symbol resolver to be called to look
240up and set the value of the symbol the first time the function is
241called (at latest; depending environment variables). It is only safe
242to leave the symbol unresolved this way if all references are function
243calls.
244
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245@item hw0_plt
246
247This modifier is used to load bits 0-15 of the pc-relative address of
248a plt entry.
249
250@item hw1_plt
251
252This modifier is used to load bits 16-31 of the pc-relative address of
253a plt entry.
254
255@item hw1_last_plt
256
257This modifier yields the same value as @code{hw1_plt}, but it also
258checks that the value does not overflow.
259
260@item hw2_last_plt
261
262This modifier is used to load bits 32-47 of the pc-relative address of
263a plt entry, and it also checks that the value does not overflow.
264
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265@item hw0_tls_gd
266
267This modifier is used to load bits 0-15 of the offset of the GOT entry
268of the symbol's TLS descriptor, to be used for general-dynamic TLS
269accesses.
270
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271@item hw0_last_tls_gd
272
273This modifier yields the same value as @code{hw0_tls_gd}, but it also
274checks that the value does not overflow.
275
276@item hw1_last_tls_gd
277
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278This modifier is used to load bits 16-31 of the offset of the GOT
279entry of the symbol's TLS descriptor, to be used for general-dynamic
280TLS accesses. It also checks that the value does not overflow.
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281
282@item hw0_tls_ie
283
284This modifier is used to load bits 0-15 of the offset of the GOT entry
285containing the offset of the symbol's address from the TCB, to be used
286for initial-exec TLS accesses.
287
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288@item hw0_last_tls_ie
289
290This modifier yields the same value as @code{hw0_tls_ie}, but it also
291checks that the value does not overflow.
292
293@item hw1_last_tls_ie
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294
295This modifier is used to load bits 16-31 of the offset of the GOT
296entry containing the offset of the symbol's address from the TCB, to
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297be used for initial-exec TLS accesses. It also checks that the value
298does not overflow.
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6f7be959 300@item hw0_tls_le
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302This modifier is used to load bits 0-15 of the offset of the symbol's
303address from the TCB, to be used for local-exec TLS accesses.
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6f7be959 305@item hw0_last_tls_le
aa137e4d 306
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307This modifier yields the same value as @code{hw0_tls_le}, but it also
308checks that the value does not overflow.
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6f7be959 310@item hw1_last_tls_le
aa137e4d 311
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312This modifier is used to load bits 16-31 of the offset of the symbol's
313address from the TCB, to be used for local-exec TLS accesses. It
314also checks that the value does not overflow.
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6f7be959 316@item tls_gd_call
aa137e4d 317
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318This modifier is used to tag an instrution as the ``call'' part of a
319calling sequence for a TLS GD reference of its operand.
aa137e4d 320
6f7be959 321@item tls_gd_add
aa137e4d 322
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323This modifier is used to tag an instruction as the ``add'' part of a
324calling sequence for a TLS GD reference of its operand.
325
326@item tls_ie_load
327
328This modifier is used to tag an instruction as the ``load'' part of a
329calling sequence for a TLS IE reference of its operand.
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330
331@end table
332
333@node TILE-Gx Directives
334@section TILE-Gx Directives
335@cindex machine directives, TILE-Gx
336@cindex TILE-Gx machine directives
337
338@table @code
339
340@cindex @code{.align} directive, TILE-Gx
341@item .align @var{expression} [, @var{expression}]
342This is the generic @var{.align} directive. The first argument is the
343requested alignment in bytes.
344
345@cindex @code{.allow_suspicious_bundles} directive, TILE-Gx
346@item .allow_suspicious_bundles
347Turns on error checking for combinations of instructions in a bundle
348that probably indicate a programming error. This is on by default.
349
350@item .no_allow_suspicious_bundles
351Turns off error checking for combinations of instructions in a bundle
352that probably indicate a programming error.
353
354@cindex @code{.require_canonical_reg_names} directive, TILE-Gx
355@item .require_canonical_reg_names
356Require that canonical register names be used, and emit a warning if
357the numeric names are used. This is on by default.
358
359@item .no_require_canonical_reg_names
360Permit the use of numeric names for registers that have canonical
361names.
362
363@end table
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