Commit | Line | Data |
---|---|---|
aa137e4d NC |
1 | @c Copyright 2011 |
2 | @c Free Software Foundation, Inc. | |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @c man end | |
6 | ||
7 | @ifset GENERIC | |
8 | @page | |
9 | @node TILE-Gx-Dependent | |
10 | @chapter TILE-Gx Dependent Features | |
11 | @end ifset | |
12 | @ifclear GENERIC | |
13 | @node Machine Dependencies | |
14 | @chapter TILE-Gx Dependent Features | |
15 | @end ifclear | |
16 | ||
17 | @cindex TILE-Gx support | |
18 | @menu | |
19 | * TILE-Gx Options:: TILE-Gx Options | |
20 | * TILE-Gx Syntax:: TILE-Gx Syntax | |
21 | * TILE-Gx Directives:: TILE-Gx Directives | |
22 | @end menu | |
23 | ||
24 | @node TILE-Gx Options | |
25 | @section Options | |
26 | ||
27 | The following table lists all available TILE-Gx specific options: | |
28 | ||
29 | @c man begin OPTIONS | |
30 | @table @gcctabopt | |
31 | @cindex @samp{-m32} option, TILE-Gx | |
32 | @cindex @samp{-m64} option, TILE-Gx | |
33 | @item -m32 | -m64 | |
34 | Select the word size, either 32 bits or 64 bits. | |
35 | ||
fb6cedde WL |
36 | @cindex @samp{-EB} option, TILE-Gx |
37 | @cindex @samp{-EL} option, TILE-Gx | |
38 | @item -EB | -EL | |
39 | Select the endianness, either big-endian (-EB) or little-endian (-EL). | |
40 | ||
aa137e4d NC |
41 | @end table |
42 | @c man end | |
43 | ||
44 | @node TILE-Gx Syntax | |
45 | @section Syntax | |
46 | @cindex TILE-Gx syntax | |
47 | @cindex syntax, TILE-Gx | |
48 | ||
49 | Block comments are delimited by @samp{/*} and @samp{*/}. End of line | |
50 | comments may be introduced by @samp{#}. | |
51 | ||
52 | Instructions consist of a leading opcode or macro name followed by | |
53 | whitespace and an optional comma-separated list of operands: | |
54 | ||
55 | @smallexample | |
56 | @var{opcode} [@var{operand}, @dots{}] | |
57 | @end smallexample | |
58 | ||
59 | Instructions must be separated by a newline or semicolon. | |
60 | ||
61 | There are two ways to write code: either write naked instructions, | |
62 | which the assembler is free to combine into VLIW bundles, or specify | |
63 | the VLIW bundles explicitly. | |
64 | ||
65 | Bundles are specified using curly braces: | |
66 | ||
67 | @smallexample | |
68 | @{ @var{add} r3,r4,r5 ; @var{add} r7,r8,r9 ; @var{lw} r10,r11 @} | |
69 | @end smallexample | |
70 | ||
71 | A bundle can span multiple lines. If you want to put multiple | |
72 | instructions on a line, whether in a bundle or not, you need to | |
73 | separate them with semicolons as in this example. | |
74 | ||
75 | A bundle may contain one or more instructions, up to the limit | |
76 | specified by the ISA (currently three). If fewer instructions are | |
77 | specified than the hardware supports in a bundle, the assembler | |
78 | inserts @code{fnop} instructions automatically. | |
79 | ||
80 | The assembler will prefer to preserve the ordering of instructions | |
81 | within the bundle, putting the first instruction in a lower-numbered | |
82 | pipeline than the next one, etc. This fact, combined with the | |
83 | optional use of explicit @code{fnop} or @code{nop} instructions, | |
84 | allows precise control over which pipeline executes each instruction. | |
85 | ||
86 | If the instructions cannot be bundled in the listed order, the | |
87 | assembler will automatically try to find a valid pipeline | |
88 | assignment. If there is no way to bundle the instructions together, | |
89 | the assembler reports an error. | |
90 | ||
91 | The assembler does not yet auto-bundle (automatically combine multiple | |
92 | instructions into one bundle), but it reserves the right to do so in | |
93 | the future. If you want to force an instruction to run by itself, put | |
94 | it in a bundle explicitly with curly braces and use @code{nop} | |
95 | instructions (not @code{fnop}) to fill the remaining pipeline slots in | |
96 | that bundle. | |
97 | ||
98 | @menu | |
99 | * TILE-Gx Opcodes:: Opcode Naming Conventions. | |
100 | * TILE-Gx Registers:: Register Naming. | |
101 | * TILE-Gx Modifiers:: Symbolic Operand Modifiers. | |
102 | @end menu | |
103 | ||
104 | @node TILE-Gx Opcodes | |
105 | @subsection Opcode Names | |
106 | @cindex TILE-Gx opcode names | |
107 | @cindex opcode names, TILE-Gx | |
108 | ||
109 | For a complete list of opcodes and descriptions of their semantics, | |
110 | see @cite{TILE-Gx Instruction Set Architecture}, available upon | |
111 | request at www.tilera.com. | |
112 | ||
113 | @node TILE-Gx Registers | |
114 | @subsection Register Names | |
115 | @cindex TILE-Gx register names | |
116 | @cindex register names, TILE-Gx | |
117 | ||
118 | General-purpose registers are represented by predefined symbols of the | |
119 | form @samp{r@var{N}}, where @var{N} represents a number between | |
120 | @code{0} and @code{63}. However, the following registers have | |
121 | canonical names that must be used instead: | |
122 | ||
123 | @table @code | |
124 | @item r54 | |
125 | sp | |
126 | ||
127 | @item r55 | |
128 | lr | |
129 | ||
130 | @item r56 | |
131 | sn | |
132 | ||
133 | @item r57 | |
134 | idn0 | |
135 | ||
136 | @item r58 | |
137 | idn1 | |
138 | ||
139 | @item r59 | |
140 | udn0 | |
141 | ||
142 | @item r60 | |
143 | udn1 | |
144 | ||
145 | @item r61 | |
146 | udn2 | |
147 | ||
148 | @item r62 | |
149 | udn3 | |
150 | ||
151 | @item r63 | |
152 | zero | |
153 | ||
154 | @end table | |
155 | ||
156 | The assembler will emit a warning if a numeric name is used instead of | |
157 | the non-numeric name. The @code{.no_require_canonical_reg_names} | |
158 | assembler pseudo-op turns off this | |
159 | warning. @code{.require_canonical_reg_names} turns it back on. | |
160 | ||
161 | @node TILE-Gx Modifiers | |
162 | @subsection Symbolic Operand Modifiers | |
163 | @cindex TILE-Gx modifiers | |
164 | @cindex symbol modifiers, TILE-Gx | |
165 | ||
166 | The assembler supports several modifiers when using symbol addresses | |
167 | in TILE-Gx instruction operands. The general syntax is the following: | |
168 | ||
169 | @smallexample | |
170 | modifier(symbol) | |
171 | @end smallexample | |
172 | ||
173 | The following modifiers are supported: | |
174 | ||
175 | @table @code | |
176 | ||
177 | @item hw0 | |
178 | ||
179 | This modifier is used to load bits 0-15 of the symbol's address. | |
180 | ||
181 | @item hw1 | |
182 | ||
183 | This modifier is used to load bits 16-31 of the symbol's address. | |
184 | ||
185 | @item hw2 | |
186 | ||
187 | This modifier is used to load bits 32-47 of the symbol's address. | |
188 | ||
189 | @item hw3 | |
190 | ||
191 | This modifier is used to load bits 48-63 of the symbol's address. | |
192 | ||
193 | @item hw0_last | |
194 | ||
195 | This modifier yields the same value as @code{hw0}, but it also checks | |
196 | that the value does not overflow. | |
197 | ||
198 | @item hw1_last | |
199 | ||
200 | This modifier yields the same value as @code{hw1}, but it also checks | |
201 | that the value does not overflow. | |
202 | ||
203 | @item hw2_last | |
204 | ||
205 | This modifier yields the same value as @code{hw2}, but it also checks | |
206 | that the value does not overflow. | |
207 | ||
208 | A 48-bit symbolic value is constructed by using the following idiom: | |
209 | ||
210 | @smallexample | |
211 | moveli r0, hw2_last(sym) | |
212 | shl16insli r0, r0, hw1(sym) | |
213 | shl16insli r0, r0, hw0(sym) | |
214 | @end smallexample | |
215 | ||
216 | @item hw0_got | |
217 | ||
218 | This modifier is used to load bits 0-15 of the symbol's offset in the | |
219 | GOT entry corresponding to the symbol. | |
220 | ||
aa137e4d NC |
221 | @item hw0_last_got |
222 | ||
223 | This modifier yields the same value as @code{hw0_got}, but it also | |
224 | checks that the value does not overflow. | |
225 | ||
226 | @item hw1_last_got | |
227 | ||
6f7be959 WL |
228 | This modifier is used to load bits 16-31 of the symbol's offset in the |
229 | GOT entry corresponding to the symbol, and it also checks that the | |
230 | value does not overflow. | |
aa137e4d NC |
231 | |
232 | @item plt | |
233 | ||
234 | This modifier is used for function symbols. It causes a | |
235 | @emph{procedure linkage table}, an array of code stubs, to be created | |
236 | at the time the shared object is created or linked against, together | |
237 | with a global offset table entry. The value is a pc-relative offset | |
238 | to the corresponding stub code in the procedure linkage table. This | |
239 | arrangement causes the run-time symbol resolver to be called to look | |
240 | up and set the value of the symbol the first time the function is | |
241 | called (at latest; depending environment variables). It is only safe | |
242 | to leave the symbol unresolved this way if all references are function | |
243 | calls. | |
244 | ||
245 | @item hw0_tls_gd | |
246 | ||
247 | This modifier is used to load bits 0-15 of the offset of the GOT entry | |
248 | of the symbol's TLS descriptor, to be used for general-dynamic TLS | |
249 | accesses. | |
250 | ||
aa137e4d NC |
251 | @item hw0_last_tls_gd |
252 | ||
253 | This modifier yields the same value as @code{hw0_tls_gd}, but it also | |
254 | checks that the value does not overflow. | |
255 | ||
256 | @item hw1_last_tls_gd | |
257 | ||
6f7be959 WL |
258 | This modifier is used to load bits 16-31 of the offset of the GOT |
259 | entry of the symbol's TLS descriptor, to be used for general-dynamic | |
260 | TLS accesses. It also checks that the value does not overflow. | |
aa137e4d NC |
261 | |
262 | @item hw0_tls_ie | |
263 | ||
264 | This modifier is used to load bits 0-15 of the offset of the GOT entry | |
265 | containing the offset of the symbol's address from the TCB, to be used | |
266 | for initial-exec TLS accesses. | |
267 | ||
6f7be959 WL |
268 | @item hw0_last_tls_ie |
269 | ||
270 | This modifier yields the same value as @code{hw0_tls_ie}, but it also | |
271 | checks that the value does not overflow. | |
272 | ||
273 | @item hw1_last_tls_ie | |
aa137e4d NC |
274 | |
275 | This modifier is used to load bits 16-31 of the offset of the GOT | |
276 | entry containing the offset of the symbol's address from the TCB, to | |
6f7be959 WL |
277 | be used for initial-exec TLS accesses. It also checks that the value |
278 | does not overflow. | |
aa137e4d | 279 | |
6f7be959 | 280 | @item hw0_tls_le |
aa137e4d | 281 | |
6f7be959 WL |
282 | This modifier is used to load bits 0-15 of the offset of the symbol's |
283 | address from the TCB, to be used for local-exec TLS accesses. | |
aa137e4d | 284 | |
6f7be959 | 285 | @item hw0_last_tls_le |
aa137e4d | 286 | |
6f7be959 WL |
287 | This modifier yields the same value as @code{hw0_tls_le}, but it also |
288 | checks that the value does not overflow. | |
aa137e4d | 289 | |
6f7be959 | 290 | @item hw1_last_tls_le |
aa137e4d | 291 | |
6f7be959 WL |
292 | This modifier is used to load bits 16-31 of the offset of the symbol's |
293 | address from the TCB, to be used for local-exec TLS accesses. It | |
294 | also checks that the value does not overflow. | |
aa137e4d | 295 | |
6f7be959 | 296 | @item tls_gd_call |
aa137e4d | 297 | |
6f7be959 WL |
298 | This modifier is used to tag an instrution as the ``call'' part of a |
299 | calling sequence for a TLS GD reference of its operand. | |
aa137e4d | 300 | |
6f7be959 | 301 | @item tls_gd_add |
aa137e4d | 302 | |
6f7be959 WL |
303 | This modifier is used to tag an instruction as the ``add'' part of a |
304 | calling sequence for a TLS GD reference of its operand. | |
305 | ||
306 | @item tls_ie_load | |
307 | ||
308 | This modifier is used to tag an instruction as the ``load'' part of a | |
309 | calling sequence for a TLS IE reference of its operand. | |
aa137e4d NC |
310 | |
311 | @end table | |
312 | ||
313 | @node TILE-Gx Directives | |
314 | @section TILE-Gx Directives | |
315 | @cindex machine directives, TILE-Gx | |
316 | @cindex TILE-Gx machine directives | |
317 | ||
318 | @table @code | |
319 | ||
320 | @cindex @code{.align} directive, TILE-Gx | |
321 | @item .align @var{expression} [, @var{expression}] | |
322 | This is the generic @var{.align} directive. The first argument is the | |
323 | requested alignment in bytes. | |
324 | ||
325 | @cindex @code{.allow_suspicious_bundles} directive, TILE-Gx | |
326 | @item .allow_suspicious_bundles | |
327 | Turns on error checking for combinations of instructions in a bundle | |
328 | that probably indicate a programming error. This is on by default. | |
329 | ||
330 | @item .no_allow_suspicious_bundles | |
331 | Turns off error checking for combinations of instructions in a bundle | |
332 | that probably indicate a programming error. | |
333 | ||
334 | @cindex @code{.require_canonical_reg_names} directive, TILE-Gx | |
335 | @item .require_canonical_reg_names | |
336 | Require that canonical register names be used, and emit a warning if | |
337 | the numeric names are used. This is on by default. | |
338 | ||
339 | @item .no_require_canonical_reg_names | |
340 | Permit the use of numeric names for registers that have canonical | |
341 | names. | |
342 | ||
343 | @end table |