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f7e42eb4 | 1 | @c Copyright 1997 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | ||
5 | @node V850-Dependent | |
6 | @chapter v850 Dependent Features | |
7 | ||
8 | @cindex V850 support | |
9 | @menu | |
10 | * V850 Options:: Options | |
11 | * V850 Syntax:: Syntax | |
12 | * V850 Floating Point:: Floating Point | |
13 | * V850 Directives:: V850 Machine Directives | |
14 | * V850 Opcodes:: Opcodes | |
15 | @end menu | |
16 | ||
17 | @node V850 Options | |
18 | @section Options | |
19 | @cindex V850 options (none) | |
20 | @cindex options for V850 (none) | |
21 | @code{@value{AS}} supports the following additional command-line options | |
22 | for the V850 processor family: | |
23 | ||
24 | @cindex command line options, V850 | |
25 | @cindex V850 command line options | |
26 | @table @code | |
27 | ||
28 | @cindex @code{-wsigned_overflow} command line option, V850 | |
29 | @item -wsigned_overflow | |
30 | Causes warnings to be produced when signed immediate values overflow the | |
31 | space available for then within their opcodes. By default this option | |
32 | is disabled as it is possible to receive spurious warnings due to using | |
33 | exact bit patterns as immediate constants. | |
34 | ||
35 | @cindex @code{-wunsigned_overflow} command line option, V850 | |
36 | @item -wunsigned_overflow | |
37 | Causes warnings to be produced when unsigned immediate values overflow | |
38 | the space available for then within their opcodes. By default this | |
39 | option is disabled as it is possible to receive spurious warnings due to | |
40 | using exact bit patterns as immediate constants. | |
41 | ||
42 | @cindex @code{-mv850} command line option, V850 | |
43 | @item -mv850 | |
44 | Specifies that the assembled code should be marked as being targeted at | |
45 | the V850 processor. This allows the linker to detect attempts to link | |
46 | such code with code assembled for other processors. | |
47 | ||
48 | @cindex @code{-mv850e} command line option, V850 | |
49 | @item -mv850e | |
50 | Specifies that the assembled code should be marked as being targeted at | |
51 | the V850E processor. This allows the linker to detect attempts to link | |
52 | such code with code assembled for other processors. | |
53 | ||
54 | @cindex @code{-mv850any} command line option, V850 | |
55 | @item -mv850any | |
56 | Specifies that the assembled code should be marked as being targeted at | |
57 | the V850 processor but support instructions that are specific to the | |
58 | extended variants of the process. This allows the production of | |
59 | binaries that contain target specific code, but which are also intended | |
60 | to be used in a generic fashion. For example libgcc.a contains generic | |
61 | routines used by the code produced by GCC for all versions of the v850 | |
62 | architecture, together with support routines only used by the V850E | |
63 | architecture. | |
64 | ||
86aba9db NC |
65 | @cindex @code{-mrelax} command line option, V850 |
66 | @item -mrelax | |
67 | Enables relaxation. This allows the .longcall and .longjump pseudo | |
68 | ops to be used in the assembler source code. These ops label sections | |
69 | of code which are either a long function call or a long branch. The | |
70 | assembler will then flag these sections of code and the linker will | |
71 | attempt to relax them. | |
72 | ||
252b5132 RH |
73 | @end table |
74 | ||
75 | ||
76 | @node V850 Syntax | |
77 | @section Syntax | |
78 | @menu | |
79 | * V850-Chars:: Special Characters | |
80 | * V850-Regs:: Register Names | |
81 | @end menu | |
82 | ||
83 | @node V850-Chars | |
84 | @subsection Special Characters | |
85 | ||
86 | @cindex line comment character, V850 | |
87 | @cindex V850 line comment character | |
88 | @samp{#} is the line comment character. | |
89 | @node V850-Regs | |
90 | @subsection Register Names | |
91 | ||
92 | @cindex V850 register names | |
93 | @cindex register names, V850 | |
94 | @code{@value{AS}} supports the following names for registers: | |
95 | @table @code | |
96 | @cindex @code{zero} register, V850 | |
97 | @item general register 0 | |
98 | r0, zero | |
99 | @item general register 1 | |
100 | r1 | |
101 | @item general register 2 | |
102 | r2, hp | |
103 | @cindex @code{sp} register, V850 | |
104 | @item general register 3 | |
105 | r3, sp | |
106 | @cindex @code{gp} register, V850 | |
107 | @item general register 4 | |
108 | r4, gp | |
109 | @cindex @code{tp} register, V850 | |
110 | @item general register 5 | |
111 | r5, tp | |
112 | @item general register 6 | |
113 | r6 | |
114 | @item general register 7 | |
115 | r7 | |
116 | @item general register 8 | |
117 | r8 | |
118 | @item general register 9 | |
119 | r9 | |
120 | @item general register 10 | |
121 | r10 | |
122 | @item general register 11 | |
123 | r11 | |
124 | @item general register 12 | |
125 | r12 | |
126 | @item general register 13 | |
127 | r13 | |
128 | @item general register 14 | |
129 | r14 | |
130 | @item general register 15 | |
131 | r15 | |
132 | @item general register 16 | |
133 | r16 | |
134 | @item general register 17 | |
135 | r17 | |
136 | @item general register 18 | |
137 | r18 | |
138 | @item general register 19 | |
139 | r19 | |
140 | @item general register 20 | |
141 | r20 | |
142 | @item general register 21 | |
143 | r21 | |
144 | @item general register 22 | |
145 | r22 | |
146 | @item general register 23 | |
147 | r23 | |
148 | @item general register 24 | |
149 | r24 | |
150 | @item general register 25 | |
151 | r25 | |
152 | @item general register 26 | |
153 | r26 | |
154 | @item general register 27 | |
155 | r27 | |
156 | @item general register 28 | |
157 | r28 | |
158 | @item general register 29 | |
159 | r29 | |
160 | @cindex @code{ep} register, V850 | |
161 | @item general register 30 | |
162 | r30, ep | |
163 | @cindex @code{lp} register, V850 | |
164 | @item general register 31 | |
165 | r31, lp | |
166 | @cindex @code{eipc} register, V850 | |
167 | @item system register 0 | |
168 | eipc | |
169 | @cindex @code{eipsw} register, V850 | |
170 | @item system register 1 | |
171 | eipsw | |
172 | @cindex @code{fepc} register, V850 | |
173 | @item system register 2 | |
174 | fepc | |
175 | @cindex @code{fepsw} register, V850 | |
176 | @item system register 3 | |
177 | fepsw | |
178 | @cindex @code{ecr} register, V850 | |
179 | @item system register 4 | |
180 | ecr | |
181 | @cindex @code{psw} register, V850 | |
182 | @item system register 5 | |
183 | psw | |
184 | @cindex @code{ctpc} register, V850 | |
185 | @item system register 16 | |
186 | ctpc | |
187 | @cindex @code{ctpsw} register, V850 | |
188 | @item system register 17 | |
189 | ctpsw | |
190 | @cindex @code{dbpc} register, V850 | |
191 | @item system register 18 | |
192 | dbpc | |
193 | @cindex @code{dbpsw} register, V850 | |
194 | @item system register 19 | |
195 | dbpsw | |
196 | @cindex @code{ctbp} register, V850 | |
197 | @item system register 20 | |
198 | ctbp | |
199 | @end table | |
200 | ||
201 | @node V850 Floating Point | |
202 | @section Floating Point | |
203 | ||
204 | @cindex floating point, V850 (@sc{ieee}) | |
205 | @cindex V850 floating point (@sc{ieee}) | |
206 | The V850 family uses @sc{ieee} floating-point numbers. | |
207 | ||
208 | @node V850 Directives | |
209 | @section V850 Machine Directives | |
210 | ||
211 | @cindex machine directives, V850 | |
212 | @cindex V850 machine directives | |
213 | @table @code | |
214 | @cindex @code{offset} directive, V850 | |
215 | @item .offset @var{<expression>} | |
216 | Moves the offset into the current section to the specified amount. | |
217 | ||
218 | @cindex @code{section} directive, V850 | |
219 | @item .section "name", <type> | |
220 | This is an extension to the standard .section directive. It sets the | |
221 | current section to be <type> and creates an alias for this section | |
222 | called "name". | |
223 | ||
224 | @cindex @code{.v850} directive, V850 | |
225 | @item .v850 | |
226 | Specifies that the assembled code should be marked as being targeted at | |
227 | the V850 processor. This allows the linker to detect attempts to link | |
228 | such code with code assembled for other processors. | |
229 | ||
230 | @cindex @code{.v850e} directive, V850 | |
231 | @item .v850e | |
232 | Specifies that the assembled code should be marked as being targeted at | |
233 | the V850E processor. This allows the linker to detect attempts to link | |
234 | such code with code assembled for other processors. | |
235 | ||
236 | @end table | |
237 | ||
238 | @node V850 Opcodes | |
239 | @section Opcodes | |
240 | ||
241 | @cindex V850 opcodes | |
242 | @cindex opcodes for V850 | |
243 | @code{@value{AS}} implements all the standard V850 opcodes. | |
244 | ||
245 | @code{@value{AS}} also implements the following pseudo ops: | |
246 | ||
247 | @table @code | |
248 | ||
249 | @cindex @code{hi0} pseudo-op, V850 | |
250 | @item hi0() | |
251 | Computes the higher 16 bits of the given expression and stores it into | |
252 | the immediate operand field of the given instruction. For example: | |
253 | ||
254 | @samp{mulhi hi0(here - there), r5, r6} | |
255 | ||
256 | computes the difference between the address of labels 'here' and | |
257 | 'there', takes the upper 16 bits of this difference, shifts it down 16 | |
258 | bits and then mutliplies it by the lower 16 bits in register 5, putting | |
259 | the result into register 6. | |
260 | ||
261 | @cindex @code{lo} pseudo-op, V850 | |
262 | @item lo() | |
263 | Computes the lower 16 bits of the given expression and stores it into | |
264 | the immediate operand field of the given instruction. For example: | |
265 | ||
266 | @samp{addi lo(here - there), r5, r6} | |
267 | ||
268 | computes the difference between the address of labels 'here' and | |
269 | 'there', takes the lower 16 bits of this difference and adds it to | |
270 | register 5, putting the result into register 6. | |
271 | ||
272 | @cindex @code{hi} pseudo-op, V850 | |
273 | @item hi() | |
274 | Computes the higher 16 bits of the given expression and then adds the | |
275 | value of the most significant bit of the lower 16 bits of the expression | |
276 | and stores the result into the immediate operand field of the given | |
277 | instruction. For example the following code can be used to compute the | |
278 | address of the label 'here' and store it into register 6: | |
279 | ||
280 | @samp{movhi hi(here), r0, r6} | |
281 | @samp{movea lo(here), r6, r6} | |
282 | ||
283 | The reason for this special behaviour is that movea performs a sign | |
062b7c0c | 284 | extension on its immediate operand. So for example if the address of |
252b5132 RH |
285 | 'here' was 0xFFFFFFFF then without the special behaviour of the hi() |
286 | pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the | |
287 | movea instruction would takes its immediate operand, 0xFFFF, sign extend | |
288 | it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF | |
289 | which is wrong (the fifth nibble is E). With the hi() pseudo op adding | |
290 | in the top bit of the lo() pseudo op, the movhi instruction actually | |
291 | stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction | |
292 | stores 0xFFFFFFFF into r6 - the right value. | |
293 | ||
294 | @cindex @code{hilo} pseudo-op, V850 | |
295 | @item hilo() | |
296 | Computes the 32 bit value of the given expression and stores it into | |
297 | the immediate operand field of the given instruction (which must be a | |
298 | mov instruction). For example: | |
299 | ||
300 | @samp{mov hilo(here), r6} | |
301 | ||
302 | computes the absolute address of label 'here' and puts the result into | |
303 | register 6. | |
304 | ||
305 | @cindex @code{sdaoff} pseudo-op, V850 | |
306 | @item sdaoff() | |
307 | Computes the offset of the named variable from the start of the Small | |
308 | Data Area (whoes address is held in register 4, the GP register) and | |
309 | stores the result as a 16 bit signed value in the immediate operand | |
310 | field of the given instruction. For example: | |
311 | ||
312 | @samp{ld.w sdaoff(_a_variable)[gp],r6} | |
313 | ||
314 | loads the contents of the location pointed to by the label '_a_variable' | |
315 | into register 6, provided that the label is located somewhere within +/- | |
316 | 32K of the address held in the GP register. [Note the linker assumes | |
317 | that the GP register contains a fixed address set to the address of the | |
318 | label called '__gp'. This can either be set up automatically by the | |
319 | linker, or specifically set by using the @samp{--defsym __gp=<value>} | |
320 | command line option]. | |
321 | ||
322 | @cindex @code{tdaoff} pseudo-op, V850 | |
323 | @item tdaoff() | |
324 | Computes the offset of the named variable from the start of the Tiny | |
325 | Data Area (whoes address is held in register 30, the EP register) and | |
326 | stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate | |
327 | operand field of the given instruction. For example: | |
328 | ||
329 | @samp{sld.w tdaoff(_a_variable)[ep],r6} | |
330 | ||
331 | loads the contents of the location pointed to by the label '_a_variable' | |
332 | into register 6, provided that the label is located somewhere within +256 | |
333 | bytes of the address held in the EP register. [Note the linker assumes | |
334 | that the EP register contains a fixed address set to the address of the | |
335 | label called '__ep'. This can either be set up automatically by the | |
336 | linker, or specifically set by using the @samp{--defsym __ep=<value>} | |
337 | command line option]. | |
338 | ||
339 | @cindex @code{zdaoff} pseudo-op, V850 | |
340 | @item zdaoff() | |
341 | Computes the offset of the named variable from address 0 and stores the | |
342 | result as a 16 bit signed value in the immediate operand field of the | |
343 | given instruction. For example: | |
344 | ||
345 | @samp{movea zdaoff(_a_variable),zero,r6} | |
346 | ||
347 | puts the address of the label '_a_variable' into register 6, assuming | |
348 | that the label is somewhere within the first 32K of memory. (Strictly | |
349 | speaking it also possible to access the last 32K of memory as well, as | |
350 | the offsets are signed). | |
351 | ||
352 | @cindex @code{ctoff} pseudo-op, V850 | |
353 | @item ctoff() | |
354 | Computes the offset of the named variable from the start of the Call | |
355 | Table Area (whoes address is helg in system register 20, the CTBP | |
356 | register) and stores the result a 6 or 16 bit unsigned value in the | |
357 | immediate field of then given instruction or piece of data. For | |
358 | example: | |
359 | ||
360 | @samp{callt ctoff(table_func1)} | |
361 | ||
362 | will put the call the function whoes address is held in the call table | |
363 | at the location labeled 'table_func1'. | |
364 | ||
86aba9db NC |
365 | @cindex @code{longcall} pseudo-op, V850 |
366 | @item .longcall @code{name} | |
367 | Indicates that the following sequence of instructions is a long call | |
368 | to function @code{name}. The linker will attempt to shorten this call | |
369 | sequence if @code{name} is within a 22bit offset of the call. Only | |
370 | valid if the @code{-mrelax} command line switch has been enabled. | |
371 | ||
372 | @cindex @code{longjump} pseudo-op, V850 | |
373 | @item .longjump @code{name} | |
374 | Indicates that the following sequence of instructions is a long jump | |
375 | to label @code{name}. The linker will attempt to shorten this code | |
376 | sequence if @code{name} is within a 22bit offset of the jump. Only | |
377 | valid if the @code{-mrelax} command line switch has been enabled. | |
378 | ||
252b5132 RH |
379 | @end table |
380 | ||
381 | ||
382 | For information on the V850 instruction set, see @cite{V850 | |
383 | Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC. | |
384 | Ltd. |