Commit | Line | Data |
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252b5132 | 1 | /* itbl-ops.c |
2da5c037 AM |
2 | Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
22 | /*======================================================================*/ | |
23 | /* | |
24 | * Herein lies the support for dynamic specification of processor | |
25 | * instructions and registers. Mnemonics, values, and formats for each | |
26 | * instruction and register are specified in an ascii file consisting of | |
27 | * table entries. The grammar for the table is defined in the document | |
28 | * "Processor instruction table specification". | |
29 | * | |
30 | * Instructions use the gnu assembler syntax, with the addition of | |
31 | * allowing mnemonics for register. | |
32 | * Eg. "func $2,reg3,0x100,symbol ; comment" | |
33 | * func - opcode name | |
34 | * $n - register n | |
35 | * reg3 - mnemonic for processor's register defined in table | |
36 | * 0xddd..d - immediate value | |
37 | * symbol - address of label or external symbol | |
38 | * | |
39 | * First, itbl_parse reads in the table of register and instruction | |
40 | * names and formats, and builds a list of entries for each | |
41 | * processor/type combination. lex and yacc are used to parse | |
42 | * the entries in the table and call functions defined here to | |
43 | * add each entry to our list. | |
44 | * | |
45 | * Then, when assembling or disassembling, these functions are called to | |
46 | * 1) get information on a processor's registers and | |
47 | * 2) assemble/disassemble an instruction. | |
48 | * To assemble(disassemble) an instruction, the function | |
49 | * itbl_assemble(itbl_disassemble) is called to search the list of | |
50 | * instruction entries, and if a match is found, uses the format | |
51 | * described in the instruction entry structure to complete the action. | |
52 | * | |
53 | * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2" | |
54 | * and we want to define function "pig" which takes two operands. | |
55 | * | |
56 | * Given the table entries: | |
57 | * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0" | |
58 | * "p3 dreg d2 0x2" | |
59 | * and that the instruction encoding for coprocessor pz has encoding: | |
60 | * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25) | |
61 | * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum) | |
62 | * | |
63 | * a structure to describe the instruction might look something like: | |
64 | * struct itbl_entry = { | |
65 | * e_processor processor = e_p3 | |
66 | * e_type type = e_insn | |
67 | * char *name = "pig" | |
68 | * uint value = 0x1 | |
69 | * uint flags = 0 | |
70 | * struct itbl_range range = 24-21 | |
71 | * struct itbl_field *field = { | |
72 | * e_type type = e_dreg | |
73 | * struct itbl_range range = 20-16 | |
74 | * struct itbl_field *next = { | |
75 | * e_type type = e_immed | |
76 | * struct itbl_range range = 15-0 | |
77 | * struct itbl_field *next = 0 | |
78 | * }; | |
79 | * }; | |
80 | * struct itbl_entry *next = 0 | |
81 | * }; | |
82 | * | |
83 | * And the assembler instructions: | |
84 | * "pig d2,0x100" | |
85 | * "pig $2,0x100" | |
86 | * | |
87 | * would both assemble to the hex value: | |
88 | * "0x4e220100" | |
89 | * | |
90 | */ | |
91 | ||
92 | #include <stdio.h> | |
93 | #include <stdlib.h> | |
94 | #include <string.h> | |
95 | #include "itbl-ops.h" | |
3d82a647 | 96 | #include <itbl-parse.h> |
252b5132 RH |
97 | |
98 | /* #define DEBUG */ | |
99 | ||
100 | #ifdef DEBUG | |
101 | #include <assert.h> | |
102 | #define ASSERT(x) assert(x) | |
103 | #define DBG(x) printf x | |
104 | #else | |
105 | #define ASSERT(x) | |
106 | #define DBG(x) | |
107 | #endif | |
108 | ||
109 | #ifndef min | |
110 | #define min(a,b) (a<b?a:b) | |
111 | #endif | |
112 | ||
113 | int itbl_have_entries = 0; | |
114 | ||
115 | /*======================================================================*/ | |
116 | /* structures for keeping itbl format entries */ | |
117 | ||
ef99799a KH |
118 | struct itbl_range { |
119 | int sbit; /* mask starting bit position */ | |
120 | int ebit; /* mask ending bit position */ | |
121 | }; | |
122 | ||
123 | struct itbl_field { | |
124 | e_type type; /* dreg/creg/greg/immed/symb */ | |
125 | struct itbl_range range; /* field's bitfield range within instruction */ | |
126 | unsigned long flags; /* field flags */ | |
127 | struct itbl_field *next; /* next field in list */ | |
128 | }; | |
252b5132 | 129 | |
252b5132 RH |
130 | /* These structures define the instructions and registers for a processor. |
131 | * If the type is an instruction, the structure defines the format of an | |
132 | * instruction where the fields are the list of operands. | |
133 | * The flags field below uses the same values as those defined in the | |
c488923f | 134 | * gnu assembler and are machine specific. */ |
ef99799a KH |
135 | struct itbl_entry { |
136 | e_processor processor; /* processor number */ | |
137 | e_type type; /* dreg/creg/greg/insn */ | |
138 | char *name; /* mnemionic name for insn/register */ | |
139 | unsigned long value; /* opcode/instruction mask/register number */ | |
140 | unsigned long flags; /* effects of the instruction */ | |
141 | struct itbl_range range; /* bit range within instruction for value */ | |
142 | struct itbl_field *fields; /* list of operand definitions (if any) */ | |
143 | struct itbl_entry *next; /* next entry */ | |
144 | }; | |
252b5132 | 145 | |
252b5132 RH |
146 | /* local data and structures */ |
147 | ||
148 | static int itbl_num_opcodes = 0; | |
149 | /* Array of entries for each processor and entry type */ | |
ef99799a | 150 | static struct itbl_entry *entries[e_nprocs][e_ntypes] = { |
252b5132 RH |
151 | {0, 0, 0, 0, 0, 0}, |
152 | {0, 0, 0, 0, 0, 0}, | |
153 | {0, 0, 0, 0, 0, 0}, | |
154 | {0, 0, 0, 0, 0, 0} | |
155 | }; | |
156 | ||
157 | /* local prototypes */ | |
b1f1fa96 KH |
158 | static unsigned long build_opcode (struct itbl_entry *e); |
159 | static e_type get_type (int yytype); | |
160 | static e_processor get_processor (int yyproc); | |
161 | static struct itbl_entry **get_entries (e_processor processor, | |
162 | e_type type); | |
163 | static struct itbl_entry *find_entry_byname (e_processor processor, | |
164 | e_type type, char *name); | |
165 | static struct itbl_entry *find_entry_byval (e_processor processor, | |
166 | e_type type, unsigned long val, struct itbl_range *r); | |
167 | static struct itbl_entry *alloc_entry (e_processor processor, | |
168 | e_type type, char *name, unsigned long value); | |
169 | static unsigned long apply_range (unsigned long value, struct itbl_range r); | |
170 | static unsigned long extract_range (unsigned long value, struct itbl_range r); | |
171 | static struct itbl_field *alloc_field (e_type type, int sbit, | |
172 | int ebit, unsigned long flags); | |
252b5132 | 173 | |
252b5132 RH |
174 | /*======================================================================*/ |
175 | /* Interfaces to the parser */ | |
176 | ||
252b5132 RH |
177 | /* Open the table and use lex and yacc to parse the entries. |
178 | * Return 1 for failure; 0 for success. */ | |
179 | ||
c488923f | 180 | int |
252b5132 RH |
181 | itbl_parse (char *insntbl) |
182 | { | |
183 | extern FILE *yyin; | |
184 | extern int yyparse (void); | |
f740e790 NC |
185 | |
186 | yyin = fopen (insntbl, FOPEN_RT); | |
252b5132 RH |
187 | if (yyin == 0) |
188 | { | |
189 | printf ("Can't open processor instruction specification file \"%s\"\n", | |
190 | insntbl); | |
191 | return 1; | |
192 | } | |
f740e790 NC |
193 | |
194 | while (yyparse ()) | |
195 | ; | |
196 | ||
252b5132 RH |
197 | fclose (yyin); |
198 | itbl_have_entries = 1; | |
199 | return 0; | |
200 | } | |
201 | ||
202 | /* Add a register entry */ | |
203 | ||
204 | struct itbl_entry * | |
205 | itbl_add_reg (int yyprocessor, int yytype, char *regname, | |
206 | int regnum) | |
207 | { | |
252b5132 RH |
208 | return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname, |
209 | (unsigned long) regnum); | |
210 | } | |
211 | ||
212 | /* Add an instruction entry */ | |
213 | ||
214 | struct itbl_entry * | |
215 | itbl_add_insn (int yyprocessor, char *name, unsigned long value, | |
216 | int sbit, int ebit, unsigned long flags) | |
217 | { | |
218 | struct itbl_entry *e; | |
219 | e = alloc_entry (get_processor (yyprocessor), e_insn, name, value); | |
220 | if (e) | |
221 | { | |
222 | e->range.sbit = sbit; | |
223 | e->range.ebit = ebit; | |
224 | e->flags = flags; | |
225 | itbl_num_opcodes++; | |
226 | } | |
227 | return e; | |
228 | } | |
229 | ||
230 | /* Add an operand to an instruction entry */ | |
231 | ||
232 | struct itbl_field * | |
233 | itbl_add_operand (struct itbl_entry *e, int yytype, int sbit, | |
234 | int ebit, unsigned long flags) | |
235 | { | |
236 | struct itbl_field *f, **last_f; | |
237 | if (!e) | |
238 | return 0; | |
c488923f | 239 | /* Add to end of fields' list. */ |
252b5132 RH |
240 | f = alloc_field (get_type (yytype), sbit, ebit, flags); |
241 | if (f) | |
242 | { | |
243 | last_f = &e->fields; | |
244 | while (*last_f) | |
245 | last_f = &(*last_f)->next; | |
246 | *last_f = f; | |
247 | f->next = 0; | |
248 | } | |
249 | return f; | |
250 | } | |
251 | ||
252b5132 RH |
252 | /*======================================================================*/ |
253 | /* Interfaces for assembler and disassembler */ | |
254 | ||
255 | #ifndef STAND_ALONE | |
256 | #include "as.h" | |
257 | #include "symbols.h" | |
258 | static void append_insns_as_macros (void); | |
259 | ||
ef99799a KH |
260 | /* Initialize for gas. */ |
261 | ||
c488923f | 262 | void |
252b5132 RH |
263 | itbl_init (void) |
264 | { | |
265 | struct itbl_entry *e, **es; | |
266 | e_processor procn; | |
267 | e_type type; | |
268 | ||
269 | if (!itbl_have_entries) | |
ef99799a | 270 | return; |
252b5132 RH |
271 | |
272 | /* Since register names don't have a prefix, put them in the symbol table so | |
273 | they can't be used as symbols. This simplifies argument parsing as | |
c488923f | 274 | we can let gas parse registers for us. */ |
252b5132 RH |
275 | /* Use symbol_create instead of symbol_new so we don't try to |
276 | output registers into the object file's symbol table. */ | |
277 | ||
278 | for (type = e_regtype0; type < e_nregtypes; type++) | |
279 | for (procn = e_p0; procn < e_nprocs; procn++) | |
280 | { | |
281 | es = get_entries (procn, type); | |
282 | for (e = *es; e; e = e->next) | |
283 | { | |
284 | symbol_table_insert (symbol_create (e->name, reg_section, | |
ef99799a | 285 | e->value, &zero_address_frag)); |
252b5132 RH |
286 | } |
287 | } | |
288 | append_insns_as_macros (); | |
289 | } | |
290 | ||
c488923f KH |
291 | /* Append insns to opcodes table and increase number of opcodes |
292 | * Structure of opcodes table: | |
252b5132 RH |
293 | * struct itbl_opcode |
294 | * { | |
295 | * const char *name; | |
c488923f KH |
296 | * const char *args; - string describing the arguments. |
297 | * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO | |
298 | * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO | |
299 | * unsigned long pinfo; - insn flags, or INSN_MACRO | |
252b5132 RH |
300 | * }; |
301 | * examples: | |
302 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, | |
303 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, | |
304 | */ | |
305 | ||
306 | static char *form_args (struct itbl_entry *e); | |
c488923f | 307 | static void |
252b5132 RH |
308 | append_insns_as_macros (void) |
309 | { | |
310 | struct ITBL_OPCODE_STRUCT *new_opcodes, *o; | |
311 | struct itbl_entry *e, **es; | |
312 | int n, id, size, new_size, new_num_opcodes; | |
313 | ||
314 | if (!itbl_have_entries) | |
ef99799a | 315 | return; |
252b5132 RH |
316 | |
317 | if (!itbl_num_opcodes) /* no new instructions to add! */ | |
318 | { | |
319 | return; | |
320 | } | |
321 | DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES)); | |
322 | ||
323 | new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes; | |
324 | ASSERT (new_num_opcodes >= itbl_num_opcodes); | |
325 | ||
326 | size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES; | |
327 | ASSERT (size >= 0); | |
328 | DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0]))); | |
329 | ||
330 | new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes; | |
331 | ASSERT (new_size > size); | |
332 | ||
333 | /* FIXME since ITBL_OPCODES culd be a static table, | |
c488923f | 334 | we can't realloc or delete the old memory. */ |
252b5132 RH |
335 | new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size); |
336 | if (!new_opcodes) | |
337 | { | |
338 | printf (_("Unable to allocate memory for new instructions\n")); | |
339 | return; | |
340 | } | |
47eebc20 | 341 | if (size) /* copy preexisting opcodes table */ |
252b5132 RH |
342 | memcpy (new_opcodes, ITBL_OPCODES, size); |
343 | ||
344 | /* FIXME! some NUMOPCODES are calculated expressions. | |
c488923f | 345 | These need to be changed before itbls can be supported. */ |
252b5132 RH |
346 | |
347 | id = ITBL_NUM_MACROS; /* begin the next macro id after the last */ | |
348 | o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */ | |
349 | for (n = e_p0; n < e_nprocs; n++) | |
350 | { | |
351 | es = get_entries (n, e_insn); | |
352 | for (e = *es; e; e = e->next) | |
353 | { | |
354 | /* name, args, mask, match, pinfo | |
355 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, | |
356 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, | |
357 | * Construct args from itbl_fields. | |
358 | */ | |
359 | o->name = e->name; | |
360 | o->args = strdup (form_args (e)); | |
361 | o->mask = apply_range (e->value, e->range); | |
47eebc20 | 362 | /* FIXME how to catch during assembly? */ |
252b5132 RH |
363 | /* mask to identify this insn */ |
364 | o->match = apply_range (e->value, e->range); | |
365 | o->pinfo = 0; | |
366 | ||
367 | #ifdef USE_MACROS | |
47eebc20 | 368 | o->mask = id++; /* FIXME how to catch during assembly? */ |
252b5132 RH |
369 | o->match = 0; /* for macros, the insn_isa number */ |
370 | o->pinfo = INSN_MACRO; | |
371 | #endif | |
372 | ||
373 | /* Don't add instructions which caused an error */ | |
374 | if (o->args) | |
375 | o++; | |
376 | else | |
377 | new_num_opcodes--; | |
378 | } | |
379 | } | |
380 | ITBL_OPCODES = new_opcodes; | |
381 | ITBL_NUM_OPCODES = new_num_opcodes; | |
382 | ||
383 | /* FIXME | |
384 | At this point, we can free the entries, as they should have | |
385 | been added to the assembler's tables. | |
386 | Don't free name though, since name is being used by the new | |
387 | opcodes table. | |
388 | ||
c488923f | 389 | Eventually, we should also free the new opcodes table itself |
252b5132 RH |
390 | on exit. |
391 | */ | |
392 | } | |
393 | ||
394 | static char * | |
395 | form_args (struct itbl_entry *e) | |
396 | { | |
397 | static char s[31]; | |
398 | char c = 0, *p = s; | |
399 | struct itbl_field *f; | |
400 | ||
401 | ASSERT (e); | |
402 | for (f = e->fields; f; f = f->next) | |
403 | { | |
404 | switch (f->type) | |
405 | { | |
406 | case e_dreg: | |
407 | c = 'd'; | |
408 | break; | |
409 | case e_creg: | |
410 | c = 't'; | |
411 | break; | |
412 | case e_greg: | |
413 | c = 's'; | |
414 | break; | |
415 | case e_immed: | |
416 | c = 'i'; | |
417 | break; | |
418 | case e_addr: | |
419 | c = 'a'; | |
420 | break; | |
421 | default: | |
422 | c = 0; /* ignore; unknown field type */ | |
423 | } | |
424 | if (c) | |
425 | { | |
426 | if (p != s) | |
427 | *p++ = ','; | |
428 | *p++ = c; | |
429 | } | |
430 | } | |
431 | *p = 0; | |
432 | return s; | |
433 | } | |
434 | #endif /* !STAND_ALONE */ | |
435 | ||
252b5132 RH |
436 | /* Get processor's register name from val */ |
437 | ||
d7ba4a77 ILT |
438 | int |
439 | itbl_get_reg_val (char *name, unsigned long *pval) | |
252b5132 RH |
440 | { |
441 | e_type t; | |
442 | e_processor p; | |
d7ba4a77 | 443 | |
252b5132 | 444 | for (p = e_p0; p < e_nprocs; p++) |
d7ba4a77 ILT |
445 | { |
446 | for (t = e_regtype0; t < e_nregtypes; t++) | |
447 | { | |
448 | if (itbl_get_val (p, t, name, pval)) | |
449 | return 1; | |
450 | } | |
451 | } | |
252b5132 RH |
452 | return 0; |
453 | } | |
454 | ||
455 | char * | |
456 | itbl_get_name (e_processor processor, e_type type, unsigned long val) | |
457 | { | |
458 | struct itbl_entry *r; | |
459 | /* type depends on instruction passed */ | |
460 | r = find_entry_byval (processor, type, val, 0); | |
461 | if (r) | |
462 | return r->name; | |
463 | else | |
464 | return 0; /* error; invalid operand */ | |
465 | } | |
466 | ||
467 | /* Get processor's register value from name */ | |
468 | ||
d7ba4a77 ILT |
469 | int |
470 | itbl_get_val (e_processor processor, e_type type, char *name, | |
471 | unsigned long *pval) | |
252b5132 RH |
472 | { |
473 | struct itbl_entry *r; | |
474 | /* type depends on instruction passed */ | |
475 | r = find_entry_byname (processor, type, name); | |
d7ba4a77 ILT |
476 | if (r == NULL) |
477 | return 0; | |
478 | *pval = r->value; | |
479 | return 1; | |
252b5132 RH |
480 | } |
481 | ||
252b5132 RH |
482 | /* Assemble instruction "name" with operands "s". |
483 | * name - name of instruction | |
484 | * s - operands | |
485 | * returns - long word for assembled instruction */ | |
486 | ||
c488923f | 487 | unsigned long |
252b5132 RH |
488 | itbl_assemble (char *name, char *s) |
489 | { | |
490 | unsigned long opcode; | |
3438adb3 | 491 | struct itbl_entry *e = NULL; |
252b5132 RH |
492 | struct itbl_field *f; |
493 | char *n; | |
494 | int processor; | |
495 | ||
496 | if (!name || !*name) | |
3b37fd66 | 497 | return 0; /* error! must have an opcode name/expr */ |
252b5132 RH |
498 | |
499 | /* find entry in list of instructions for all processors */ | |
500 | for (processor = 0; processor < e_nprocs; processor++) | |
501 | { | |
502 | e = find_entry_byname (processor, e_insn, name); | |
503 | if (e) | |
504 | break; | |
505 | } | |
506 | if (!e) | |
ef5c4bfc | 507 | return 0; /* opcode not in table; invalid instruction */ |
252b5132 RH |
508 | opcode = build_opcode (e); |
509 | ||
510 | /* parse opcode's args (if any) */ | |
c488923f | 511 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ |
252b5132 RH |
512 | { |
513 | struct itbl_entry *r; | |
514 | unsigned long value; | |
515 | if (!s || !*s) | |
516 | return 0; /* error - not enough operands */ | |
517 | n = itbl_get_field (&s); | |
518 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ | |
519 | switch (f->type) | |
520 | { | |
521 | case e_dreg: | |
522 | case e_creg: | |
523 | case e_greg: | |
524 | /* Accept either a string name | |
525 | * or '$' followed by the register number */ | |
526 | if (*n == '$') | |
527 | { | |
528 | n++; | |
529 | value = strtol (n, 0, 10); | |
530 | /* FIXME! could have "0l"... then what?? */ | |
531 | if (value == 0 && *n != '0') | |
532 | return 0; /* error; invalid operand */ | |
533 | } | |
534 | else | |
535 | { | |
536 | r = find_entry_byname (e->processor, f->type, n); | |
537 | if (r) | |
538 | value = r->value; | |
539 | else | |
540 | return 0; /* error; invalid operand */ | |
541 | } | |
542 | break; | |
543 | case e_addr: | |
544 | /* use assembler's symbol table to find symbol */ | |
545 | /* FIXME!! Do we need this? | |
546 | if so, what about relocs?? | |
547 | my_getExpression (&imm_expr, s); | |
548 | return 0; /-* error; invalid operand *-/ | |
549 | break; | |
550 | */ | |
551 | /* If not a symbol, fall thru to IMMED */ | |
552 | case e_immed: | |
c488923f | 553 | if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */ |
252b5132 RH |
554 | { |
555 | n += 2; | |
556 | value = strtol (n, 0, 16); | |
557 | /* FIXME! could have "0xl"... then what?? */ | |
558 | } | |
559 | else | |
560 | { | |
561 | value = strtol (n, 0, 10); | |
562 | /* FIXME! could have "0l"... then what?? */ | |
563 | if (value == 0 && *n != '0') | |
564 | return 0; /* error; invalid operand */ | |
565 | } | |
566 | break; | |
567 | default: | |
568 | return 0; /* error; invalid field spec */ | |
569 | } | |
570 | opcode |= apply_range (value, f->range); | |
571 | } | |
572 | if (s && *s) | |
573 | return 0; /* error - too many operands */ | |
574 | return opcode; /* done! */ | |
575 | } | |
576 | ||
577 | /* Disassemble instruction "insn". | |
578 | * insn - instruction | |
579 | * s - buffer to hold disassembled instruction | |
580 | * returns - 1 if succeeded; 0 if failed | |
581 | */ | |
582 | ||
c488923f | 583 | int |
252b5132 RH |
584 | itbl_disassemble (char *s, unsigned long insn) |
585 | { | |
586 | e_processor processor; | |
587 | struct itbl_entry *e; | |
588 | struct itbl_field *f; | |
589 | ||
590 | if (!ITBL_IS_INSN (insn)) | |
ef99799a | 591 | return 0; /* error */ |
252b5132 RH |
592 | processor = get_processor (ITBL_DECODE_PNUM (insn)); |
593 | ||
594 | /* find entry in list */ | |
595 | e = find_entry_byval (processor, e_insn, insn, 0); | |
596 | if (!e) | |
ef5c4bfc | 597 | return 0; /* opcode not in table; invalid instruction */ |
252b5132 RH |
598 | strcpy (s, e->name); |
599 | ||
ef99799a | 600 | /* Parse insn's args (if any). */ |
c488923f | 601 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ |
252b5132 RH |
602 | { |
603 | struct itbl_entry *r; | |
604 | unsigned long value; | |
605 | ||
47eebc20 | 606 | if (f == e->fields) /* First operand is preceded by tab. */ |
252b5132 | 607 | strcat (s, "\t"); |
ef99799a | 608 | else /* ','s separate following operands. */ |
252b5132 RH |
609 | strcat (s, ","); |
610 | value = extract_range (insn, f->range); | |
611 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ | |
612 | switch (f->type) | |
613 | { | |
614 | case e_dreg: | |
615 | case e_creg: | |
616 | case e_greg: | |
617 | /* Accept either a string name | |
ef99799a | 618 | or '$' followed by the register number. */ |
252b5132 RH |
619 | r = find_entry_byval (e->processor, f->type, value, &f->range); |
620 | if (r) | |
621 | strcat (s, r->name); | |
622 | else | |
41e60a82 | 623 | sprintf (s, "%s$%lu", s, value); |
252b5132 RH |
624 | break; |
625 | case e_addr: | |
ef99799a KH |
626 | /* Use assembler's symbol table to find symbol. */ |
627 | /* FIXME!! Do we need this? If so, what about relocs?? */ | |
628 | /* If not a symbol, fall through to IMMED. */ | |
252b5132 | 629 | case e_immed: |
41e60a82 | 630 | sprintf (s, "%s0x%lx", s, value); |
252b5132 RH |
631 | break; |
632 | default: | |
633 | return 0; /* error; invalid field spec */ | |
634 | } | |
635 | } | |
ef99799a | 636 | return 1; /* Done! */ |
252b5132 RH |
637 | } |
638 | ||
639 | /*======================================================================*/ | |
640 | /* | |
641 | * Local functions for manipulating private structures containing | |
642 | * the names and format for the new instructions and registers | |
643 | * for each processor. | |
644 | */ | |
645 | ||
646 | /* Calculate instruction's opcode and function values from entry */ | |
647 | ||
c488923f | 648 | static unsigned long |
252b5132 RH |
649 | build_opcode (struct itbl_entry *e) |
650 | { | |
651 | unsigned long opcode; | |
652 | ||
653 | opcode = apply_range (e->value, e->range); | |
654 | opcode |= ITBL_ENCODE_PNUM (e->processor); | |
655 | return opcode; | |
656 | } | |
657 | ||
658 | /* Calculate absolute value given the relative value and bit position range | |
659 | * within the instruction. | |
660 | * The range is inclusive where 0 is least significant bit. | |
661 | * A range of { 24, 20 } will have a mask of | |
662 | * bit 3 2 1 | |
663 | * pos: 1098 7654 3210 9876 5432 1098 7654 3210 | |
664 | * bin: 0000 0001 1111 0000 0000 0000 0000 0000 | |
665 | * hex: 0 1 f 0 0 0 0 0 | |
666 | * mask: 0x01f00000. | |
667 | */ | |
668 | ||
c488923f | 669 | static unsigned long |
252b5132 RH |
670 | apply_range (unsigned long rval, struct itbl_range r) |
671 | { | |
672 | unsigned long mask; | |
673 | unsigned long aval; | |
674 | int len = MAX_BITPOS - r.sbit; | |
675 | ||
676 | ASSERT (r.sbit >= r.ebit); | |
677 | ASSERT (MAX_BITPOS >= r.sbit); | |
678 | ASSERT (r.ebit >= 0); | |
679 | ||
680 | /* create mask by truncating 1s by shifting */ | |
681 | mask = 0xffffffff << len; | |
682 | mask = mask >> len; | |
683 | mask = mask >> r.ebit; | |
684 | mask = mask << r.ebit; | |
685 | ||
686 | aval = (rval << r.ebit) & mask; | |
687 | return aval; | |
688 | } | |
689 | ||
690 | /* Calculate relative value given the absolute value and bit position range | |
691 | * within the instruction. */ | |
692 | ||
c488923f | 693 | static unsigned long |
252b5132 RH |
694 | extract_range (unsigned long aval, struct itbl_range r) |
695 | { | |
696 | unsigned long mask; | |
697 | unsigned long rval; | |
698 | int len = MAX_BITPOS - r.sbit; | |
699 | ||
700 | /* create mask by truncating 1s by shifting */ | |
701 | mask = 0xffffffff << len; | |
702 | mask = mask >> len; | |
703 | mask = mask >> r.ebit; | |
704 | mask = mask << r.ebit; | |
705 | ||
706 | rval = (aval & mask) >> r.ebit; | |
707 | return rval; | |
708 | } | |
709 | ||
710 | /* Extract processor's assembly instruction field name from s; | |
711 | * forms are "n args" "n,args" or "n" */ | |
712 | /* Return next argument from string pointer "s" and advance s. | |
d7ba4a77 | 713 | * delimiters are " ,()" */ |
252b5132 RH |
714 | |
715 | char * | |
716 | itbl_get_field (char **S) | |
717 | { | |
718 | static char n[128]; | |
41e60a82 | 719 | char *s; |
252b5132 RH |
720 | int len; |
721 | ||
722 | s = *S; | |
723 | if (!s || !*s) | |
724 | return 0; | |
d7ba4a77 ILT |
725 | /* FIXME: This is a weird set of delimiters. */ |
726 | len = strcspn (s, " \t,()"); | |
252b5132 RH |
727 | ASSERT (128 > len + 1); |
728 | strncpy (n, s, len); | |
729 | n[len] = 0; | |
730 | if (s[len] == '\0') | |
731 | s = 0; /* no more args */ | |
732 | else | |
733 | s += len + 1; /* advance to next arg */ | |
734 | ||
735 | *S = s; | |
736 | return n; | |
737 | } | |
738 | ||
739 | /* Search entries for a given processor and type | |
740 | * to find one matching the name "n". | |
741 | * Return a pointer to the entry */ | |
742 | ||
743 | static struct itbl_entry * | |
744 | find_entry_byname (e_processor processor, | |
745 | e_type type, char *n) | |
746 | { | |
747 | struct itbl_entry *e, **es; | |
748 | ||
749 | es = get_entries (processor, type); | |
c488923f | 750 | for (e = *es; e; e = e->next) /* for each entry, ... */ |
252b5132 RH |
751 | { |
752 | if (!strcmp (e->name, n)) | |
753 | return e; | |
754 | } | |
755 | return 0; | |
756 | } | |
757 | ||
758 | /* Search entries for a given processor and type | |
759 | * to find one matching the value "val" for the range "r". | |
760 | * Return a pointer to the entry. | |
761 | * This function is used for disassembling fields of an instruction. | |
762 | */ | |
763 | ||
764 | static struct itbl_entry * | |
765 | find_entry_byval (e_processor processor, e_type type, | |
766 | unsigned long val, struct itbl_range *r) | |
767 | { | |
768 | struct itbl_entry *e, **es; | |
769 | unsigned long eval; | |
770 | ||
771 | es = get_entries (processor, type); | |
c488923f | 772 | for (e = *es; e; e = e->next) /* for each entry, ... */ |
252b5132 RH |
773 | { |
774 | if (processor != e->processor) | |
775 | continue; | |
776 | /* For insns, we might not know the range of the opcode, | |
777 | * so a range of 0 will allow this routine to match against | |
778 | * the range of the entry to be compared with. | |
779 | * This could cause ambiguities. | |
780 | * For operands, we get an extracted value and a range. | |
781 | */ | |
c488923f | 782 | /* if range is 0, mask val against the range of the compared entry. */ |
252b5132 RH |
783 | if (r == 0) /* if no range passed, must be whole 32-bits |
784 | * so create 32-bit value from entry's range */ | |
785 | { | |
786 | eval = apply_range (e->value, e->range); | |
787 | val &= apply_range (0xffffffff, e->range); | |
788 | } | |
41e60a82 ILT |
789 | else if ((r->sbit == e->range.sbit && r->ebit == e->range.ebit) |
790 | || (e->range.sbit == 0 && e->range.ebit == 0)) | |
252b5132 RH |
791 | { |
792 | eval = apply_range (e->value, *r); | |
793 | val = apply_range (val, *r); | |
794 | } | |
795 | else | |
796 | continue; | |
797 | if (val == eval) | |
798 | return e; | |
799 | } | |
800 | return 0; | |
801 | } | |
802 | ||
c488923f | 803 | /* Return a pointer to the list of entries for a given processor and type. */ |
252b5132 RH |
804 | |
805 | static struct itbl_entry ** | |
806 | get_entries (e_processor processor, e_type type) | |
807 | { | |
808 | return &entries[processor][type]; | |
809 | } | |
810 | ||
c488923f | 811 | /* Return an integral value for the processor passed from yyparse. */ |
252b5132 | 812 | |
c488923f | 813 | static e_processor |
252b5132 RH |
814 | get_processor (int yyproc) |
815 | { | |
816 | /* translate from yacc's processor to enum */ | |
817 | if (yyproc >= e_p0 && yyproc < e_nprocs) | |
818 | return (e_processor) yyproc; | |
819 | return e_invproc; /* error; invalid processor */ | |
820 | } | |
821 | ||
c488923f | 822 | /* Return an integral value for the entry type passed from yyparse. */ |
252b5132 | 823 | |
c488923f | 824 | static e_type |
252b5132 RH |
825 | get_type (int yytype) |
826 | { | |
827 | switch (yytype) | |
828 | { | |
829 | /* translate from yacc's type to enum */ | |
830 | case INSN: | |
831 | return e_insn; | |
832 | case DREG: | |
833 | return e_dreg; | |
834 | case CREG: | |
835 | return e_creg; | |
836 | case GREG: | |
837 | return e_greg; | |
838 | case ADDR: | |
839 | return e_addr; | |
840 | case IMMED: | |
841 | return e_immed; | |
842 | default: | |
843 | return e_invtype; /* error; invalid type */ | |
844 | } | |
845 | } | |
846 | ||
252b5132 RH |
847 | /* Allocate and initialize an entry */ |
848 | ||
849 | static struct itbl_entry * | |
850 | alloc_entry (e_processor processor, e_type type, | |
851 | char *name, unsigned long value) | |
852 | { | |
853 | struct itbl_entry *e, **es; | |
854 | if (!name) | |
855 | return 0; | |
856 | e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry)); | |
857 | if (e) | |
858 | { | |
859 | memset (e, 0, sizeof (struct itbl_entry)); | |
860 | e->name = (char *) malloc (sizeof (strlen (name)) + 1); | |
861 | if (e->name) | |
862 | strcpy (e->name, name); | |
863 | e->processor = processor; | |
864 | e->type = type; | |
865 | e->value = value; | |
866 | es = get_entries (e->processor, e->type); | |
867 | e->next = *es; | |
868 | *es = e; | |
869 | } | |
870 | return e; | |
871 | } | |
872 | ||
873 | /* Allocate and initialize an entry's field */ | |
874 | ||
875 | static struct itbl_field * | |
876 | alloc_field (e_type type, int sbit, int ebit, | |
877 | unsigned long flags) | |
878 | { | |
879 | struct itbl_field *f; | |
880 | f = (struct itbl_field *) malloc (sizeof (struct itbl_field)); | |
881 | if (f) | |
882 | { | |
883 | memset (f, 0, sizeof (struct itbl_field)); | |
884 | f->type = type; | |
885 | f->range.sbit = sbit; | |
886 | f->range.ebit = ebit; | |
887 | f->flags = flags; | |
888 | } | |
889 | return f; | |
890 | } |