[AArch64] PR target/20553, fix opcode mask for SIMD multiply by element
[deliverable/binutils-gdb.git] / gas / testsuite / gas / aarch64 / advsimd-fp16.s
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1/* simdhp.s Test file for AArch64 half-precision floating-point
2 vector instructions. */
3
4 /* Vector three-same. */
5
6 .macro three_same, op
7 \op v1.2d, v2.2d, v3.2d
8 \op v1.2s, v2.2s, v3.2s
9 \op v1.4s, v2.4s, v3.4s
10 \op v0.4h, v0.4h, v0.4h
11 \op v1.4h, v2.4h, v3.4h
12 \op v0.8h, v0.8h, v0.8h
13 \op v1.8h, v2.8h, v3.8h
14 .endm
15
16 .text
17
18 three_same fmaxnm
19 three_same fmaxnmp
20 three_same fminnm
21 three_same fminnmp
22 three_same fmla
23 three_same fmls
24 three_same fadd
25 three_same faddp
26 three_same fsub
27 three_same fmulx
28 three_same fmul
29 three_same fcmeq
30 three_same fcmge
31 three_same fcmgt
32 three_same facge
33 three_same facgt
34 three_same fmax
35 three_same fmaxp
36 three_same fmin
37 three_same fminp
38 three_same frecps
39 three_same fdiv
40 three_same frsqrts
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41
42 /* Scalar three-same. */
43
44 .macro sthree_same, op
45 \op d0, d1, d2
46 \op s0, s1, s2
47 \op h0, h1, h2
48 \op h0, h0, h0
49 .endm
50
51 sthree_same fabd
52 sthree_same fmulx
53 sthree_same fcmeq
54 sthree_same fcmgt
55 sthree_same fcmge
56 sthree_same facge
57 sthree_same facgt
58 sthree_same frecps
59 sthree_same frsqrts
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60
61 /* Vector two-register misc. */
62
63 .macro tworeg_zero, op
64 \op v0.2d, v1.2d, #0.0
65 \op v0.2s, v1.2s, #0.0
66 \op v0.4s, v1.4s, #0.0
67 \op v0.4h, v1.4h, #0.0
68 \op v0.8h, v1.8h, #0.0
69 .endm
70
71 tworeg_zero fcmgt
72 tworeg_zero fcmge
73 tworeg_zero fcmeq
74 tworeg_zero fcmle
75 tworeg_zero fcmlt
76
77 .macro tworeg_misc, op
78 \op v0.2d, v1.2d
79 \op v0.2s, v1.2s
80 \op v0.4s, v1.4s
81 \op v0.4h, v1.4h
82 \op v0.8h, v1.8h
83 .endm
84
85 tworeg_misc fabs
86 tworeg_misc fneg
87
88 tworeg_misc frintn
89 tworeg_misc frinta
90 tworeg_misc frintp
91
92 tworeg_misc frintm
93 tworeg_misc frintx
94 tworeg_misc frintz
95 tworeg_misc frinti
96
97 tworeg_misc fcvtns
98 tworeg_misc fcvtnu
99 tworeg_misc fcvtps
100 tworeg_misc fcvtpu
101
102 tworeg_misc fcvtms
103 tworeg_misc fcvtmu
104 tworeg_misc fcvtzs
105 tworeg_misc fcvtzu
106
107 tworeg_misc fcvtas
108 tworeg_misc fcvtau
109
110 tworeg_misc scvtf
111 tworeg_misc ucvtf
112 tworeg_misc frecpe
113 tworeg_misc frsqrte
114 tworeg_misc fsqrt
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115
116 /* Scalar two-register misc. */
117
118 .macro stworeg_zero, op
119 \op d0, d1, #0.0
120 \op s0, s1, #0.0
121 \op h0, h1, #0.0
122 \op h0, h0, #0.0
123 .endm
124
125 stworeg_zero fcmgt
126 stworeg_zero fcmge
127 stworeg_zero fcmeq
128 stworeg_zero fcmle
129 stworeg_zero fcmlt
130
131 .macro stworeg_misc, op
132 \op d0, d1
133 \op s0, s1
134 \op h0, h1
135 \op h0, h0
136 .endm
137
138 stworeg_misc fcvtns
139 stworeg_misc fcvtnu
140 stworeg_misc fcvtps
141 stworeg_misc fcvtpu
142
143 stworeg_misc fcvtms
144 stworeg_misc fcvtmu
145 stworeg_misc fcvtzs
146 stworeg_misc fcvtzu
147
148 stworeg_misc fcvtas
149 stworeg_misc fcvtau
150
151 stworeg_misc scvtf
152 stworeg_misc ucvtf
153
154 stworeg_misc frecpe
155 stworeg_misc frsqrte
156 stworeg_misc frecpx
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157
158 /* Vector indexed element. */
159
160 .macro indexed_elem, op
161 \op v1.2d, v2.2d, v3.d[1]
162 \op v1.2s, v2.2s, v3.s[2]
163 \op v1.4s, v2.4s, v3.s[1]
164 \op v0.4h, v0.4h, v0.h[0]
165 \op v1.4h, v2.4h, v3.h[0]
166 \op v0.8h, v0.8h, v0.h[0]
167 \op v1.8h, v2.8h, v3.h[0]
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168 \op v1.2d, v5.2d, v10.d[0]
169 \op v8.2s, v0.2s, v11.s[3]
170 \op v0.4h, v9.4h, v15.h[7]
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171 .endm
172
173 indexed_elem fmla
174 indexed_elem fmls
175
176 indexed_elem fmul
177 indexed_elem fmulx
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178
179 /* Scalar indexed element. */
180
181 .macro sindexed_elem, op
182 \op d1, d2, v3.d[1]
183 \op s1, s2, v3.s[1]
184 \op h1, h2, v3.h[1]
185 \op h0, h0, v0.h[0]
186 .endm
187
188 sindexed_elem fmla
189 sindexed_elem fmls
190
191 sindexed_elem fmul
192 sindexed_elem fmulx
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193
194 /* Adv.SIMD across lanes. */
195
196 .macro across_lanes, op
197 \op s1, v2.4s
198 \op h1, v2.4h
199 \op h1, v2.8h
200 \op h0, v0.4h
201 \op h0, v0.8h
202 .endm
203
204 across_lanes fmaxnmv
205 across_lanes fmaxv
206 across_lanes fminnmv
207 across_lanes fminv
208
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209 /* Adv.SIMD modified immediate. */
210
211 fmov v1.2d, #2.0
212 fmov v1.2s, #2.0
213 fmov v1.4s, #2.0
214 fmov v1.4h, #2.0
215 fmov v1.8h, #2.0
216 fmov v0.4h, #1.0
217 fmov v0.8h, #1.0
b195470d 218
b5b0f34c 219 /* Adv.SIMD scalar pairwise. */
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220
221 .macro scalar_pairwise, op
222 \op d1, v2.2d
223 \op s1, v2.2s
224 \op h1, v2.2h
225 \op h0, v0.2h
226 .endm
227
228 scalar_pairwise fmaxnmp
229 scalar_pairwise faddp
230 scalar_pairwise fmaxp
231 scalar_pairwise fminnmp
232 scalar_pairwise fminp
233
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234 /* Adv.SIMD shift by immediate. */
235
236 .macro shift_imm, op
237 \op v1.2d, v2.2d, #3
238 \op v1.2s, v2.2s, #3
239 \op v1.4s, v2.4s, #3
240 \op v1.4h, v2.4h, #3
241 \op v1.8h, v2.8h, #3
242 \op v0.4h, v0.4h, #1
243 \op v0.8h, v0.8h, #1
244 .endm
245
246 shift_imm scvtf
247 shift_imm fcvtzs
248 shift_imm ucvtf
249 shift_imm fcvtzu
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250
251 /* Adv.SIMD scalar shift by immediate. */
252
253 .macro sshift_imm, op
254 \op d1, d2, #3
255 \op s1, s2, #3
256 \op h1, h2, #3
257 \op h0, h0, #1
258 .endm
259
260 sshift_imm scvtf
261 sshift_imm fcvtzs
262 sshift_imm ucvtf
263 sshift_imm fcvtzu
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