Commit | Line | Data |
---|---|---|
a06ea964 NC |
1 | // diagnostic.s Test file for diagnostic quality. |
2 | ||
3 | .text | |
4 | fmul, s0, s1, s2 | |
5 | fmul , s0, s1, s2 | |
6 | fmul , s0, s1, s2 | |
7 | b.random label1 | |
8 | fmull s0 | |
9 | aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa | |
10 | sys 1,c1,c3,3, | |
11 | ext v0.8b, v1.8b, v2.8b, 8 | |
12 | ext v0.16b, v1.16b, v2.16b, 20 | |
13 | svc -1 | |
14 | svc 65536 | |
15 | ccmp w0, 32, 10, le | |
16 | ccmp x0, -1, 10, le | |
17 | tlbi alle3is, x0 | |
18 | tlbi vaale1is | |
19 | tlbi vaale1is x0 | |
20 | msr spsel, 3 | |
21 | fcvtzu x15, d31, #66 | |
22 | scvtf s0, w0, 33 | |
23 | scvtf s0, w0, 0 | |
24 | smlal v0.4s, v31.4h, v16.h[1] | |
25 | smlal v0.4s, v31.4h, v15.h[8] | |
26 | add sp, x0, x7, lsr #2 | |
27 | add x0, x0, x7, uxtx #5 | |
28 | add x0, xzr, x7, ror #5 | |
29 | add w0, wzr, w7, asr #32 | |
30 | st2 {v0.4s, v1.4s}, [sp], #24 | |
31 | ldr q0, [x0, w0, uxtw #5] | |
32 | st2 {v0.4s, v1.4s, v2.4s, v3.4s}, [sp], #64 | |
33 | adds x1, sp, 2134, lsl #4 | |
34 | movz w0, 2134, lsl #8 | |
35 | movz w0, 2134, lsl #32 | |
36 | movz x0, 2134, lsl #47 | |
37 | sbfiz w0, w7, 15, 18 | |
38 | sbfiz w0, w7, 15, 0 | |
39 | shll v1.4s, v2.4h, #15 | |
40 | shll v1.4s, v2.4h, #32 | |
41 | shl v1.2s, v2.2s, 32 | |
42 | sqshrn2 v2.16b, v3.8h, #17 | |
43 | movi v1.4h, 256 | |
d2865ed3 | 44 | movi v1.4h, -129 |
a06ea964 NC |
45 | movi v1.4h, 255, msl #8 |
46 | movi d0, 256 | |
47 | movi v1.4h, 255, lsl #7 | |
48 | movi v1.4h, 255, lsl #16 | |
49 | movi v2.2s, 255, msl #0 | |
50 | movi v2.2s, 255, msl #15 | |
51 | fmov v1.2s, 1.01 | |
52 | fmov v1.2d, 1.01 | |
53 | fmov s3, 1.01 | |
54 | fmov d3, 1.01 | |
55 | fcmp d0, #1.0 | |
56 | fcmp d0, x0 | |
57 | cmgt v0.4s, v2.4s, #1 | |
58 | fmov d3, 1.00, lsl #3 | |
59 | st2 {v0.4s, v1.4s}, [sp], sp | |
60 | st2 {v0.4s, v1.4s}, [sp], zr | |
61 | ldr q0, [x0, w0, lsr #4] | |
62 | adds x1, sp, 2134, uxtw #12 | |
63 | movz x0, 2134, lsl #64 | |
64 | adds sp, sp, 2134, lsl #12 | |
65 | ldxrb w2, [x0, #1] | |
66 | ldrb w0, x1, x2, sxtx | |
67 | prfm PLDL3KEEP, [x9, x15, sxtx #2] | |
68 | sysl x7, #1, C16, C30, #1 | |
69 | sysl x7, #1, C15, C77, #1 | |
a6a51754 | 70 | sysl x7, #1, x15, C1, #1 |
a06ea964 NC |
71 | add x0, xzr, x7, uxtx #5 |
72 | mov x0, ##5 | |
73 | bad expression | |
74 | mockup-op | |
75 | orr x0. x0, #0xff, lsl #1 | |
76 | movk x1, #:abs_g1_s:s12 | |
77 | movz x1, #:abs_g1_s:s12, lsl #16 | |
78 | prfm pldl3strm, [sp, w0, sxtw #3]! | |
79 | prfm 0x2f, LABEL1 | |
80 | dmb #16 | |
81 | tbz w0, #40, 0x17c | |
82 | st2 {v4.2d, v5.2d, v6.2d}, [x3] | |
83 | ld2 {v1.4h, v0.4h}, [x1] | |
84 | isb osh | |
85 | st2 {v4.2d, v5.2d, v6.2d}, \[x3\] | |
86 | ldnp w7, w15, [x3, #3] | |
87 | stnp x7, x15, [x3, #32]! | |
88 | ldnp w7, w15, [x3, #256] | |
89 | movi v1.2d, 4294967295, lsl #0 | |
90 | movi v1.8b, 97, lsl #8 | |
a3251895 | 91 | msr dummy, x1 |
62b0d0d5 | 92 | fmov s0, 0x42000000 |
4e50d5f8 YZ |
93 | ldp x0, x1, [x2, #4] |
94 | ldp x0, x1, [x2, #4]! | |
95 | ldp x0, x1, [x2], #4 | |
96 | stp w0, w1, [x2, #3] | |
97 | stp w0, w1, [x2, #2]! | |
98 | stp w0, w1, [x2], #1 | |
68a64283 YZ |
99 | cinc w0, w1, al |
100 | cinc w0, w1, nv | |
101 | cset w0, al | |
102 | cset w0, nv | |
f4c51f60 JW |
103 | |
104 | # test diagnostic info on optional operand | |
62e20ed4 | 105 | |
f4c51f60 JW |
106 | ret kk |
107 | clrex x0 | |
108 | clrex w0 | |
109 | clrex kk | |
110 | sys #0, c0, c0, #0, kk | |
111 | sys #0, c0, c0, #0, | |
ee804238 JW |
112 | |
113 | casp w0,w1,w2,w3,[x4] | |
54a28c4c JW |
114 | |
115 | # test warning of unpredictable load pairs | |
116 | ldp x0, x0, [sp] | |
117 | ldp d0, d0, [sp] | |
118 | ldp x0, x0, [sp], #16 | |
119 | ldnp x0, x0, [sp] | |
120 | ||
121 | # test warning of unpredictable writeback | |
122 | ldr x0, [x0, #8]! | |
123 | str x0, [x0, #8]! | |
124 | str x1, [x1], #8 | |
125 | stp x0, x1, [x0, #16]! | |
126 | ldp x0, x1, [x1], #16 | |
3e29ed9f | 127 | adr x2, :got:s1 |
27228ca2 | 128 | ldr x0, [x0, :got:s1] |
4bf8c6e8 JW |
129 | |
130 | # Test error of 32-bit base reg | |
131 | ldr x1, [wsp, #8]! | |
132 | ldp x6, x29, [w7, #8]! | |
133 | str x30, [w11, #8]! | |
134 | stp x8, x27, [wsp, #8]! | |
135 | ||
136 | # Test various valid load/store reg combination. | |
137 | # especially we shouldn't warn on xzr, although | |
138 | # xzr is with the same encoding 31 as sp. | |
139 | .macro ldst_pair_wb_2 op, reg1, reg2 | |
140 | .irp base x3, x6, x25, sp | |
141 | \op \reg1, \reg2, [\base], #16 | |
142 | \op \reg1, \reg2, [\base, #32]! | |
143 | \op \reg2, \reg1, [\base], #32 | |
144 | \op \reg2, \reg1, [\base, #16]! | |
145 | .endr | |
146 | .endm | |
147 | ||
148 | .macro ldst_pair_wb_1 op, reg1, width | |
149 | .irp reg2 0, 14, 21, 23, 29 | |
150 | ldst_pair_wb_2 \op, \reg1, \width\reg2 | |
151 | .endr | |
152 | .endm | |
153 | ||
154 | .macro ldst_pair_wb_64 op | |
155 | .irp reg1 x2, x15, x16, x27, x30, xzr | |
156 | ldst_pair_wb_1 \op, \reg1, x | |
157 | .endr | |
158 | .endm | |
159 | ||
160 | .macro ldst_pair_wb_32 op | |
161 | .irp reg1 w1, w12, w16, w19, w30, wzr | |
162 | ldst_pair_wb_1 \op, \reg1, w | |
163 | .endr | |
164 | .endm | |
165 | ||
166 | .macro ldst_single_wb_1 op, reg | |
167 | .irp base x1, x4, x13, x26, sp | |
168 | \op \reg, [\base], #16 | |
169 | .endr | |
170 | .endm | |
171 | ||
172 | .macro ldst_single_wb_32 op | |
173 | .irp reg w0, w3, w12, w21, w28, w30, wzr | |
174 | ldst_single_wb_1 \op, \reg | |
175 | .endr | |
176 | .endm | |
177 | ||
178 | .macro ldst_single_wb_64 op | |
179 | .irp reg x2, x5, x17, x23, x24, x30, xzr | |
180 | ldst_single_wb_1 \op, \reg | |
181 | .endr | |
182 | .endm | |
183 | ||
184 | ldst_pair_wb_32 stp | |
185 | ldst_pair_wb_64 stp | |
186 | ||
187 | ldst_pair_wb_32 ldp | |
188 | ldst_pair_wb_64 ldp | |
189 | ||
190 | ldst_pair_wb_64 ldpsw | |
191 | ||
192 | ldst_single_wb_32 str | |
193 | ldst_single_wb_64 str | |
194 | ||
195 | ldst_single_wb_32 strb | |
196 | ||
197 | ldst_single_wb_32 strh | |
198 | ||
199 | ldst_single_wb_32 ldr | |
200 | ldst_single_wb_64 ldr | |
201 | ||
202 | ldst_single_wb_32 ldrb | |
203 | ||
204 | ldst_single_wb_32 ldrh | |
205 | ||
206 | ldst_single_wb_32 ldrsb | |
207 | ldst_single_wb_64 ldrsb | |
208 | ||
209 | ldst_single_wb_32 ldrsh | |
210 | ldst_single_wb_64 ldrsh | |
211 | ||
212 | ldst_single_wb_64 ldrsw | |
dab26bf4 RS |
213 | |
214 | dup v0.2d, v1.2d[-1] | |
215 | dup v0.2d, v1.2d[0] | |
216 | dup v0.2d, v1.2d[1] | |
217 | dup v0.2d, v1.2d[2] | |
218 | dup v0.2d, v1.2d[64] | |
219 | ||
220 | dup v0.4s, v1.4s[-1] | |
221 | dup v0.4s, v1.4s[0] | |
222 | dup v0.4s, v1.4s[3] | |
223 | dup v0.4s, v1.4s[4] | |
224 | dup v0.4s, v1.4s[65] | |
225 | ||
226 | dup v0.8h, v1.8h[-1] | |
227 | dup v0.8h, v1.8h[0] | |
228 | dup v0.8h, v1.8h[7] | |
229 | dup v0.8h, v1.8h[8] | |
230 | dup v0.8h, v1.8h[66] | |
231 | ||
232 | dup v0.16b, v1.16b[-1] | |
233 | dup v0.16b, v1.16b[0] | |
234 | dup v0.16b, v1.16b[15] | |
235 | dup v0.16b, v1.16b[16] | |
236 | dup v0.16b, v1.16b[67] | |
237 | ||
238 | ld2 {v0.d, v1.d}[-1], [x0] | |
239 | ld2 {v0.d, v1.d}[0], [x0] | |
240 | ld2 {v0.d, v1.d}[1], [x0] | |
241 | ld2 {v0.d, v1.d}[2], [x0] | |
242 | ld2 {v0.d, v1.d}[64], [x0] | |
243 | ||
244 | ld2 {v0.s, v1.s}[-1], [x0] | |
245 | ld2 {v0.s, v1.s}[0], [x0] | |
246 | ld2 {v0.s, v1.s}[3], [x0] | |
247 | ld2 {v0.s, v1.s}[4], [x0] | |
248 | ld2 {v0.s, v1.s}[65], [x0] | |
249 | ||
250 | ld2 {v0.h, v1.h}[-1], [x0] | |
251 | ld2 {v0.h, v1.h}[0], [x0] | |
252 | ld2 {v0.h, v1.h}[7], [x0] | |
253 | ld2 {v0.h, v1.h}[8], [x0] | |
254 | ld2 {v0.h, v1.h}[66], [x0] | |
255 | ||
256 | ld2 {v0.b, v1.b}[-1], [x0] | |
257 | ld2 {v0.b, v1.b}[0], [x0] | |
258 | ld2 {v0.b, v1.b}[15], [x0] | |
259 | ld2 {v0.b, v1.b}[16], [x0] | |
260 | ld2 {v0.b, v1.b}[67], [x0] | |
6a9deabe | 261 | |
66881839 TC |
262 | |
263 | ||
264 | ||
265 | ||
e1b988bb RS |
266 | |
267 | st2 {v0.4s, v1.4s}, [sp], xzr | |
268 | str x1, [x2, sp] | |
73866052 RS |
269 | |
270 | ldr x0, [x1, #:lo12:foo] // OK | |
271 | ldnp x1, x2, [x3, #:lo12:foo] | |
272 | ld1 {v0.4s}, [x3, #:lo12:foo] | |
273 | stuminl x0, [x3, #:lo12:foo] | |
274 | prfum pldl1keep, [x3, #:lo12:foo] | |
275 | ||
276 | ldr x0, [x3], x4 | |
277 | ldnp x1, x2, [x3], x4 | |
278 | ld1 {v0.4s}, [x3], x4 // OK | |
279 | stuminl x0, [x3], x4 | |
280 | prfum pldl1keep, [x3], x4 | |
bc33f5f9 RS |
281 | |
282 | ldr x0, [x1, #1, mul vl] | |
283 | ldr x0, [x1, x2, mul vl] | |
284 | ldr x0, [x1, x2, mul #1] | |
285 | ldr x0, [x1, x2, mul #4] | |
286 | ||
287 | strb w7, [x30, x0, mul] | |
288 | strb w7, [x30, x0, mul #1] | |
289 | strb w7, [x30, w0, mul] | |
290 | strb w7, [x30, w0, mul #2] | |
291 | ||
292 | adds x1, sp, 1, mul #1 | |
293 | adds x1, sp, 2, mul #255 | |
294 | adds x1, sp, 3, mul #256 | |
295 | orr x0, x0, #0xff, mul #1 | |
296 | orr x0, x0, #0xfe, mul #255 | |
297 | orr x0, x0, #0xfc, mul #256 | |
8975f864 RR |
298 | |
299 | ip0 .req x0 | |
300 | ip1 .req x1 | |
301 | lr .req x2 | |
302 | fp .req x3 | |
ee943970 RR |
303 | |
304 | stlxrb w26, w26, [x0] | |
305 | stlxrh w26, w26, [x1] | |
306 | stlxr w26, w26, [x2] | |
307 | stlxrb w26, w27, [x26] | |
308 | stlxrh w26, w27, [x26] | |
309 | stlxr w26, w27, [x26] | |
310 | stlxr w26, x27, [x26] | |
311 | stlxr w26, x26, [x3] | |
312 | ldxp x26, x26, [x5] | |
313 | ldxp x26, x1, [x26] |