projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 8382113f MM |
1 | /* The instructions with non-zero register numbers are there to ensure we have |
| 2 | the correct argument positioning (i.e. check that the first argument is at | |
| 3 | the end of the word etc). | |
| 4 | The instructions with all-zero register numbers are to ensure the previous | |
| 5 | encoding didn't just "happen" to fit -- so that if we change the registers | |
| 6 | that changes the correct part of the word. | |
| 7 | Each of the numbered patterns begin and end with a 1, so we can replace | |
| 8 | them with all-zeros and see the entire range has changed. */ | |
| 9 | ||
| 10 | // SVE | |
| 11 | fmmla z17.d, z21.d, z27.d | |
| 12 | fmmla z0.d, z0.d, z0.d | |
| 13 | ||
| 14 | ld1rob { z17.b }, p5/z, [sp, x27] | |
| 15 | ld1rob { z0.b }, p0/z, [sp, x0] | |
| 5437a02a JB |
16 | ld1roh { z17.h }, p5/z, [sp, x27, lsl #1] |
| 17 | ld1roh { z0.h }, p0/z, [sp, x0, lsl #1] | |
| 18 | ld1row { z17.s }, p5/z, [sp, x27, lsl #2] | |
| 19 | ld1row { z0.s }, p0/z, [sp, x0, lsl #2] | |
| 20 | ld1rod { z17.d }, p5/z, [sp, x27, lsl #3] | |
| 21 | ld1rod { z0.d }, p0/z, [sp, x0, lsl #3] | |
| 8382113f MM |
22 | |
| 23 | ld1rob { z17.b }, p5/z, [x0, x27] | |
| 24 | ld1rob { z0.b }, p0/z, [x0, x0] | |
| 5437a02a JB |
25 | ld1roh { z17.h }, p5/z, [x0, x27, lsl #1] |
| 26 | ld1roh { z0.h }, p0/z, [x0, x0, lsl #1] | |
| 27 | ld1row { z17.s }, p5/z, [x0, x27, lsl #2] | |
| 28 | ld1row { z0.s }, p0/z, [x0, x0, lsl #2] | |
| 29 | ld1rod { z17.d }, p5/z, [x0, x27, lsl #3] | |
| 30 | ld1rod { z0.d }, p0/z, [x0, x0, lsl #3] | |
| 8382113f MM |
31 | |
| 32 | ld1rob { z17.b }, p5/z, [sp, #0] | |
| 33 | ld1rob { z0.b }, p0/z, [sp, #224] | |
| 34 | ld1rob { z0.b }, p0/z, [sp, #-256] | |
| 35 | ld1roh { z17.h }, p5/z, [sp, #0] | |
| 36 | ld1roh { z0.h }, p0/z, [sp, #224] | |
| 37 | ld1roh { z0.h }, p0/z, [sp, #-256] | |
| 38 | ld1row { z17.s }, p5/z, [sp, #0] | |
| 39 | ld1row { z0.s }, p0/z, [sp, #224] | |
| 40 | ld1row { z0.s }, p0/z, [sp, #-256] | |
| 41 | ld1rod { z17.d }, p5/z, [sp, #0] | |
| 42 | ld1rod { z0.d }, p0/z, [sp, #224] | |
| 43 | ld1rod { z0.d }, p0/z, [sp, #-256] | |
| 44 | ||
| 45 | ld1rob { z17.b }, p5/z, [x0, #0] | |
| 46 | ld1rob { z0.b }, p0/z, [x0, #224] | |
| 47 | ld1rob { z0.b }, p0/z, [x0, #-256] | |
| 48 | ld1roh { z17.h }, p5/z, [x0, #0] | |
| 49 | ld1roh { z0.h }, p0/z, [x0, #224] | |
| 50 | ld1roh { z0.h }, p0/z, [x0, #-256] | |
| 51 | ld1row { z17.s }, p5/z, [x0, #0] | |
| 52 | ld1row { z0.s }, p0/z, [x0, #224] | |
| 53 | ld1row { z0.s }, p0/z, [x0, #-256] | |
| 54 | ld1rod { z17.d }, p5/z, [x0, #0] | |
| 55 | ld1rod { z0.d }, p0/z, [x0, #224] | |
| 56 | ld1rod { z0.d }, p0/z, [x0, #-256] | |
| 57 | ||
| 58 | zip1 z17.q, z21.q, z5.q | |
| 59 | zip1 z0.q, z0.q, z0.q | |
| 60 | zip2 z17.q, z21.q, z5.q | |
| 61 | zip2 z0.q, z0.q, z0.q | |
| 62 | ||
| 8c45011a JB |
63 | uzp1 z17.q, z21.q, z5.q |
| 64 | uzp1 z0.q, z0.q, z0.q | |
| 65 | uzp2 z17.q, z21.q, z5.q | |
| 66 | uzp2 z0.q, z0.q, z0.q | |
| 8382113f MM |
67 | |
| 68 | trn1 z17.q, z21.q, z5.q | |
| 69 | trn1 z0.q, z0.q, z0.q | |
| 70 | trn2 z17.q, z21.q, z5.q | |
| 71 | trn2 z0.q, z0.q, z0.q |