Commit | Line | Data |
---|---|---|
50cc854c MW |
1 | /* Incorrect use of the RAS extension instructions. */ |
2 | .text | |
3 | ||
4 | .macro rw_sys_reg sys_reg xreg r w | |
5 | .ifc \w, 1 | |
6 | msr \sys_reg, \xreg | |
7 | .endif | |
8 | .ifc \r, 1 | |
9 | mrs \xreg, \sys_reg | |
10 | .endif | |
11 | .endm | |
12 | ||
13 | /* ARMv8-A. */ | |
14 | .arch armv8-a | |
15 | esb | |
16 | hint #0x10 | |
17 | ||
18 | rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 | |
19 | rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 | |
20 | ||
21 | rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 | |
22 | rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 | |
23 | rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 | |
24 | rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 | |
25 | ||
26 | rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 | |
27 | rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 | |
28 | ||
29 | rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 | |
30 | rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 | |
31 | rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 | |
32 | ||
33 | /* ARMv8.1-A. */ | |
34 | ||
35 | .arch armv8.1-a | |
36 | esb | |
37 | hint #0x10 | |
38 | ||
39 | rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 | |
40 | rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 | |
41 | ||
42 | rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 | |
43 | rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 | |
44 | rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 | |
45 | rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 | |
46 | ||
47 | rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 | |
48 | rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 | |
49 | ||
50 | rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 | |
51 | rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 | |
52 | rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 |