Commit | Line | Data |
---|---|---|
37ab9779 CZ |
1 | lr r5, [status] |
2 | lr r5, [semaphore] | |
3 | lr r5, [lp_start] | |
4 | lr r5, [lp_end] | |
5 | lr r5, [identity] | |
6 | lr r5, [debug] | |
7 | lr r5, [pc] | |
8 | lr r5, [adcr] | |
9 | lr r5, [apcr] | |
10 | lr r5, [acr] | |
11 | lr r5, [status32] | |
12 | lr r5, [status32_l1] | |
13 | lr r5, [status32_l2] | |
14 | lr r5, [bpu_flush] | |
15 | lr r5, [ivic] | |
16 | lr r5, [ic_ivic] | |
17 | lr r5, [che_mode] | |
18 | lr r5, [ic_ctrl] | |
19 | lr r5, [mulhi] | |
20 | lr r5, [lockline] | |
21 | lr r5, [ic_lil] | |
22 | lr r5, [dmc_code_ram] | |
23 | lr r5, [tag_addr_mask] | |
24 | lr r5, [tag_data_mask] | |
25 | lr r5, [line_length_mask] | |
26 | lr r5, [aux_ldst_ram] | |
27 | lr r5, [aux_dccm] | |
28 | lr r5, [unlockline] | |
29 | lr r5, [ic_ivil] | |
30 | lr r5, [ic_ram_address] | |
31 | lr r5, [ic_tag] | |
32 | lr r5, [ic_wp] | |
33 | lr r5, [ic_data] | |
34 | lr r5, [sram_seq] | |
35 | lr r5, [count0] | |
36 | lr r5, [control0] | |
37 | lr r5, [limit0] | |
38 | lr r5, [pcport] | |
39 | lr r5, [int_vector_base] | |
40 | lr r5, [aux_vbfdw_mode] | |
41 | lr r5, [jli_base] | |
42 | lr r5, [aux_vbfdw_bm0] | |
43 | lr r5, [aux_vbfdw_bm1] | |
44 | lr r5, [aux_vbfdw_accu] | |
45 | lr r5, [aux_vbfdw_ofst] | |
46 | lr r5, [aux_vbfdw_intstat] | |
47 | lr r5, [aux_xmac0_24] | |
48 | lr r5, [aux_xmac1_24] | |
49 | lr r5, [aux_xmac2_24] | |
50 | lr r5, [aux_fbf_store_16] | |
51 | lr r5, [ax0] | |
52 | lr r5, [ax1] | |
53 | lr r5, [aux_crc_poly] | |
54 | lr r5, [aux_crc_mode] | |
55 | lr r5, [mx0] | |
56 | lr r5, [mx1] | |
57 | lr r5, [my0] | |
58 | lr r5, [my1] | |
59 | lr r5, [xyconfig] | |
60 | lr r5, [scratch_a] | |
61 | lr r5, [burstsys] | |
62 | lr r5, [tsch] | |
63 | lr r5, [burstxym] | |
64 | lr r5, [burstsz] | |
65 | lr r5, [burstval] | |
66 | lr r5, [xtp_newval] | |
67 | lr r5, [aux_macmode] | |
68 | lr r5, [lsp_newval] | |
69 | lr r5, [aux_irq_lv12] | |
70 | lr r5, [aux_xmac0] | |
71 | lr r5, [aux_xmac1] | |
72 | lr r5, [aux_xmac2] | |
73 | lr r5, [dc_ivdc] | |
74 | lr r5, [dc_ctrl] | |
75 | lr r5, [dc_ldl] | |
76 | lr r5, [dc_ivdl] | |
77 | lr r5, [dc_flsh] | |
78 | lr r5, [dc_fldl] | |
79 | lr r5, [hexdata] | |
80 | lr r5, [hexctrl] | |
81 | lr r5, [led] | |
82 | lr r5, [dilstat] | |
83 | lr r5, [swstat] | |
84 | lr r5, [dc_ram_addr] | |
85 | lr r5, [dc_tag] | |
86 | lr r5, [dc_wp] | |
87 | lr r5, [dc_data] | |
88 | lr r5, [dccm_base_build] | |
89 | lr r5, [crc_build] | |
90 | lr r5, [bta_link_build] | |
91 | lr r5, [vbfdw_build] | |
92 | lr r5, [ea_build] | |
93 | lr r5, [dataspace] | |
94 | lr r5, [memsubsys] | |
95 | lr r5, [vecbase_ac_build] | |
96 | lr r5, [p_base_addr] | |
97 | lr r5, [data_uncached_build] | |
98 | lr r5, [fp_build] | |
99 | lr r5, [dpfp_build] | |
100 | lr r5, [mpu_build] | |
101 | lr r5, [rf_build] | |
102 | lr r5, [mmu_build] | |
103 | lr r5, [aa2_build] | |
104 | lr r5, [vecbase_build] | |
105 | lr r5, [d_cache_build] | |
106 | lr r5, [madi_build] | |
107 | lr r5, [dccm_build] | |
108 | lr r5, [timer_build] | |
109 | lr r5, [ap_build] | |
110 | lr r5, [i_cache_build] | |
111 | lr r5, [iccm_build] | |
112 | lr r5, [dspram_build] | |
113 | lr r5, [mac_build] | |
114 | lr r5, [multiply_build] | |
115 | lr r5, [swap_build] | |
116 | lr r5, [norm_build] | |
117 | lr r5, [minmax_build] | |
118 | lr r5, [barrel_build] | |
119 | lr r5, [ax0] | |
120 | lr r5, [ax1] | |
121 | lr r5, [ax2] | |
122 | lr r5, [ax3] | |
123 | lr r5, [ay0] | |
124 | lr r5, [ay1] | |
125 | lr r5, [ay2] | |
126 | lr r5, [ay3] | |
127 | lr r5, [mx00] | |
128 | lr r5, [mx01] | |
129 | lr r5, [mx10] | |
130 | lr r5, [mx11] | |
131 | lr r5, [mx20] | |
132 | lr r5, [mx21] | |
133 | lr r5, [mx30] | |
134 | lr r5, [mx31] | |
135 | lr r5, [my00] | |
136 | lr r5, [my01] | |
137 | lr r5, [my10] | |
138 | lr r5, [my11] | |
139 | lr r5, [my20] | |
140 | lr r5, [my21] | |
141 | lr r5, [my30] | |
142 | lr r5, [my31] | |
143 | lr r5, [xyconfig] | |
144 | lr r5, [burstsys] | |
145 | lr r5, [burstxym] | |
146 | lr r5, [burstsz] | |
147 | lr r5, [burstval] | |
148 | lr r5, [xylsbasex] | |
149 | lr r5, [xylsbasey] | |
150 | lr r5, [aux_xmaclw_h] | |
151 | lr r5, [aux_xmaclw_l] | |
152 | lr r5, [se_ctrl] | |
153 | lr r5, [se_stat] | |
154 | lr r5, [se_err] | |
155 | lr r5, [se_eadr] | |
156 | lr r5, [se_spc] | |
157 | lr r5, [sdm_base] | |
158 | lr r5, [scm_base] | |
159 | lr r5, [se_dbg_ctrl] | |
160 | lr r5, [se_dbg_data0] | |
161 | lr r5, [se_dbg_data1] | |
162 | lr r5, [se_dbg_data2] | |
163 | lr r5, [se_dbg_data3] | |
164 | lr r5, [se_watch] | |
165 | lr r5, [bpu_build] | |
166 | lr r5, [arc600_build_config] | |
167 | lr r5, [isa_config] | |
168 | lr r5, [hwp_build] | |
169 | lr r5, [pct_build] | |
170 | lr r5, [cc_build] | |
171 | lr r5, [pm_bcr] | |
172 | lr r5, [scq_switch_build] | |
173 | lr r5, [vraptor_build] | |
174 | lr r5, [dma_config] | |
175 | lr r5, [simd_config] | |
176 | lr r5, [vlc_build] | |
177 | lr r5, [simd_dma_build] | |
178 | lr r5, [ifetch_queue_build] | |
179 | lr r5, [smart_build] | |
180 | lr r5, [count1] | |
181 | lr r5, [control1] | |
182 | lr r5, [limit1] | |
183 | lr r5, [timer_xx] | |
184 | lr r5, [arcangel_periph_xx] | |
185 | lr r5, [periph_xx] | |
186 | lr r5, [aux_irq_lev] | |
187 | lr r5, [aux_irq_hint] | |
188 | lr r5, [aux_inter_core_interrupt] | |
189 | lr r5, [aes_aux_0] | |
190 | lr r5, [aes_aux_1] | |
191 | lr r5, [aes_aux_2] | |
192 | lr r5, [aes_crypt_mode] | |
193 | lr r5, [aes_auxs] | |
194 | lr r5, [aes_auxi] | |
195 | lr r5, [aes_aux_3] | |
196 | lr r5, [aes_aux_4] | |
197 | lr r5, [arith_ctl_aux] | |
198 | lr r5, [des_aux] | |
199 | lr r5, [ap_amv0] | |
200 | lr r5, [ap_amm0] | |
201 | lr r5, [ap_ac0] | |
202 | lr r5, [ap_amv1] | |
203 | lr r5, [ap_amm1] | |
204 | lr r5, [ap_ac1] | |
205 | lr r5, [ap_amv2] | |
206 | lr r5, [ap_amm2] | |
207 | lr r5, [ap_ac2] | |
208 | lr r5, [ap_amv3] | |
209 | lr r5, [ap_amm3] | |
210 | lr r5, [ap_ac3] | |
211 | lr r5, [ap_amv4] | |
212 | lr r5, [ap_amm4] | |
213 | lr r5, [ap_ac4] | |
214 | lr r5, [ap_amv5] | |
215 | lr r5, [ap_amm5] | |
216 | lr r5, [ap_ac5] | |
217 | lr r5, [ap_amv6] | |
218 | lr r5, [ap_amm6] | |
219 | lr r5, [ap_ac6] | |
220 | lr r5, [ap_amv7] | |
221 | lr r5, [ap_amm7] | |
222 | lr r5, [ap_ac7] | |
223 | lr r5, [pct_control] | |
224 | lr r5, [pct_bank] | |
225 | lr r5, [fp_status] | |
226 | lr r5, [aux_dpfp1l] | |
227 | lr r5, [d1l] | |
228 | lr r5, [aux_dpfp1h] | |
229 | lr r5, [d1h] | |
230 | lr r5, [d1l] | |
231 | lr r5, [aux_dpfp2l] | |
232 | lr r5, [d2l] | |
233 | lr r5, [d1h] | |
234 | lr r5, [aux_dpfp2h] | |
235 | lr r5, [d2h] | |
236 | lr r5, [d2l] | |
237 | lr r5, [dpfp_status] | |
238 | lr r5, [d2h] | |
239 | lr r5, [rtt] | |
240 | lr r5, [eret] | |
241 | lr r5, [erbta] | |
242 | lr r5, [erstatus] | |
243 | lr r5, [ecr] | |
244 | lr r5, [efa] | |
245 | lr r5, [tlbpd0] | |
246 | lr r5, [tlbpd1] | |
247 | lr r5, [tlbindex] | |
248 | lr r5, [tlbcommand] | |
249 | lr r5, [pid] | |
250 | lr r5, [mpuen] | |
251 | lr r5, [icause1] | |
252 | lr r5, [icause2] | |
253 | lr r5, [aux_ienable] | |
254 | lr r5, [aux_itrigger] | |
255 | lr r5, [xpu] | |
256 | lr r5, [bta] | |
257 | lr r5, [bta_l1] | |
258 | lr r5, [bta_l2] | |
259 | lr r5, [aux_irq_pulse_cancel] | |
260 | lr r5, [aux_irq_pending] | |
261 | lr r5, [scratch_data0] | |
262 | lr r5, [mpuic] | |
263 | lr r5, [mpufa] | |
264 | lr r5, [mpurdb0] | |
265 | lr r5, [mpurdp0] | |
266 | lr r5, [mpurdb1] | |
267 | lr r5, [mpurdp1] | |
268 | lr r5, [mpurdb2] | |
269 | lr r5, [mpurdp2] | |
270 | lr r5, [mpurdb3] | |
271 | lr r5, [mpurdp3] | |
272 | lr r5, [mpurdb4] | |
273 | lr r5, [mpurdp4] | |
274 | lr r5, [mpurdb5] | |
275 | lr r5, [mpurdp5] | |
276 | lr r5, [mpurdb6] | |
277 | lr r5, [mpurdp6] | |
278 | lr r5, [mpurdb7] | |
279 | lr r5, [mpurdp7] | |
280 | lr r5, [mpurdb8] | |
281 | lr r5, [mpurdp8] | |
282 | lr r5, [mpurdb9] | |
283 | lr r5, [mpurdp9] | |
284 | lr r5, [mpurdb10] | |
285 | lr r5, [mpurdp10] | |
286 | lr r5, [mpurdb11] | |
287 | lr r5, [mpurdp11] | |
288 | lr r5, [mpurdb12] | |
289 | lr r5, [mpurdp12] | |
290 | lr r5, [mpurdb13] | |
291 | lr r5, [mpurdp13] | |
292 | lr r5, [mpurdb14] | |
293 | lr r5, [mpurdp14] | |
294 | lr r5, [mpurdb15] | |
295 | lr r5, [mpurdp15] | |
296 | lr r5, [eia_flags] | |
297 | lr r5, [pm_status] | |
298 | lr r5, [wake] | |
299 | lr r5, [dvfs_performance] | |
300 | lr r5, [pwr_ctrl] | |
301 | lr r5, [aux_vlc_buf_idx] | |
302 | lr r5, [aux_vlc_read_buf] | |
303 | lr r5, [aux_vlc_valid_bits] | |
304 | lr r5, [aux_vlc_buf_in] | |
305 | lr r5, [aux_vlc_buf_free] | |
306 | lr r5, [aux_vlc_ibuf_status] | |
307 | lr r5, [aux_vlc_setup] | |
308 | lr r5, [aux_vlc_bits] | |
309 | lr r5, [aux_vlc_table] | |
310 | lr r5, [aux_vlc_get_symbol] | |
311 | lr r5, [aux_vlc_read_symbol] | |
312 | lr r5, [aux_ucavlc_setup] | |
313 | lr r5, [aux_ucavlc_state] | |
314 | lr r5, [aux_cavlc_zero_left] | |
315 | lr r5, [aux_uvlc_i_state] | |
316 | lr r5, [aux_vlc_dma_ptr] | |
317 | lr r5, [aux_vlc_dma_end] | |
318 | lr r5, [aux_vlc_dma_esc] | |
319 | lr r5, [aux_vlc_dma_ctrl] | |
320 | lr r5, [aux_vlc_get_0bit] | |
321 | lr r5, [aux_vlc_get_1bit] | |
322 | lr r5, [aux_vlc_get_2bit] | |
323 | lr r5, [aux_vlc_get_3bit] | |
324 | lr r5, [aux_vlc_get_4bit] | |
325 | lr r5, [aux_vlc_get_5bit] | |
326 | lr r5, [aux_vlc_get_6bit] | |
327 | lr r5, [aux_vlc_get_7bit] | |
328 | lr r5, [aux_vlc_get_8bit] | |
329 | lr r5, [aux_vlc_get_9bit] | |
330 | lr r5, [aux_vlc_get_10bit] | |
331 | lr r5, [aux_vlc_get_11bit] | |
332 | lr r5, [aux_vlc_get_12bit] | |
333 | lr r5, [aux_vlc_get_13bit] | |
334 | lr r5, [aux_vlc_get_14bit] | |
335 | lr r5, [aux_vlc_get_15bit] | |
336 | lr r5, [aux_vlc_get_16bit] | |
337 | lr r5, [aux_vlc_get_17bit] | |
338 | lr r5, [aux_vlc_get_18bit] | |
339 | lr r5, [aux_vlc_get_19bit] | |
340 | lr r5, [aux_vlc_get_20bit] | |
341 | lr r5, [aux_vlc_get_21bit] | |
342 | lr r5, [aux_vlc_get_22bit] | |
343 | lr r5, [aux_vlc_get_23bit] | |
344 | lr r5, [aux_vlc_get_24bit] | |
345 | lr r5, [aux_vlc_get_25bit] | |
346 | lr r5, [aux_vlc_get_26bit] | |
347 | lr r5, [aux_vlc_get_27bit] | |
348 | lr r5, [aux_vlc_get_28bit] | |
349 | lr r5, [aux_vlc_get_29bit] | |
350 | lr r5, [aux_vlc_get_30bit] | |
351 | lr r5, [aux_vlc_get_31bit] | |
352 | lr r5, [aux_cabac_ctrl] | |
353 | lr r5, [aux_cabac_ctx_state] | |
354 | lr r5, [aux_cabac_cod_param] | |
355 | lr r5, [aux_cabac_misc0] | |
356 | lr r5, [aux_cabac_misc1] | |
357 | lr r5, [aux_cabac_misc2] | |
358 | lr r5, [arc600_build_config] | |
359 | lr r5, [smart_control] | |
360 | lr r5, [smart_data_0] | |
361 | lr r5, [smart_data_1] | |
362 | lr r5, [smart_data_2] | |
363 | lr r5, [smart_data_3] |