Commit | Line | Data |
---|---|---|
c19d1205 ZW |
1 | # name: ARM architecture 4t instructions |
2 | # as: -march=armv4t | |
3 | # objdump: -dr --prefix-addresses --show-raw-insn | |
845b51d6 | 4 | # EABI targets have their own variant. |
b47b60aa | 5 | # notarget: *-*-*eabi* *-*-symbianelf *-*-nacl* |
c19d1205 ZW |
6 | |
7 | .*: +file format .*arm.* | |
8 | ||
9 | Disassembly of section .text: | |
10 | 0+00 <[^>]+> e12fff10 ? bx r0 | |
11 | 0+04 <[^>]+> 012fff11 ? bxeq r1 | |
12 | 0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> | |
945ee430 | 13 | 0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] |
c19d1205 ZW |
14 | 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] |
15 | 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! | |
5f69fa6d RE |
16 | 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] |
17 | 0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 | |
18 | 0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 | |
fe56b6ce NC |
19 | 0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].* |
20 | 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* | |
21 | 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* | |
c19d1205 | 22 | 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> |
945ee430 | 23 | 0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] |
fe56b6ce | 24 | 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 |
c19d1205 ZW |
25 | 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 |
26 | 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 | |
27 | 0+44 <[^>]+> e124f005 ? msr CPSR_s, r5 | |
28 | 0+48 <[^>]+> e128f006 ? msr CPSR_f, r6 | |
29 | 0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7 | |
fe56b6ce | 30 | 0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 |
c19d1205 ZW |
31 | 0+54 <[^>]+> e161f008 ? msr SPSR_c, r8 |
32 | 0+58 <[^>]+> e162f009 ? msr SPSR_x, r9 | |
33 | 0+5c <[^>]+> e164f00a ? msr SPSR_s, sl | |
34 | 0+60 <[^>]+> e168f00b ? msr SPSR_f, fp | |
35 | 0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip | |
fe56b6ce NC |
36 | 0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) |
37 | 0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) | |
c19d1205 | 38 |