Commit | Line | Data |
---|---|---|
16a1fa25 TP |
1 | #name: ARMv8-M Mainline Security Extensions MSR/MRS instructions |
2 | #source: archv8m-cmse-msr.s | |
3 | #as: -march=armv8-m.main | |
659f032c | 4 | #objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb |
16a1fa25 TP |
5 | |
6 | .*: +file format .*arm.* | |
7 | ||
8 | Disassembly of section .text: | |
16a1fa25 | 9 | 0+.* <[^>]*> f3ef 8008 mrs r0, MSP |
16a1fa25 | 10 | 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS |
16a1fa25 | 11 | 0+.* <[^>]*> f3ef 8008 mrs r0, MSP |
16a1fa25 | 12 | 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS |
1a336194 TP |
13 | 0+.* <[^>]*> f3ef 8109 mrs r1, PSP |
14 | 0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS | |
15 | 0+.* <[^>]*> f3ef 8109 mrs r1, PSP | |
16 | 0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS | |
17 | 0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM | |
18 | 0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS | |
19 | 0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM | |
20 | 0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS | |
21 | 0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM | |
22 | 0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS | |
23 | 0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM | |
24 | 0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS | |
25 | 0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK | |
26 | 0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS | |
27 | 0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK | |
28 | 0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS | |
29 | 0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI | |
30 | 0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS | |
31 | 0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI | |
32 | 0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS | |
33 | 0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK | |
34 | 0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS | |
35 | 0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK | |
36 | 0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS | |
37 | 0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL | |
38 | 0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS | |
39 | 0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL | |
40 | 0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS | |
41 | 0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS | |
42 | 0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS | |
43 | 0+.* <[^>]*> f380 8808 msr MSP, r0 | |
44 | 0+.* <[^>]*> f380 8888 msr MSP_NS, r0 | |
45 | 0+.* <[^>]*> f380 8808 msr MSP, r0 | |
46 | 0+.* <[^>]*> f380 8888 msr MSP_NS, r0 | |
47 | 0+.* <[^>]*> f381 8809 msr PSP, r1 | |
48 | 0+.* <[^>]*> f381 8889 msr PSP_NS, r1 | |
49 | 0+.* <[^>]*> f381 8809 msr PSP, r1 | |
50 | 0+.* <[^>]*> f381 8889 msr PSP_NS, r1 | |
51 | 0+.* <[^>]*> f382 880a msr MSPLIM, r2 | |
52 | 0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 | |
53 | 0+.* <[^>]*> f382 880a msr MSPLIM, r2 | |
54 | 0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 | |
55 | 0+.* <[^>]*> f383 880b msr PSPLIM, r3 | |
56 | 0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 | |
57 | 0+.* <[^>]*> f383 880b msr PSPLIM, r3 | |
58 | 0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 | |
59 | 0+.* <[^>]*> f384 8810 msr PRIMASK, r4 | |
60 | 0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 | |
61 | 0+.* <[^>]*> f384 8810 msr PRIMASK, r4 | |
62 | 0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 | |
63 | 0+.* <[^>]*> f385 8811 msr BASEPRI, r5 | |
64 | 0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 | |
65 | 0+.* <[^>]*> f385 8811 msr BASEPRI, r5 | |
66 | 0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 | |
67 | 0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 | |
68 | 0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 | |
69 | 0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 | |
70 | 0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 | |
71 | 0+.* <[^>]*> f387 8814 msr CONTROL, r7 | |
72 | 0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 | |
73 | 0+.* <[^>]*> f387 8814 msr CONTROL, r7 | |
74 | 0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 | |
75 | 0+.* <[^>]*> f388 8898 msr SP_NS, r8 | |
76 | 0+.* <[^>]*> f388 8898 msr SP_NS, r8 |