Commit | Line | Data |
---|---|---|
105bde57 MW |
1 | /* ARMv8.2 features. */ |
2 | ||
3 | /* RAS instructions. */ | |
4 | A1: | |
5 | .arm | |
6 | esb | |
7 | T1: .thumb | |
8 | esb | |
9 | ||
10 | /* RAS system registers. */ | |
11 | .macro test_sysreg Opc1 CRn CRm Opc2 rw | |
12 | mrc p15, \Opc1,\() r0, \CRn\(), \CRm\(), \Opc2\() | |
13 | .if \rw | |
14 | mcr p15, \Opc1\(), r1, \CRn\(), \CRm\(), \Opc2\() | |
15 | .endif | |
16 | .endm | |
17 | ||
18 | A2: | |
19 | .arm | |
20 | test_sysreg 0 c0 c1 0 0 | |
21 | test_sysreg 0 c0 c2 6 0 | |
22 | test_sysreg 0 c5 c3 0 0 | |
23 | test_sysreg 0 c5 c3 1 1 | |
24 | ||
25 | test_sysreg 0 c5 c4 0 0 | |
26 | test_sysreg 0 c5 c4 1 1 | |
27 | test_sysreg 0 c5 c4 2 1 | |
28 | test_sysreg 0 c5 c4 3 1 | |
29 | test_sysreg 0 c5 c4 4 0 | |
30 | test_sysreg 0 c5 c4 5 1 | |
31 | test_sysreg 0 c5 c4 7 1 | |
32 | ||
33 | test_sysreg 0 c5 c5 0 1 | |
34 | test_sysreg 0 c5 c5 1 1 | |
35 | test_sysreg 0 c5 c5 4 1 | |
36 | test_sysreg 0 c5 c5 5 1 | |
37 | ||
38 | test_sysreg 0 c12 c1 1 1 | |
39 | test_sysreg 4 c1 c1 4 1 | |
40 | test_sysreg 4 c5 c2 3 1 | |
41 | test_sysreg 4 c1 c1 1 1 | |
42 | test_sysreg 4 c12 c1 1 1 | |
43 | ||
44 | test_sysreg 6 c1 c1 0 1 |