projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 5aae9ae9 MM |
1 | [^ :]+: Assembler messages: |
| 2 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#0' | |
| 3 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#2048' | |
| 4 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#1920' | |
| 5 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#64' | |
| 6 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#63' | |
| 7 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p7,q0,#0' | |
| 8 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q7,#0' | |
| 9 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#0' | |
| 10 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#2048' | |
| 11 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#1920' | |
| 12 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#64' | |
| 13 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#63' | |
| 14 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p7,q0,#0' | |
| 15 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q7,#0' | |
| 16 | [^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode | |
| 17 | [^ :]+:[0-9]+: Error: bad instruction `vcx1t p0,q0,#0' | |
| 18 | [^ :]+:[0-9]+: Error: bad instruction `vcx1at p0,q0,#0' | |
| 19 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#0' | |
| 20 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#64' | |
| 21 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#60' | |
| 22 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#2' | |
| 23 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#1' | |
| 24 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p7,q0,q0,#0' | |
| 25 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q7,q0,#0' | |
| 26 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q7,#0' | |
| 27 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#0' | |
| 28 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#64' | |
| 29 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#60' | |
| 30 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#2' | |
| 31 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#1' | |
| 32 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p7,q0,q0,#0' | |
| 33 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q7,q0,#0' | |
| 34 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q7,#0' | |
| 35 | [^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode | |
| 36 | [^ :]+:[0-9]+: Error: bad instruction `vcx2t p0,q0,q0,#0' | |
| 37 | [^ :]+:[0-9]+: Error: bad instruction `vcx2at p0,q0,q0,#0' | |
| 38 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#0' | |
| 39 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#8' | |
| 40 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#6' | |
| 41 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#1' | |
| 42 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p7,q0,q0,q0,#0' | |
| 43 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q7,q0,q0,#0' | |
| 44 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q7,q0,#0' | |
| 45 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q7,#0' | |
| 46 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#0' | |
| 47 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#8' | |
| 48 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#6' | |
| 49 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#1' | |
| 50 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p7,q0,q0,q0,#0' | |
| 51 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q7,q0,q0,#0' | |
| 52 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q7,q0,#0' | |
| 53 | [^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q7,#0' | |
| 54 | [^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode | |
| 55 | [^ :]+:[0-9]+: Error: bad instruction `vcx3t p0,q0,q0,q0,#0' | |
| 56 | [^ :]+:[0-9]+: Error: bad instruction `vcx3at p0,q0,q0,q0,#0' | |
| 57 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#0' | |
| 58 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#1920' | |
| 59 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#64' | |
| 60 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#63' | |
| 61 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p7,s0,#0' | |
| 62 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s1,#0' | |
| 63 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s30,#0' | |
| 64 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#0' | |
| 65 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#1920' | |
| 66 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#64' | |
| 67 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#63' | |
| 68 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p7,d0,#0' | |
| 69 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d15,#0' | |
| 70 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#0' | |
| 71 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#1920' | |
| 72 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#64' | |
| 73 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#63' | |
| 74 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p7,s0,#0' | |
| 75 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s1,#0' | |
| 76 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s30,#0' | |
| 77 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#0' | |
| 78 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#1920' | |
| 79 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#64' | |
| 80 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#63' | |
| 81 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p7,d0,#0' | |
| 82 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d15,#0' | |
| 83 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#0' | |
| 84 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#60' | |
| 85 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#2' | |
| 86 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#1' | |
| 87 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p7,s0,s0,#0' | |
| 88 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s1,s0,#0' | |
| 89 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s30,s0,#0' | |
| 90 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s1,#0' | |
| 91 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s30,#0' | |
| 92 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#0' | |
| 93 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#60' | |
| 94 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#2' | |
| 95 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#1' | |
| 96 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p7,d0,d0,#0' | |
| 97 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d15,d0,#0' | |
| 98 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d15,#0' | |
| 99 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#0' | |
| 100 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#60' | |
| 101 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#2' | |
| 102 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#1' | |
| 103 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p7,s0,s0,#0' | |
| 104 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s1,s0,#0' | |
| 105 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s30,s0,#0' | |
| 106 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s1,#0' | |
| 107 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s30,#0' | |
| 108 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#0' | |
| 109 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#60' | |
| 110 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#2' | |
| 111 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#1' | |
| 112 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p7,d0,d0,#0' | |
| 113 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d15,d0,#0' | |
| 114 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d15,#0' | |
| 115 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#0' | |
| 116 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#6' | |
| 117 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#1' | |
| 118 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p7,s0,s0,s0,#0' | |
| 119 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s1,s0,s0,#0' | |
| 120 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s30,s0,s0,#0' | |
| 121 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s1,s0,#0' | |
| 122 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s30,s0,#0' | |
| 123 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s1,#0' | |
| 124 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s30,#0' | |
| 125 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#0' | |
| 126 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#6' | |
| 127 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#1' | |
| 128 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p7,d0,d0,d0,#0' | |
| 129 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d15,d0,d0,#0' | |
| 130 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d15,d0,#0' | |
| 131 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d15,#0' | |
| 132 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#0' | |
| 133 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#6' | |
| 134 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#1' | |
| 135 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p7,s0,s0,s0,#0' | |
| 136 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s1,s0,s0,#0' | |
| 137 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s30,s0,s0,#0' | |
| 138 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s1,s0,#0' | |
| 139 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s30,s0,#0' | |
| 140 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s1,#0' | |
| 141 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s30,#0' | |
| 142 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#0' | |
| 143 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#6' | |
| 144 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#1' | |
| 145 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p7,d0,d0,d0,#0' | |
| 146 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d15,d0,d0,#0' | |
| 147 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d15,d0,#0' | |
| 148 | [^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d15,#0' |