[BINUTILS, AArch64] Enable Transactional Memory Extension
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / copro-arm_v2plus-thumb_v6t2plus.s
CommitLineData
4070243b 1.syntax unified
252b5132
RH
2.text
3.align 0
4 cdp p1, 4, cr1, cr2, cr3
5 cdpeq 4, 3, c1, c4, cr5, 5
6
7 ldc 5, cr9, [r3]
8 ldcl 1, cr14, [r1, #32]
9 ldcmi 0, cr0, [r2, #1020]!
4070243b 10 ldclpl p7, c1, [r3], #64
252b5132
RH
11 ldc p0, c8, foo
12foo:
13
14 stc 5, cr0, [r3]
15 stcl 3, cr15, [r0, #8]
16 stceq p4, cr12, [r2, #100]!
17 stccc p6, c8, [r4], #48
18 stc p1, c7, bar
19bar:
20
21 mrc 2, 3, r5, c1, c2
22 mrcge p4, 5, r15, cr1, cr2, 7
23
fdfde340 24 mcr p7, 1, r5, cr1, cr1
252b5132 25 mcrlt 5, 1, r8, cr2, cr9, 0
f02232aa
NC
26
27 @ The following patterns test Addressing Mode 5 "Unindexed"
f02232aa
NC
28 ldc 3, c7, [r0], {0}
29 stc p14, c6, [r1], {1}
4070243b
TP
30 ldcl 7, c3, [r4], {4}
31 stcl p8, c2, [r5], {5}
32 @ using '11' below results in an (invalid) Neon vldmia instruction.
33 ldcl 12, c8, [r8], {255}
34 stcl p12, c9, [r9], {254}
0bbf2aa4
NC
35
36 # Extra instructions to allow for code alignment in arm-aout target.
37 nop
38 nop
db472d6f
MGD
39
40 # UAL-syntax for MRC with APSR. Pre-UAL was PC
41 mrcge p4, 5, APSR_nzcv, cr1, cr2, 7
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