[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / mask_1-armv8-r.d

#objdump: -dr --prefix-address --show-raw-insn
#name: ARMv8-R vsel, vmaxnm, vminnm, vrint decoding mask.
#source: mask_1-armv8-ar.s
#as: -march=armv8-r
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*

# Test VFMA instruction disassembly

.*: *file format .*arm.*


Disassembly of section .text:
0+000 <.*> fe011a10 	mcr2	10, 0, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
0+004 <.*> fe011b10 	mcr2	11, 0, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
0+008 <.*> fe811a10 	mcr2	10, 4, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
0+00c <.*> fe811b10 	mcr2	11, 4, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
0+010 <.*> fe811a50 	mcr2	10, 4, r1, cr1, cr0, \{2\}	; <UNPREDICTABLE>
0+014 <.*> fe811b50 	mcr2	11, 4, r1, cr1, cr0, \{2\}	; <UNPREDICTABLE>
0+018 <.*> fefb0ae0 			; <UNDEFINED> instruction: 0xfefb0ae0
0+01c <.*> fefb0be0 			; <UNDEFINED> instruction: 0xfefb0be0
0+020 <.*> fefb0ae0 			; <UNDEFINED> instruction: 0xfefb0ae0
0+024 <.*> fefb0be0 			; <UNDEFINED> instruction: 0xfefb0be0
0+028 <.*> fef80ae0 			; <UNDEFINED> instruction: 0xfef80ae0
0+02c <.*> fef80be0 			; <UNDEFINED> instruction: 0xfef80be0
0+030 <.*> fef90ae0 			; <UNDEFINED> instruction: 0xfef90ae0
0+034 <.*> fef90be0 			; <UNDEFINED> instruction: 0xfef90be0
0+038 <.*> fefa0ae0 			; <UNDEFINED> instruction: 0xfefa0ae0
0+03c <.*> fefa0be0 			; <UNDEFINED> instruction: 0xfefa0be0
Commit	Line	Data
3e309328	1	#objdump: -dr --prefix-address --show-raw-insn
ced40572 TP	2	#name: ARMv8-R vsel, vmaxnm, vminnm, vrint decoding mask.
	3	#source: mask_1-armv8-ar.s
	4	#as: -march=armv8-r
3e309328 RL	5	# This test is only valid on ELF based ports.
	6	#not-target: --coff --pe --wince --aout* --netbsd --riscix*
	7
	8	# Test VFMA instruction disassembly
	9
	10	.: file format .arm.
	11
	12
	13	Disassembly of section .text:
	14	0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
	15	0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
	16	0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
	17	0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
	18	0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
	19	0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
	20	0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
	21	0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
	22	0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
	23	0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
	24	0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0
	25	0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0
	26	0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0
	27	0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0
	28	0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0
	29	0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0