Commit | Line | Data |
---|---|---|
3e309328 RL |
1 | #objdump: -dr --prefix-address --show-raw-insn |
2 | #name: vsel, vmaxnm, vminnm, vrint decoding mask. | |
3 | #as: -march=armv8-a | |
4 | # This test is only valid on ELF based ports. | |
5 | #not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* | |
6 | ||
7 | # Test VFMA instruction disassembly | |
8 | ||
9 | .*: *file format .*arm.* | |
10 | ||
11 | ||
12 | Disassembly of section .text: | |
13 | 0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE> | |
14 | 0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE> | |
15 | 0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE> | |
16 | 0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE> | |
17 | 0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE> | |
18 | 0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE> | |
19 | 0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0 | |
20 | 0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0 | |
21 | 0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0 | |
22 | 0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0 | |
23 | 0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0 | |
24 | 0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0 | |
25 | 0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0 | |
26 | 0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0 | |
27 | 0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0 | |
28 | 0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0 |