[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / mve-vbrsr-bad.l

[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Error: bad type in SIMD instruction -- `vbrsr.64 q0,q1,r2'
[^:]*:12: Error: ARM register expected -- `vbrsr.32 q0,q1,q2'
[^:]*:14: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:15: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:17: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:19: Error: instruction missing MVE vector predication code -- `vbrsr.32 q0,q1,r2'
[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vbrsrt.32 q0,q1,r2'
Commit	Line	Data
c2dafc2a AV	1	[^:]*: Assembler messages:
	2	[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
	3	[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
	4	[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
	5	[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
	6	[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
	7	[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
	8	[^:]*:11: Error: bad type in SIMD instruction -- `vbrsr.64 q0,q1,r2'
	9	[^:]*:12: Error: ARM register expected -- `vbrsr.32 q0,q1,q2'
	10	[^:]*:14: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
	11	[^:]*:15: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
	12	[^:]*:17: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
	13	[^:]*:19: Error: instruction missing MVE vector predication code -- `vbrsr.32 q0,q1,r2'
	14	[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vbrsrt.32 q0,q1,r2'