projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4d6ac854 AV |
1 | # name: MVE vcvt instructions, part 3 |
| 2 | # as: -march=armv8.1-m.main+mve.fp | |
| 3 | # objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main | |
| 4 | ||
| 5 | .*: +file format .*arm.* | |
| 6 | ||
| 7 | Disassembly of section .text: | |
| 8 | [^>]*> ee3f 1e01 vcvtt.f16.f32 q0, q0 | |
| 9 | [^>]*> ee3f 0e01 vcvtb.f16.f32 q0, q0 | |
| 10 | [^>]*> ee3f 1e05 vcvtt.f16.f32 q0, q2 | |
| 11 | [^>]*> ee3f 0e05 vcvtb.f16.f32 q0, q2 | |
| 12 | [^>]*> ee3f 1e09 vcvtt.f16.f32 q0, q4 | |
| 13 | [^>]*> ee3f 0e09 vcvtb.f16.f32 q0, q4 | |
| 14 | [^>]*> ee3f 1e11 ; <UNDEFINED> instruction: 0xee3f1e11 | |
| 15 | [^>]*> ee3f 0e11 ; <UNDEFINED> instruction: 0xee3f0e11 | |
| 16 | [^>]*> ee3f 1e1d ; <UNDEFINED> instruction: 0xee3f1e1d | |
| 17 | [^>]*> ee3f 0e1d ; <UNDEFINED> instruction: 0xee3f0e1d | |
| 18 | [^>]*> ee3f 5e01 vcvtt.f16.f32 q2, q0 | |
| 19 | [^>]*> ee3f 4e01 vcvtb.f16.f32 q2, q0 | |
| 20 | [^>]*> ee3f 5e05 vcvtt.f16.f32 q2, q2 | |
| 21 | [^>]*> ee3f 4e05 vcvtb.f16.f32 q2, q2 | |
| 22 | [^>]*> ee3f 5e09 vcvtt.f16.f32 q2, q4 | |
| 23 | [^>]*> ee3f 4e09 vcvtb.f16.f32 q2, q4 | |
| 24 | [^>]*> ee3f 5e11 ; <UNDEFINED> instruction: 0xee3f5e11 | |
| 25 | [^>]*> ee3f 4e11 ; <UNDEFINED> instruction: 0xee3f4e11 | |
| 26 | [^>]*> ee3f 5e1d ; <UNDEFINED> instruction: 0xee3f5e1d | |
| 27 | [^>]*> ee3f 4e1d ; <UNDEFINED> instruction: 0xee3f4e1d | |
| 28 | [^>]*> ee3f 9e01 vcvtt.f16.f32 q4, q0 | |
| 29 | [^>]*> ee3f 8e01 vcvtb.f16.f32 q4, q0 | |
| 30 | [^>]*> ee3f 9e05 vcvtt.f16.f32 q4, q2 | |
| 31 | [^>]*> ee3f 8e05 vcvtb.f16.f32 q4, q2 | |
| 32 | [^>]*> ee3f 9e09 vcvtt.f16.f32 q4, q4 | |
| 33 | [^>]*> ee3f 8e09 vcvtb.f16.f32 q4, q4 | |
| 34 | [^>]*> ee3f 9e11 ; <UNDEFINED> instruction: 0xee3f9e11 | |
| 35 | [^>]*> ee3f 8e11 ; <UNDEFINED> instruction: 0xee3f8e11 | |
| 36 | [^>]*> ee3f 9e1d ; <UNDEFINED> instruction: 0xee3f9e1d | |
| 37 | [^>]*> ee3f 8e1d ; <UNDEFINED> instruction: 0xee3f8e1d | |
| 38 | [^>]*> ee3f 1e01 vcvtt.f16.f32 q0, q0 | |
| 39 | [^>]*> ee3f 0e01 vcvtb.f16.f32 q0, q0 | |
| 40 | [^>]*> ee3f 1e05 vcvtt.f16.f32 q0, q2 | |
| 41 | [^>]*> ee3f 0e05 vcvtb.f16.f32 q0, q2 | |
| 42 | [^>]*> ee3f 1e09 vcvtt.f16.f32 q0, q4 | |
| 43 | [^>]*> ee3f 0e09 vcvtb.f16.f32 q0, q4 | |
| 44 | [^>]*> ee3f 1e11 ; <UNDEFINED> instruction: 0xee3f1e11 | |
| 45 | [^>]*> ee3f 0e11 ; <UNDEFINED> instruction: 0xee3f0e11 | |
| 46 | [^>]*> ee3f 1e1d ; <UNDEFINED> instruction: 0xee3f1e1d | |
| 47 | [^>]*> ee3f 0e1d ; <UNDEFINED> instruction: 0xee3f0e1d | |
| 48 | [^>]*> ee3f de01 vcvtt.f16.f32 q6, q0 | |
| 49 | [^>]*> ee3f ce01 vcvtb.f16.f32 q6, q0 | |
| 50 | [^>]*> ee3f de05 vcvtt.f16.f32 q6, q2 | |
| 51 | [^>]*> ee3f ce05 vcvtb.f16.f32 q6, q2 | |
| 52 | [^>]*> ee3f de09 vcvtt.f16.f32 q6, q4 | |
| 53 | [^>]*> ee3f ce09 vcvtb.f16.f32 q6, q4 | |
| 54 | [^>]*> ee3f de11 ; <UNDEFINED> instruction: 0xee3fde11 | |
| 55 | [^>]*> ee3f ce11 ; <UNDEFINED> instruction: 0xee3fce11 | |
| 56 | [^>]*> ee3f de1d ; <UNDEFINED> instruction: 0xee3fde1d | |
| 57 | [^>]*> ee3f ce1d ; <UNDEFINED> instruction: 0xee3fce1d | |
| 58 | [^>]*> fe3f 1e01 vcvtt.f32.f16 q0, q0 | |
| 59 | [^>]*> fe3f 0e01 vcvtb.f32.f16 q0, q0 | |
| 60 | [^>]*> fe3f 1e05 vcvtt.f32.f16 q0, q2 | |
| 61 | [^>]*> fe3f 0e05 vcvtb.f32.f16 q0, q2 | |
| 62 | [^>]*> fe3f 1e09 vcvtt.f32.f16 q0, q4 | |
| 63 | [^>]*> fe3f 0e09 vcvtb.f32.f16 q0, q4 | |
| 64 | [^>]*> fe3f 1e11 ; <UNDEFINED> instruction: 0xfe3f1e11 | |
| 65 | [^>]*> fe3f 0e11 ; <UNDEFINED> instruction: 0xfe3f0e11 | |
| 66 | [^>]*> fe3f 1e1d ; <UNDEFINED> instruction: 0xfe3f1e1d | |
| 67 | [^>]*> fe3f 0e1d ; <UNDEFINED> instruction: 0xfe3f0e1d | |
| 68 | [^>]*> fe3f 5e01 vcvtt.f32.f16 q2, q0 | |
| 69 | [^>]*> fe3f 4e01 vcvtb.f32.f16 q2, q0 | |
| 70 | [^>]*> fe3f 5e05 vcvtt.f32.f16 q2, q2 | |
| 71 | [^>]*> fe3f 4e05 vcvtb.f32.f16 q2, q2 | |
| 72 | [^>]*> fe3f 5e09 vcvtt.f32.f16 q2, q4 | |
| 73 | [^>]*> fe3f 4e09 vcvtb.f32.f16 q2, q4 | |
| 74 | [^>]*> fe3f 5e11 ; <UNDEFINED> instruction: 0xfe3f5e11 | |
| 75 | [^>]*> fe3f 4e11 ; <UNDEFINED> instruction: 0xfe3f4e11 | |
| 76 | [^>]*> fe3f 5e1d ; <UNDEFINED> instruction: 0xfe3f5e1d | |
| 77 | [^>]*> fe3f 4e1d ; <UNDEFINED> instruction: 0xfe3f4e1d | |
| 78 | [^>]*> fe3f 9e01 vcvtt.f32.f16 q4, q0 | |
| 79 | [^>]*> fe3f 8e01 vcvtb.f32.f16 q4, q0 | |
| 80 | [^>]*> fe3f 9e05 vcvtt.f32.f16 q4, q2 | |
| 81 | [^>]*> fe3f 8e05 vcvtb.f32.f16 q4, q2 | |
| 82 | [^>]*> fe3f 9e09 vcvtt.f32.f16 q4, q4 | |
| 83 | [^>]*> fe3f 8e09 vcvtb.f32.f16 q4, q4 | |
| 84 | [^>]*> fe3f 9e11 ; <UNDEFINED> instruction: 0xfe3f9e11 | |
| 85 | [^>]*> fe3f 8e11 ; <UNDEFINED> instruction: 0xfe3f8e11 | |
| 86 | [^>]*> fe3f 9e1d ; <UNDEFINED> instruction: 0xfe3f9e1d | |
| 87 | [^>]*> fe3f 8e1d ; <UNDEFINED> instruction: 0xfe3f8e1d | |
| 88 | [^>]*> fe3f 1e01 vcvtt.f32.f16 q0, q0 | |
| 89 | [^>]*> fe3f 0e01 vcvtb.f32.f16 q0, q0 | |
| 90 | [^>]*> fe3f 1e05 vcvtt.f32.f16 q0, q2 | |
| 91 | [^>]*> fe3f 0e05 vcvtb.f32.f16 q0, q2 | |
| 92 | [^>]*> fe3f 1e09 vcvtt.f32.f16 q0, q4 | |
| 93 | [^>]*> fe3f 0e09 vcvtb.f32.f16 q0, q4 | |
| 94 | [^>]*> fe3f 1e11 ; <UNDEFINED> instruction: 0xfe3f1e11 | |
| 95 | [^>]*> fe3f 0e11 ; <UNDEFINED> instruction: 0xfe3f0e11 | |
| 96 | [^>]*> fe3f 1e1d ; <UNDEFINED> instruction: 0xfe3f1e1d | |
| 97 | [^>]*> fe3f 0e1d ; <UNDEFINED> instruction: 0xfe3f0e1d | |
| 98 | [^>]*> fe3f de01 vcvtt.f32.f16 q6, q0 | |
| 99 | [^>]*> fe3f ce01 vcvtb.f32.f16 q6, q0 | |
| 100 | [^>]*> fe3f de05 vcvtt.f32.f16 q6, q2 | |
| 101 | [^>]*> fe3f ce05 vcvtb.f32.f16 q6, q2 | |
| 102 | [^>]*> fe3f de09 vcvtt.f32.f16 q6, q4 | |
| 103 | [^>]*> fe3f ce09 vcvtb.f32.f16 q6, q4 | |
| 104 | [^>]*> fe3f de11 ; <UNDEFINED> instruction: 0xfe3fde11 | |
| 105 | [^>]*> fe3f ce11 ; <UNDEFINED> instruction: 0xfe3fce11 | |
| 106 | [^>]*> fe3f de1d ; <UNDEFINED> instruction: 0xfe3fde1d | |
| 107 | [^>]*> fe3f ce1d ; <UNDEFINED> instruction: 0xfe3fce1d | |
| 108 | [^>]*> fe31 af4d vpsttee | |
| 109 | [^>]*> ee3f 1e05 vcvttt.f16.f32 q0, q2 | |
| 110 | [^>]*> ee3f 0e05 vcvtbt.f16.f32 q0, q2 | |
| 111 | [^>]*> fe3f 5e09 vcvtte.f32.f16 q2, q4 | |
| 112 | [^>]*> fe3f 4e09 vcvtbe.f32.f16 q2, q4 |