[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / mve-vdup-bad.l

[^:]*: Assembler messages:
[^:]*:11: Error: bad type in SIMD instruction -- `vdup.64 q0,r1'
[^:]*:12: Error: selected FPU does not support instruction -- `vdup.32 q0,d0\[1\]'
[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Error: syntax error -- `vdupeq.32 q0,r2'
[^:]*:18: Error: syntax error -- `vdupeq.32 q0,r2'
[^:]*:20: Error: syntax error -- `vdupeq.32 q0,r2'
[^:]*:21: Error: incorrect condition in VPT/VPST block -- `vdupt.32 q0,r2'
[^:]*:23: Error: instruction missing MVE vector predication code -- `vdup.32 q0,r2'
Commit	Line	Data
b409bdb6 AV	1	[^:]*: Assembler messages:
	2	[^:]*:11: Error: bad type in SIMD instruction -- `vdup.64 q0,r1'
	3	[^:]*:12: Error: selected FPU does not support instruction -- `vdup.32 q0,d0\[1\]'
	4	[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand
	5	[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
	6	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	7	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	8	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	9	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	10	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	11	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	12	[^:]*:17: Error: syntax error -- `vdupeq.32 q0,r2'
	13	[^:]*:18: Error: syntax error -- `vdupeq.32 q0,r2'
	14	[^:]*:20: Error: syntax error -- `vdupeq.32 q0,r2'
	15	[^:]*:21: Error: incorrect condition in VPT/VPST block -- `vdupt.32 q0,r2'
	16	[^:]*:23: Error: instruction missing MVE vector predication code -- `vdup.32 q0,r2'