[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / mve-vmax-vmin-bad.l

[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2'
[^:]*:11: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2'
[^:]*:12: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2'
[^:]*:13: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2'
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
[^:]*:18: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
[^:]*:20: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxt.s16 q0,q1,q2'
[^:]*:23: Error: instruction missing MVE vector predication code -- `vmax.s16 q0,q1,q2'
[^:]*:25: Error: syntax error -- `vmineq.u32 q0,q1,q2'
[^:]*:26: Error: syntax error -- `vmineq.u32 q0,q1,q2'
[^:]*:28: Error: syntax error -- `vmineq.u32 q0,q1,q2'
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmint.u32 q0,q1,q2'
[^:]*:31: Error: instruction missing MVE vector predication code -- `vmin.u32 q0,q1,q2'
Commit	Line	Data
935295b5 AV	1	[^:]*: Assembler messages:
	2	[^:]*:10: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2'
	3	[^:]*:11: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2'
	4	[^:]*:12: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2'
	5	[^:]*:13: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2'
	6	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	7	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	8	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	9	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	10	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	11	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	12	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	13	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	14	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	15	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	16	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	17	[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
	18	[^:]*:17: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
	19	[^:]*:18: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
	20	[^:]*:20: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
	21	[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxt.s16 q0,q1,q2'
	22	[^:]*:23: Error: instruction missing MVE vector predication code -- `vmax.s16 q0,q1,q2'
	23	[^:]*:25: Error: syntax error -- `vmineq.u32 q0,q1,q2'
	24	[^:]*:26: Error: syntax error -- `vmineq.u32 q0,q1,q2'
	25	[^:]*:28: Error: syntax error -- `vmineq.u32 q0,q1,q2'
	26	[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmint.u32 q0,q1,q2'
	27	[^:]*:31: Error: instruction missing MVE vector predication code -- `vmin.u32 q0,q1,q2'