projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a302e574 AV |
1 | [^:]*: Assembler messages: |
| 2 | [^:]*:10: Error: Odd register not allowed here -- `vmlsdav.s16 r1,q1,q2' | |
| 3 | [^:]*:11: Error: bad type in SIMD instruction -- `vmlsdav.u16 r0,q1,q2' | |
| 4 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
| 5 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
| 6 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
| 7 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
| 8 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
| 9 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
| 10 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
| 11 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
| 12 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
| 13 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
| 14 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
| 15 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
| 16 | [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block | |
| 17 | [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block | |
| 18 | [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block | |
| 19 | [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block | |
| 20 | [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block | |
| 21 | [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block | |
| 22 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 23 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 24 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 25 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 26 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 27 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 28 | [^:]*:17: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' | |
| 29 | [^:]*:18: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' | |
| 30 | [^:]*:20: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' | |
| 31 | [^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavt.s16 r0,q1,q2' | |
| 32 | [^:]*:23: Error: instruction missing MVE vector predication code -- `vmlsdav.s16 r0,q1,q2' | |
| 33 | [^:]*:25: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' | |
| 34 | [^:]*:26: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' | |
| 35 | [^:]*:28: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' | |
| 36 | [^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavat.s16 r0,q1,q2' | |
| 37 | [^:]*:31: Error: instruction missing MVE vector predication code -- `vmlsdava.s16 r0,q1,q2' | |
| 38 | [^:]*:33: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' | |
| 39 | [^:]*:34: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' | |
| 40 | [^:]*:36: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' | |
| 41 | [^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavxt.s16 r0,q1,q2' | |
| 42 | [^:]*:39: Error: instruction missing MVE vector predication code -- `vmlsdavx.s16 r0,q1,q2' | |
| 43 | [^:]*:41: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' | |
| 44 | [^:]*:42: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' | |
| 45 | [^:]*:44: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' | |
| 46 | [^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavaxt.s16 r0,q1,q2' | |
| 47 | [^:]*:47: Error: instruction missing MVE vector predication code -- `vmlsdavax.s16 r0,q1,q2' |