Commit | Line | Data |
---|---|---|
4d6ac854 AV |
1 | .syntax unified |
2 | .thumb | |
3 | ||
4 | .macro all_vstr op, imm | |
5 | .irp op1, q0, q1, q2, q4, q7 | |
6 | .irp op2, q0, q1, q2, q4, q7 | |
7 | \op \op1, [\op2, #\imm] | |
8 | \op \op1, [\op2, #-\imm] | |
9 | \op \op1, [\op2, #\imm]! | |
10 | \op \op1, [\op2, #-\imm]! | |
11 | .endr | |
12 | .endr | |
13 | .endm | |
14 | ||
15 | .irp data, .32, .u32, .s32, .f32 | |
16 | .irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 480 | |
17 | all_vstr vstrw\data, \imm | |
18 | .endr | |
19 | .endr | |
20 | ||
21 | .irp data, .64, .u64, .s64 | |
22 | .irp imm, 0, 8, 16, 32, 64, 128, 256, 512, 1016, 680, 336, 960, 120 | |
23 | all_vstr vstrd\data, \imm | |
24 | .endr | |
25 | .endr | |
26 | ||
27 | ||
28 | vpstete | |
29 | vstrwt.32 q0, [q1, #4] | |
30 | vstrwe.u32 q1, [q0, #-4] | |
31 | vstrwt.s32 q2, [q2] | |
32 | vstrwe.f32 q3, [q4, #-508] | |
33 | vpstet | |
34 | vstrdt.64 q4, [q5, #512] | |
35 | vstrde.u64 q5, [q6, #1016] | |
36 | vstrdt.s64 q6, [q7, #-1016] | |
37 | ||
38 | .macro all_vldr_qq op, op1, op2, imm | |
39 | \op \op1, [\op2, #\imm] | |
40 | \op \op1, [\op2, #-\imm] | |
41 | \op \op1, [\op2, #\imm]! | |
42 | \op \op1, [\op2, #-\imm]! | |
43 | .endm | |
44 | ||
45 | .macro all_vldr_q0 op, imm | |
46 | .irp op2, q1, q2, q4, q7 | |
47 | all_vldr_qq \op, q0, \op2, \imm | |
48 | .endr | |
49 | .endm | |
50 | ||
51 | .macro all_vldr_q1 op, imm | |
52 | .irp op2, q0, q2, q4, q7 | |
53 | all_vldr_qq \op, q1, \op2, \imm | |
54 | .endr | |
55 | .endm | |
56 | ||
57 | .macro all_vldr_q2 op, imm | |
58 | .irp op2, q0, q1, q4, q7 | |
59 | all_vldr_qq \op, q2, \op2, \imm | |
60 | .endr | |
61 | .endm | |
62 | ||
63 | .macro all_vldr_q4 op, imm | |
64 | .irp op2, q0, q1, q2, q7 | |
65 | all_vldr_qq \op, q4, \op2, \imm | |
66 | .endr | |
67 | .endm | |
68 | ||
69 | .macro all_vldr_q7 op, imm | |
70 | .irp op2, q0, q1, q2, q4 | |
71 | all_vldr_qq \op, q7, \op2, \imm | |
72 | .endr | |
73 | .endm | |
74 | ||
75 | .macro all_vldr op, imm | |
76 | all_vldr_q0 \op, \imm | |
77 | all_vldr_q1 \op, \imm | |
78 | all_vldr_q2 \op, \imm | |
79 | all_vldr_q4 \op, \imm | |
80 | all_vldr_q7 \op, \imm | |
81 | .endm | |
82 | ||
83 | .irp data, .32, .u32, .s32, .f32 | |
84 | .irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 480 | |
85 | all_vldr vldrw\data, \imm | |
86 | .endr | |
87 | .endr | |
88 | ||
89 | .irp data, .64, .u64, .s64 | |
90 | .irp imm, 0, 8, 16, 32, 64, 128, 256, 512, 1016, 680, 336, 960, 120 | |
91 | all_vldr vldrd\data, \imm | |
92 | .endr | |
93 | .endr | |
94 | ||
95 | vpstete | |
96 | vldrwt.32 q0, [q1, #4] | |
97 | vldrwe.u32 q1, [q0, #-4] | |
98 | vldrwt.s32 q2, [q3] | |
99 | vldrwe.f32 q3, [q4, #-508] | |
100 | vpstet | |
101 | vldrdt.64 q4, [q5, #512] | |
102 | vldrde.u64 q5, [q6, #1016] | |
103 | vldrdt.s64 q6, [q7, #-1016] |