projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| edd40341 JB |
1 | @ Neon tests. Basic bitfield tests, using zero for as many registers/fields as |
| 2 | @ possible, but without causing instructions to be badly-formed. | |
| 3 | ||
| 4 | .arm | |
| 5 | .syntax unified | |
| 6 | .text | |
| 7 | ||
| 8 | .macro regs3_1 op opq vtype | |
| 9 | \op\vtype q0,q0,q0 | |
| 10 | \opq\vtype q0,q0,q0 | |
| 11 | \op\vtype d0,d0,d0 | |
| 12 | .endm | |
| 13 | ||
| 14 | .macro dregs3_1 op vtype | |
| 15 | \op\vtype d0,d0,d0 | |
| 16 | .endm | |
| 17 | ||
| 18 | .macro regn3_1 op operand2 vtype | |
| 19 | \op\vtype d0,q0,\operand2 | |
| 20 | .endm | |
| 21 | ||
| 22 | .macro regl3_1 op operand2 vtype | |
| 23 | \op\vtype q0,d0,\operand2 | |
| 24 | .endm | |
| 25 | ||
| 26 | .macro regw3_1 op operand2 vtype | |
| 27 | \op\vtype q0,q0,\operand2 | |
| 28 | .endm | |
| 29 | ||
| 30 | .macro regs2_1 op opq vtype | |
| 31 | \op\vtype q0,q0 | |
| 32 | \opq\vtype q0,q0 | |
| 33 | \op\vtype d0,d0 | |
| 34 | .endm | |
| 35 | ||
| 36 | .macro regs3_su_32 op opq | |
| 37 | regs3_1 \op \opq .s8 | |
| 38 | regs3_1 \op \opq .s16 | |
| 39 | regs3_1 \op \opq .s32 | |
| 40 | regs3_1 \op \opq .u8 | |
| 41 | regs3_1 \op \opq .u16 | |
| 42 | regs3_1 \op \opq .u32 | |
| 43 | .endm | |
| 44 | ||
| 45 | regs3_su_32 vaba vabaq | |
| 46 | regs3_su_32 vhadd vhaddq | |
| 47 | regs3_su_32 vrhadd vrhaddq | |
| 48 | regs3_su_32 vhsub vhsubq | |
| 49 | ||
| 50 | .macro regs3_su_64 op opq | |
| 51 | regs3_1 \op \opq .s8 | |
| 52 | regs3_1 \op \opq .s16 | |
| 53 | regs3_1 \op \opq .s32 | |
| 54 | regs3_1 \op \opq .s64 | |
| 55 | regs3_1 \op \opq .u8 | |
| 56 | regs3_1 \op \opq .u16 | |
| 57 | regs3_1 \op \opq .u32 | |
| 58 | regs3_1 \op \opq .u64 | |
| 59 | .endm | |
| 60 | ||
| 61 | regs3_su_64 vqadd vqaddq | |
| 62 | regs3_su_64 vqsub vqsubq | |
| 63 | regs3_su_64 vrshl vrshlq | |
| 64 | regs3_su_64 vqrshl vqrshlq | |
| 65 | ||
| 66 | regs3_su_64 vshl vshlq | |
| 67 | regs3_su_64 vqshl vqshlq | |
| 68 | ||
| 69 | .macro regs2i_1 op opq imm vtype | |
| 70 | \op\vtype q0,q0,\imm | |
| 71 | \opq\vtype q0,q0,\imm | |
| 72 | \op\vtype d0,d0,\imm | |
| 73 | .endm | |
| 74 | ||
| 75 | .macro regs2i_su_64 op opq imm | |
| 76 | regs2i_1 \op \opq \imm .s8 | |
| 77 | regs2i_1 \op \opq \imm .s16 | |
| 78 | regs2i_1 \op \opq \imm .s32 | |
| 79 | regs2i_1 \op \opq \imm .s64 | |
| 80 | regs2i_1 \op \opq \imm .u8 | |
| 81 | regs2i_1 \op \opq \imm .u16 | |
| 82 | regs2i_1 \op \opq \imm .u32 | |
| 83 | regs2i_1 \op \opq \imm .u64 | |
| 84 | .endm | |
| 85 | ||
| 86 | .macro regs2i_i_64 op opq imm | |
| 87 | regs2i_1 \op \opq \imm .i8 | |
| 88 | regs2i_1 \op \opq \imm .i16 | |
| 89 | regs2i_1 \op \opq \imm .i32 | |
| 428e3f1f PB |
90 | regs2i_1 \op \opq \imm .s32 |
| 91 | regs2i_1 \op \opq \imm .u32 | |
| edd40341 JB |
92 | regs2i_1 \op \opq \imm .i64 |
| 93 | .endm | |
| 94 | ||
| 95 | regs2i_i_64 vshl vshlq 0 | |
| 96 | regs2i_su_64 vqshl vqshlq 0 | |
| 97 | ||
| 98 | .macro regs3_ntyp op opq | |
| 99 | regs3_1 \op \opq .8 | |
| 100 | .endm | |
| 101 | ||
| 102 | regs3_ntyp vand vandq | |
| 103 | regs3_ntyp vbic vbicq | |
| 104 | regs3_ntyp vorr vorrq | |
| 105 | regs3_ntyp vorn vornq | |
| 106 | regs3_ntyp veor veorq | |
| 107 | ||
| 108 | .macro logic_imm_1 op opq imm vtype | |
| 109 | \op\vtype q0,\imm | |
| 110 | \opq\vtype q0,\imm | |
| 111 | \op\vtype d0,\imm | |
| 112 | .endm | |
| 113 | ||
| 114 | .macro logic_imm op opq | |
| 115 | logic_imm_1 \op \opq 0x000000ff .i32 | |
| 428e3f1f PB |
116 | logic_imm_1 \op \opq 0x000000ff .s32 |
| 117 | logic_imm_1 \op \opq 0x000000ff .u32 | |
| edd40341 JB |
118 | logic_imm_1 \op \opq 0x0000ff00 .i32 |
| 119 | logic_imm_1 \op \opq 0x00ff0000 .i32 | |
| 120 | logic_imm_1 \op \opq 0xff000000 .i32 | |
| 121 | logic_imm_1 \op \opq 0x00ff .i16 | |
| 122 | logic_imm_1 \op \opq 0xff00 .i16 | |
| 123 | .endm | |
| 124 | ||
| 125 | logic_imm vbic vbicq | |
| 126 | logic_imm vorr vorrq | |
| 127 | ||
| 128 | .macro logic_inv_imm op opq | |
| 129 | logic_imm_1 \op \opq 0xffffff00 .i32 | |
| 428e3f1f PB |
130 | logic_imm_1 \op \opq 0xffffff00 .s32 |
| 131 | logic_imm_1 \op \opq 0xffffff00 .u32 | |
| edd40341 JB |
132 | logic_imm_1 \op \opq 0xffff00ff .i32 |
| 133 | logic_imm_1 \op \opq 0xff00ffff .i32 | |
| 134 | logic_imm_1 \op \opq 0x00ffffff .i32 | |
| 135 | logic_imm_1 \op \opq 0xff00 .i16 | |
| 136 | logic_imm_1 \op \opq 0x00ff .i16 | |
| 137 | .endm | |
| 138 | ||
| 139 | logic_inv_imm vand vandq | |
| 140 | logic_inv_imm vorn vornq | |
| 141 | ||
| 142 | regs3_ntyp vbsl vbslq | |
| 143 | regs3_ntyp vbit vbitq | |
| 144 | regs3_ntyp vbif vbifq | |
| 145 | ||
| 146 | .macro regs3_suf_32 op opq | |
| 147 | regs3_1 \op \opq .s8 | |
| 148 | regs3_1 \op \opq .s16 | |
| 149 | regs3_1 \op \opq .s32 | |
| 150 | regs3_1 \op \opq .u8 | |
| 151 | regs3_1 \op \opq .u16 | |
| 152 | regs3_1 \op \opq .u32 | |
| 153 | regs3_1 \op \opq .f32 | |
| 154 | .endm | |
| 155 | ||
| 156 | .macro regs3_if_32 op opq | |
| 157 | regs3_1 \op \opq .i8 | |
| 158 | regs3_1 \op \opq .i16 | |
| 159 | regs3_1 \op \opq .i32 | |
| 428e3f1f PB |
160 | regs3_1 \op \opq .s32 |
| 161 | regs3_1 \op \opq .u32 | |
| edd40341 JB |
162 | regs3_1 \op \opq .f32 |
| 163 | .endm | |
| 164 | ||
| 165 | regs3_suf_32 vabd vabdq | |
| 166 | regs3_suf_32 vmax vmaxq | |
| 167 | regs3_suf_32 vmin vminq | |
| 168 | ||
| 169 | regs3_suf_32 vcge vcgeq | |
| 170 | regs3_suf_32 vcgt vcgtq | |
| 171 | regs3_suf_32 vcle vcleq | |
| 172 | regs3_suf_32 vclt vcltq | |
| 173 | ||
| 174 | regs3_if_32 vceq vceqq | |
| 175 | ||
| 176 | .macro regs2i_sf_0 op opq | |
| 177 | regs2i_1 \op \opq 0 .s8 | |
| 178 | regs2i_1 \op \opq 0 .s16 | |
| 179 | regs2i_1 \op \opq 0 .s32 | |
| 180 | regs2i_1 \op \opq 0 .f32 | |
| 181 | .endm | |
| 182 | ||
| 183 | regs2i_sf_0 vcge vcgeq | |
| 184 | regs2i_sf_0 vcgt vcgtq | |
| 185 | regs2i_sf_0 vcle vcleq | |
| 186 | regs2i_sf_0 vclt vcltq | |
| 187 | ||
| 188 | .macro regs2i_if_0 op opq | |
| 189 | regs2i_1 \op \opq 0 .i8 | |
| 190 | regs2i_1 \op \opq 0 .i16 | |
| 191 | regs2i_1 \op \opq 0 .i32 | |
| 428e3f1f PB |
192 | regs2i_1 \op \opq 0 .s32 |
| 193 | regs2i_1 \op \opq 0 .u32 | |
| edd40341 JB |
194 | regs2i_1 \op \opq 0 .f32 |
| 195 | .endm | |
| 196 | ||
| 197 | regs2i_if_0 vceq vceqq | |
| 198 | ||
| 199 | .macro dregs3_suf_32 op | |
| 200 | dregs3_1 \op .s8 | |
| 201 | dregs3_1 \op .s16 | |
| 202 | dregs3_1 \op .s32 | |
| 203 | dregs3_1 \op .u8 | |
| 204 | dregs3_1 \op .u16 | |
| 205 | dregs3_1 \op .u32 | |
| 206 | dregs3_1 \op .f32 | |
| 207 | .endm | |
| 208 | ||
| 209 | dregs3_suf_32 vpmax | |
| 210 | dregs3_suf_32 vpmin | |
| 211 | ||
| 212 | .macro sregs3_1 op opq vtype | |
| 213 | \op\vtype q0,q0,q0 | |
| 214 | \opq\vtype q0,q0,q0 | |
| 215 | \op\vtype d0,d0,d0 | |
| 216 | .endm | |
| 217 | ||
| 218 | .macro sclr21_1 op opq vtype | |
| 219 | \op\vtype q0,q0,d0[0] | |
| 220 | \opq\vtype q0,q0,d0[0] | |
| 221 | \op\vtype d0,d0,d0[0] | |
| 222 | .endm | |
| 223 | ||
| 224 | .macro mul_incl_scalar op opq | |
| 225 | regs3_1 \op \opq .i8 | |
| 226 | regs3_1 \op \opq .i16 | |
| 227 | regs3_1 \op \opq .i32 | |
| 428e3f1f PB |
228 | regs3_1 \op \opq .s32 |
| 229 | regs3_1 \op \opq .u32 | |
| edd40341 JB |
230 | regs3_1 \op \opq .f32 |
| 231 | sclr21_1 \op \opq .i16 | |
| 232 | sclr21_1 \op \opq .i32 | |
| 428e3f1f PB |
233 | sclr21_1 \op \opq .s32 |
| 234 | sclr21_1 \op \opq .u32 | |
| edd40341 JB |
235 | sclr21_1 \op \opq .f32 |
| 236 | .endm | |
| 237 | ||
| 238 | mul_incl_scalar vmla vmlaq | |
| 239 | mul_incl_scalar vmls vmlsq | |
| 240 | ||
| 241 | .macro dregs3_if_32 op | |
| 242 | dregs3_1 \op .i8 | |
| 243 | dregs3_1 \op .i16 | |
| 244 | dregs3_1 \op .i32 | |
| 428e3f1f PB |
245 | dregs3_1 \op .s32 |
| 246 | dregs3_1 \op .u32 | |
| edd40341 JB |
247 | dregs3_1 \op .f32 |
| 248 | .endm | |
| 249 | ||
| 250 | dregs3_if_32 vpadd | |
| 251 | ||
| 252 | .macro regs3_if_64 op opq | |
| 253 | regs3_1 \op \opq .i8 | |
| 254 | regs3_1 \op \opq .i16 | |
| 255 | regs3_1 \op \opq .i32 | |
| 428e3f1f PB |
256 | regs3_1 \op \opq .s32 |
| 257 | regs3_1 \op \opq .u32 | |
| edd40341 JB |
258 | regs3_1 \op \opq .i64 |
| 259 | regs3_1 \op \opq .f32 | |
| 260 | .endm | |
| 261 | ||
| 262 | regs3_if_64 vadd vaddq | |
| 263 | regs3_if_64 vsub vsubq | |
| 264 | ||
| 265 | .macro regs3_sz_32 op opq | |
| 266 | regs3_1 \op \opq .8 | |
| 267 | regs3_1 \op \opq .16 | |
| 268 | regs3_1 \op \opq .32 | |
| 269 | .endm | |
| 270 | ||
| 271 | regs3_sz_32 vtst vtstq | |
| 272 | ||
| 273 | .macro regs3_ifp_32 op opq | |
| 274 | regs3_1 \op \opq .i8 | |
| 275 | regs3_1 \op \opq .i16 | |
| 276 | regs3_1 \op \opq .i32 | |
| 428e3f1f PB |
277 | regs3_1 \op \opq .s32 |
| 278 | regs3_1 \op \opq .u32 | |
| edd40341 JB |
279 | regs3_1 \op \opq .f32 |
| 280 | regs3_1 \op \opq .p8 | |
| 281 | .endm | |
| 282 | ||
| 283 | regs3_ifp_32 vmul vmulq | |
| 284 | ||
| 285 | .macro dqmulhs op opq | |
| 286 | regs3_1 \op \opq .s16 | |
| 287 | regs3_1 \op \opq .s32 | |
| 288 | sclr21_1 \op \opq .s16 | |
| 289 | sclr21_1 \op \opq .s32 | |
| 290 | .endm | |
| 291 | ||
| 292 | dqmulhs vqdmulh vqdmulhq | |
| 293 | dqmulhs vqrdmulh vqrdmulhq | |
| 294 | ||
| 295 | regs3_1 vacge vacgeq .f32 | |
| 296 | regs3_1 vacgt vacgtq .f32 | |
| 297 | regs3_1 vacle vacleq .f32 | |
| 298 | regs3_1 vaclt vacltq .f32 | |
| 299 | regs3_1 vrecps vrecpsq .f32 | |
| 300 | regs3_1 vrsqrts vrsqrtsq .f32 | |
| 301 | ||
| 302 | .macro regs2_sf_32 op opq | |
| 303 | regs2_1 \op \opq .s8 | |
| 304 | regs2_1 \op \opq .s16 | |
| 305 | regs2_1 \op \opq .s32 | |
| 306 | regs2_1 \op \opq .f32 | |
| 307 | .endm | |
| 308 | ||
| 309 | regs2_sf_32 vabs vabsq | |
| 310 | regs2_sf_32 vneg vnegq | |
| 311 | ||
| 312 | .macro rshift_imm op opq | |
| 313 | regs2i_1 \op \opq 7 .s8 | |
| 314 | regs2i_1 \op \opq 15 .s16 | |
| 315 | regs2i_1 \op \opq 31 .s32 | |
| 316 | regs2i_1 \op \opq 63 .s64 | |
| 317 | regs2i_1 \op \opq 7 .u8 | |
| 318 | regs2i_1 \op \opq 15 .u16 | |
| 319 | regs2i_1 \op \opq 31 .u32 | |
| 320 | regs2i_1 \op \opq 63 .u64 | |
| 321 | .endm | |
| 322 | ||
| 323 | rshift_imm vshr vshrq | |
| 324 | rshift_imm vrshr vrshrq | |
| 325 | rshift_imm vsra vsraq | |
| 326 | rshift_imm vrsra vrsraq | |
| 327 | ||
| 328 | regs2i_1 vsli vsliq 0 .8 | |
| 329 | regs2i_1 vsli vsliq 0 .16 | |
| 330 | regs2i_1 vsli vsliq 0 .32 | |
| 331 | regs2i_1 vsli vsliq 0 .64 | |
| 332 | ||
| 333 | regs2i_1 vsri vsriq 7 .8 | |
| 334 | regs2i_1 vsri vsriq 15 .16 | |
| 335 | regs2i_1 vsri vsriq 31 .32 | |
| 336 | regs2i_1 vsri vsriq 63 .64 | |
| 337 | ||
| 338 | regs2i_1 vqshlu vqshluq 0 .s8 | |
| 339 | regs2i_1 vqshlu vqshluq 0 .s16 | |
| 340 | regs2i_1 vqshlu vqshluq 0 .s32 | |
| 341 | regs2i_1 vqshlu vqshluq 0 .s64 | |
| 342 | ||
| 343 | .macro qrshift_imm op | |
| 344 | regn3_1 \op 7 .s16 | |
| 345 | regn3_1 \op 15 .s32 | |
| 346 | regn3_1 \op 31 .s64 | |
| 347 | regn3_1 \op 7 .u16 | |
| 348 | regn3_1 \op 15 .u32 | |
| 349 | regn3_1 \op 31 .u64 | |
| 350 | .endm | |
| 351 | ||
| 352 | .macro qrshiftu_imm op | |
| 353 | regn3_1 \op 7 .s16 | |
| 354 | regn3_1 \op 15 .s32 | |
| 355 | regn3_1 \op 31 .s64 | |
| 356 | .endm | |
| 357 | ||
| 358 | .macro qrshifti_imm op | |
| 359 | regn3_1 \op 7 .i16 | |
| 360 | regn3_1 \op 15 .i32 | |
| 428e3f1f PB |
361 | regn3_1 \op 15 .s32 |
| 362 | regn3_1 \op 15 .u32 | |
| edd40341 JB |
363 | regn3_1 \op 31 .i64 |
| 364 | .endm | |
| 365 | ||
| 366 | qrshift_imm vqshrn | |
| 367 | qrshift_imm vqrshrn | |
| 368 | qrshiftu_imm vqshrun | |
| 369 | qrshiftu_imm vqrshrun | |
| 370 | ||
| 371 | qrshifti_imm vshrn | |
| 372 | qrshifti_imm vrshrn | |
| 373 | ||
| 374 | regl3_1 vshll 1 .s8 | |
| 375 | regl3_1 vshll 1 .s16 | |
| 376 | regl3_1 vshll 1 .s32 | |
| 377 | regl3_1 vshll 1 .u8 | |
| 378 | regl3_1 vshll 1 .u16 | |
| 379 | regl3_1 vshll 1 .u32 | |
| 380 | ||
| 381 | regl3_1 vshll 8 .i8 | |
| 382 | regl3_1 vshll 16 .i16 | |
| 383 | regl3_1 vshll 32 .i32 | |
| 428e3f1f PB |
384 | regl3_1 vshll 32 .s32 |
| 385 | regl3_1 vshll 32 .u32 | |
| edd40341 JB |
386 | |
| 387 | .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32" | |
| 388 | \op\t1 \opr,\opr\arg | |
| 389 | \op\t2 \opr,\opr\arg | |
| 390 | \op\t3 \opr,\opr\arg | |
| 391 | \op\t4 \opr,\opr\arg | |
| 392 | .endm | |
| 393 | ||
| 394 | convert vcvt q0 | |
| 395 | convert vcvtq q0 | |
| 396 | convert vcvt d0 | |
| 397 | convert vcvt q0 ",1" | |
| 398 | convert vcvtq q0 ",1" | |
| 399 | convert vcvt d0 ",1" | |
| 400 | ||
| 401 | vmov q0,q0 | |
| 402 | vmov d0,d0 | |
| 403 | vmov.8 d0[0],r0 | |
| 404 | vmov.16 d0[0],r0 | |
| 405 | vmov.32 d0[0],r0 | |
| 406 | vmov d0,r0,r0 | |
| 407 | vmov.s8 r0,d0[0] | |
| 408 | vmov.s16 r0,d0[0] | |
| 409 | vmov.u8 r0,d0[0] | |
| 410 | vmov.u16 r0,d0[0] | |
| 411 | vmov.32 r0,d0[0] | |
| 412 | vmov r0,r1,d0 | |
| 413 | ||
| 414 | .macro mov_imm op imm vtype | |
| 415 | \op\vtype q0,\imm | |
| 416 | \op\vtype d0,\imm | |
| 417 | .endm | |
| 418 | ||
| 419 | mov_imm vmov 0x00000077 .i32 | |
| 428e3f1f PB |
420 | mov_imm vmov 0x00000077 .s32 |
| 421 | mov_imm vmov 0x00000077 .u32 | |
| edd40341 | 422 | mov_imm vmvn 0x00000077 .i32 |
| 428e3f1f PB |
423 | mov_imm vmvn 0x00000077 .s32 |
| 424 | mov_imm vmvn 0x00000077 .u32 | |
| edd40341 JB |
425 | mov_imm vmov 0x00007700 .i32 |
| 426 | mov_imm vmvn 0x00007700 .i32 | |
| 427 | mov_imm vmov 0x00770000 .i32 | |
| 428 | mov_imm vmvn 0x00770000 .i32 | |
| 429 | mov_imm vmov 0x77000000 .i32 | |
| 430 | mov_imm vmvn 0x77000000 .i32 | |
| 431 | mov_imm vmov 0x0077 .i16 | |
| 432 | mov_imm vmvn 0x0077 .i16 | |
| 433 | mov_imm vmov 0x7700 .i16 | |
| 434 | mov_imm vmvn 0x7700 .i16 | |
| 435 | mov_imm vmov 0x000077ff .i32 | |
| 436 | mov_imm vmvn 0x000077ff .i32 | |
| 437 | mov_imm vmov 0x0077ffff .i32 | |
| 438 | mov_imm vmvn 0x0077ffff .i32 | |
| 439 | mov_imm vmov 0x77 .i8 | |
| 440 | mov_imm vmov 0xff0000ff000000ff .i64 | |
| 441 | mov_imm vmov 0x40880000 .f32 | |
| 442 | ||
| 443 | vmvn q0,q0 | |
| 444 | vmvnq q0,q0 | |
| 445 | vmvn d0,d0 | |
| 446 | ||
| 447 | .macro long_ops op | |
| 448 | regl3_1 \op d0 .s8 | |
| 449 | regl3_1 \op d0 .s16 | |
| 450 | regl3_1 \op d0 .s32 | |
| 451 | regl3_1 \op d0 .u8 | |
| 452 | regl3_1 \op d0 .u16 | |
| 453 | regl3_1 \op d0 .u32 | |
| 454 | .endm | |
| 455 | ||
| 456 | long_ops vabal | |
| 457 | long_ops vabdl | |
| 458 | long_ops vaddl | |
| 459 | long_ops vsubl | |
| 460 | ||
| 461 | .macro long_mac op | |
| 462 | regl3_1 \op d0 .s8 | |
| 463 | regl3_1 \op d0 .s16 | |
| 464 | regl3_1 \op d0 .s32 | |
| 465 | regl3_1 \op d0 .u8 | |
| 466 | regl3_1 \op d0 .u16 | |
| 467 | regl3_1 \op d0 .u32 | |
| 468 | regl3_1 \op "d0[0]" .s16 | |
| 469 | regl3_1 \op "d0[0]" .s32 | |
| 470 | regl3_1 \op "d0[0]" .u16 | |
| 471 | regl3_1 \op "d0[0]" .u32 | |
| 472 | .endm | |
| 473 | ||
| 474 | long_mac vmlal | |
| 475 | long_mac vmlsl | |
| 476 | ||
| 477 | .macro wide_ops op | |
| 478 | regw3_1 \op d0 .s8 | |
| 479 | regw3_1 \op d0 .s16 | |
| 480 | regw3_1 \op d0 .s32 | |
| 481 | regw3_1 \op d0 .u8 | |
| 482 | regw3_1 \op d0 .u16 | |
| 483 | regw3_1 \op d0 .u32 | |
| 484 | .endm | |
| 485 | ||
| 486 | wide_ops vaddw | |
| 487 | wide_ops vsubw | |
| 488 | ||
| 489 | .macro narr_ops op | |
| 490 | regn3_1 \op q0 .i16 | |
| 491 | regn3_1 \op q0 .i32 | |
| 428e3f1f PB |
492 | regn3_1 \op q0 .s32 |
| 493 | regn3_1 \op q0 .u32 | |
| edd40341 JB |
494 | regn3_1 \op q0 .i64 |
| 495 | .endm | |
| 496 | ||
| 497 | narr_ops vaddhn | |
| 498 | narr_ops vraddhn | |
| 499 | narr_ops vsubhn | |
| 500 | narr_ops vrsubhn | |
| 501 | ||
| 502 | .macro long_dmac op | |
| 503 | regl3_1 \op d0 .s16 | |
| 504 | regl3_1 \op d0 .s32 | |
| 505 | regl3_1 \op "d0[0]" .s16 | |
| 506 | regl3_1 \op "d0[0]" .s32 | |
| 507 | .endm | |
| 508 | ||
| 509 | long_dmac vqdmlal | |
| 510 | long_dmac vqdmlsl | |
| 511 | long_dmac vqdmull | |
| 512 | ||
| 513 | regl3_1 vmull d0 .s8 | |
| 514 | regl3_1 vmull d0 .s16 | |
| 515 | regl3_1 vmull d0 .s32 | |
| 516 | regl3_1 vmull d0 .u8 | |
| 517 | regl3_1 vmull d0 .u16 | |
| 518 | regl3_1 vmull d0 .u32 | |
| 519 | regl3_1 vmull d0 .p8 | |
| 520 | regl3_1 vmull "d0[0]" .s16 | |
| 521 | regl3_1 vmull "d0[0]" .s32 | |
| 522 | regl3_1 vmull "d0[0]" .u16 | |
| 523 | regl3_1 vmull "d0[0]" .u32 | |
| 524 | ||
| 525 | vext.8 q0,q0,q0,0 | |
| 526 | vextq.8 q0,q0,q0,0 | |
| 527 | vext.8 d0,d0,d0,0 | |
| 528 | ||
| 529 | .macro revs op opq vtype | |
| 530 | \op\vtype q0,q0 | |
| 531 | \opq\vtype q0,q0 | |
| 532 | \op\vtype d0,d0 | |
| 533 | .endm | |
| 534 | ||
| 535 | revs vrev64 vrev64q .8 | |
| 536 | revs vrev64 vrev64q .16 | |
| 537 | revs vrev64 vrev64q .32 | |
| 538 | revs vrev32 vrev32q .8 | |
| 539 | revs vrev32 vrev32q .16 | |
| 540 | revs vrev16 vrev16q .8 | |
| 541 | ||
| 542 | .macro dups op opq vtype | |
| 543 | \op\vtype q0,r0 | |
| 544 | \opq\vtype q0,r0 | |
| 545 | \op\vtype d0,r0 | |
| 546 | \op\vtype q0,d0[0] | |
| 547 | \opq\vtype q0,d0[0] | |
| 548 | \op\vtype d0,d0[0] | |
| 549 | .endm | |
| 550 | ||
| 551 | dups vdup vdupq .8 | |
| 552 | dups vdup vdupq .16 | |
| 553 | dups vdup vdupq .32 | |
| 554 | ||
| 555 | .macro binop_3typ op op1 op2 t1 t2 t3 | |
| 556 | \op\t1 \op1,\op2 | |
| 557 | \op\t2 \op1,\op2 | |
| 558 | \op\t3 \op1,\op2 | |
| 559 | .endm | |
| 560 | ||
| 561 | binop_3typ vmovl q0 d0 .s8 .s16 .s32 | |
| 562 | binop_3typ vmovl q0 d0 .u8 .u16 .u32 | |
| 563 | binop_3typ vmovn d0 q0 .i16 .i32 .i64 | |
| 428e3f1f PB |
564 | vmovn.s32 d0, q0 |
| 565 | vmovn.u32 d0, q0 | |
| edd40341 JB |
566 | binop_3typ vqmovn d0 q0 .s16 .s32 .s64 |
| 567 | binop_3typ vqmovn d0 q0 .u16 .u32 .u64 | |
| 568 | binop_3typ vqmovun d0 q0 .s16 .s32 .s64 | |
| 569 | ||
| 570 | .macro binops op opq vtype="" rhs="0" | |
| 571 | \op\vtype q0,q\rhs | |
| 572 | \opq\vtype q0,q\rhs | |
| 573 | \op\vtype d0,d\rhs | |
| 574 | .endm | |
| 575 | ||
| 576 | .macro regs2_sz_32 op opq | |
| 577 | binops \op \opq .8 1 | |
| 578 | binops \op \opq .16 1 | |
| 579 | binops \op \opq .32 1 | |
| 580 | .endm | |
| 581 | ||
| 582 | regs2_sz_32 vzip vzipq | |
| 583 | regs2_sz_32 vuzp vuzpq | |
| 584 | ||
| 585 | .macro regs2_s_32 op opq | |
| 586 | binops \op \opq .s8 | |
| 587 | binops \op \opq .s16 | |
| 588 | binops \op \opq .s32 | |
| 589 | .endm | |
| 590 | ||
| 591 | regs2_s_32 vqabs vqabsq | |
| 592 | regs2_s_32 vqneg vqnegq | |
| 593 | ||
| 594 | .macro regs2_su_32 op opq | |
| 595 | regs2_s_32 \op \opq | |
| 596 | binops \op \opq .u8 | |
| 597 | binops \op \opq .u16 | |
| 598 | binops \op \opq .u32 | |
| 599 | .endm | |
| 600 | ||
| 601 | regs2_su_32 vpadal vpadalq | |
| 602 | regs2_su_32 vpaddl vpaddlq | |
| 603 | ||
| 604 | binops vrecpe vrecpeq .u32 | |
| 605 | binops vrecpe vrecpeq .f32 | |
| 606 | binops vrsqrte vrsqrteq .u32 | |
| 607 | binops vrsqrte vrsqrteq .f32 | |
| 608 | ||
| 609 | regs2_s_32 vcls vclsq | |
| 610 | ||
| 611 | .macro regs2_i_32 op opq | |
| 612 | binops \op \opq .i8 | |
| 613 | binops \op \opq .i16 | |
| 614 | binops \op \opq .i32 | |
| 428e3f1f PB |
615 | binops \op \opq .s32 |
| 616 | binops \op \opq .u32 | |
| edd40341 JB |
617 | .endm |
| 618 | ||
| 619 | regs2_i_32 vclz vclzq | |
| 620 | ||
| 621 | binops vcnt vcntq .8 | |
| 622 | ||
| 623 | binops vswp vswpq "" 1 | |
| 624 | ||
| 625 | regs2_sz_32 vtrn vtrnq | |
| 626 | ||
| 627 | vtbl.8 d0,{d0},d0 | |
| 628 | vtbx.8 d0,{d0},d0 | |
| 629 |