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539d4391 NC |
1 | .arch armv7-r |
2 | .syntax unified | |
3 | .text | |
4 | .thumb | |
5 | .global foo | |
6 | foo: | |
7 | @ Section A6.1.3 "Use of 0b1101 as a register specifier". | |
8 | ||
9 | @ R13 as the source or destination register of a mov instruction. | |
10 | @ only register to register transfers without shifts are supported, | |
11 | @ with no flag setting | |
12 | ||
13 | mov sp,r0 | |
14 | mov r0,sp | |
15 | ||
16 | @ Using the following instructions to adjust r13 up or down by a | |
17 | @ multiple of 4: | |
18 | ||
19 | add sp,sp,#0 | |
20 | addw sp,sp,#0 | |
21 | sub sp,sp,#0 | |
22 | subw sp,sp,#0 | |
23 | add sp,sp,r0 | |
24 | add sp,sp,r0,lsl #1 | |
25 | sub sp,sp,r0 | |
26 | sub sp,sp,r0,lsl #1 | |
27 | ||
28 | @ R13 as a base register <Rn> of any load/store instruction. | |
29 | ||
30 | ldr r0, [sp] | |
31 | ldr r0, [pc] | |
32 | ldr pc, [r0] | |
33 | ldr sp, [r0] | |
34 | ldr pc, [pc] | |
35 | ldr sp, [sp] | |
36 | ldr pc, [sp] | |
37 | ldr sp, [pc] | |
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38 | |
39 | str r0, [sp] | |
539d4391 | 40 | str sp, [r0] |
539d4391 | 41 | str sp, [sp] |
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42 | |
43 | @ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction. | |
44 | ||
45 | add r0, sp, r0 | |
46 | adds r0, sp, r0 | |
47 | add r0, sp, r0, lsl #1 | |
48 | adds r0, sp, r0, lsl #1 | |
49 | ||
50 | cmn sp, #0 | |
51 | cmn sp, r0 | |
52 | cmn sp, r0, lsl #1 | |
53 | cmp sp, #0 | |
54 | cmp sp, r0 | |
55 | cmp sp, r0, lsl #1 | |
56 | ||
57 | sub sp, #0 | |
58 | subs sp, #0 | |
59 | sub r0, sp, #0 | |
60 | subs r0, sp, #0 | |
61 | ||
62 | @ ADD (sp plus immediate). | |
63 | ||
64 | add sp, #4 | |
65 | add r0, sp, #4 | |
66 | adds sp, #4 | |
67 | adds r0, sp, #4 | |
68 | addw r0, sp, #4 | |
69 | ||
70 | add sp, sp, #4 | |
71 | adds sp, sp, #4 | |
72 | addw sp, sp, #4 | |
73 | ||
74 | @ ADD (sp plus register). | |
75 | ||
76 | add sp, r0 | |
77 | add r0, sp, r0 | |
78 | add r0, sp, r0, lsl #1 | |
79 | adds sp, r0 | |
80 | adds r0, sp, r0 | |
81 | adds r0, sp, r0, lsl #1 | |
82 | ||
83 | add sp, sp, r0 | |
84 | add sp, sp, r0, lsl #1 | |
85 | adds sp, sp, r0 | |
86 | adds sp, sp, r0, lsl #1 | |
87 | ||
88 | add sp, sp, sp | |
89 | ||
90 | @ SUB (sp minus immediate). | |
91 | ||
92 | sub r0, sp , #0 | |
93 | subs r0, sp , #0 | |
94 | subw r0, sp , #0 | |
95 | ||
96 | sub sp, sp , #0 | |
97 | subs sp, sp , #0 | |
98 | subw sp, sp , #0 | |
99 | ||
100 | @ SUB (sp minus register). | |
101 | ||
102 | sub sp, #0 | |
103 | subs sp, #0 | |
104 | sub r0, sp, r0, lsl #1 | |
105 | subs r0, sp, r0, lsl #1 | |
106 | ||
107 | sub sp, sp, r0, lsl #1 | |
108 | subs sp, sp, r0, lsl #1 | |
109 | ||
110 | @ PC-related insns (equivalent to adr). | |
111 | ||
112 | add r0, pc, #4 | |
113 | sub r0, pc, #4 | |
114 | adds r0, pc, #4 | |
115 | subs r0, pc, #4 | |
116 | addw r0, pc, #4 | |
117 | subw r0, pc, #4 | |
118 | ||
119 | @ nops to pad the section out to an alignment boundary. | |
120 | ||
121 | nop | |
122 | nop | |
123 | nop |