projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 539d4391 NC |
1 | .arch armv7-r |
| 2 | .syntax unified | |
| 3 | .text | |
| 4 | .thumb | |
| 5 | .global foo | |
| 749479c8 AO |
6 | foo: |
| 7 | .align 4 | |
| 539d4391 NC |
8 | @ Section A6.1.3 "Use of 0b1101 as a register specifier". |
| 9 | ||
| 10 | @ R13 as the source or destination register of a mov instruction. | |
| 11 | @ only register to register transfers without shifts are supported, | |
| 12 | @ with no flag setting | |
| 13 | ||
| 14 | mov sp,r0 | |
| 15 | mov r0,sp | |
| 16 | ||
| 17 | @ Using the following instructions to adjust r13 up or down by a | |
| 18 | @ multiple of 4: | |
| 19 | ||
| 20 | add sp,sp,#0 | |
| 21 | addw sp,sp,#0 | |
| 22 | sub sp,sp,#0 | |
| 23 | subw sp,sp,#0 | |
| 24 | add sp,sp,r0 | |
| 25 | add sp,sp,r0,lsl #1 | |
| 26 | sub sp,sp,r0 | |
| 27 | sub sp,sp,r0,lsl #1 | |
| 28 | ||
| 29 | @ R13 as a base register <Rn> of any load/store instruction. | |
| 30 | ||
| 31 | ldr r0, [sp] | |
| 32 | ldr r0, [pc] | |
| 33 | ldr pc, [r0] | |
| 34 | ldr sp, [r0] | |
| 35 | ldr pc, [pc] | |
| 36 | ldr sp, [sp] | |
| 37 | ldr pc, [sp] | |
| 38 | ldr sp, [pc] | |
| 539d4391 NC |
39 | |
| 40 | str r0, [sp] | |
| 539d4391 | 41 | str sp, [r0] |
| 539d4391 | 42 | str sp, [sp] |
| 539d4391 NC |
43 | |
| 44 | @ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction. | |
| 45 | ||
| 46 | add r0, sp, r0 | |
| 47 | adds r0, sp, r0 | |
| 48 | add r0, sp, r0, lsl #1 | |
| 49 | adds r0, sp, r0, lsl #1 | |
| 50 | ||
| 51 | cmn sp, #0 | |
| 52 | cmn sp, r0 | |
| 53 | cmn sp, r0, lsl #1 | |
| 54 | cmp sp, #0 | |
| 55 | cmp sp, r0 | |
| 56 | cmp sp, r0, lsl #1 | |
| 57 | ||
| 58 | sub sp, #0 | |
| 59 | subs sp, #0 | |
| 60 | sub r0, sp, #0 | |
| 61 | subs r0, sp, #0 | |
| 62 | ||
| 63 | @ ADD (sp plus immediate). | |
| 64 | ||
| 65 | add sp, #4 | |
| 66 | add r0, sp, #4 | |
| 67 | adds sp, #4 | |
| 68 | adds r0, sp, #4 | |
| 69 | addw r0, sp, #4 | |
| 70 | ||
| 71 | add sp, sp, #4 | |
| 72 | adds sp, sp, #4 | |
| 73 | addw sp, sp, #4 | |
| 74 | ||
| 75 | @ ADD (sp plus register). | |
| 76 | ||
| 77 | add sp, r0 | |
| 78 | add r0, sp, r0 | |
| 79 | add r0, sp, r0, lsl #1 | |
| 80 | adds sp, r0 | |
| 81 | adds r0, sp, r0 | |
| 82 | adds r0, sp, r0, lsl #1 | |
| 83 | ||
| 84 | add sp, sp, r0 | |
| 85 | add sp, sp, r0, lsl #1 | |
| 86 | adds sp, sp, r0 | |
| 87 | adds sp, sp, r0, lsl #1 | |
| 88 | ||
| 89 | add sp, sp, sp | |
| 90 | ||
| 91 | @ SUB (sp minus immediate). | |
| 92 | ||
| 93 | sub r0, sp , #0 | |
| 94 | subs r0, sp , #0 | |
| 95 | subw r0, sp , #0 | |
| 96 | ||
| 97 | sub sp, sp , #0 | |
| 98 | subs sp, sp , #0 | |
| 99 | subw sp, sp , #0 | |
| 100 | ||
| 101 | @ SUB (sp minus register). | |
| 102 | ||
| 103 | sub sp, #0 | |
| 104 | subs sp, #0 | |
| 105 | sub r0, sp, r0, lsl #1 | |
| 106 | subs r0, sp, r0, lsl #1 | |
| 107 | ||
| 108 | sub sp, sp, r0, lsl #1 | |
| 109 | subs sp, sp, r0, lsl #1 | |
| 110 | ||
| 111 | @ PC-related insns (equivalent to adr). | |
| 112 | ||
| 113 | add r0, pc, #4 | |
| 114 | sub r0, pc, #4 | |
| 115 | adds r0, pc, #4 | |
| 116 | subs r0, pc, #4 | |
| 117 | addw r0, pc, #4 | |
| 118 | subw r0, pc, #4 | |
| 119 | ||
| 120 | @ nops to pad the section out to an alignment boundary. | |
| 121 | ||
| 122 | nop | |
| 123 | nop | |
| 124 | nop |