Commit | Line | Data |
---|---|---|
539d4391 NC |
1 | .arch armv7-r |
2 | .syntax unified | |
3 | .text | |
4 | .thumb | |
5 | .global foo | |
6 | foo: | |
7 | @ Section A6.1.3 "Use of 0b1101 as a register specifier". | |
8 | ||
9 | @ R13 as the source or destination register of a mov instruction. | |
10 | @ only register to register transfers without shifts are supported, | |
11 | @ with no flag setting | |
12 | ||
13 | mov sp,r0 | |
14 | mov r0,sp | |
15 | ||
16 | @ Using the following instructions to adjust r13 up or down by a | |
17 | @ multiple of 4: | |
18 | ||
19 | add sp,sp,#0 | |
20 | addw sp,sp,#0 | |
21 | sub sp,sp,#0 | |
22 | subw sp,sp,#0 | |
23 | add sp,sp,r0 | |
24 | add sp,sp,r0,lsl #1 | |
25 | sub sp,sp,r0 | |
26 | sub sp,sp,r0,lsl #1 | |
27 | ||
28 | @ R13 as a base register <Rn> of any load/store instruction. | |
29 | ||
30 | ldr r0, [sp] | |
31 | ldr r0, [pc] | |
32 | ldr pc, [r0] | |
33 | ldr sp, [r0] | |
34 | ldr pc, [pc] | |
35 | ldr sp, [sp] | |
36 | ldr pc, [sp] | |
37 | ldr sp, [pc] | |
38 | ldr sp, [r0, +pc] | |
39 | ||
40 | str r0, [sp] | |
41 | str r0, [pc] | |
42 | str pc, [r0] | |
43 | str sp, [r0] | |
44 | str pc, [pc] | |
45 | str sp, [sp] | |
46 | str pc, [sp] | |
47 | str sp, [pc] | |
48 | str sp, [r0, +pc] | |
49 | ||
50 | @ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction. | |
51 | ||
52 | add r0, sp, r0 | |
53 | adds r0, sp, r0 | |
54 | add r0, sp, r0, lsl #1 | |
55 | adds r0, sp, r0, lsl #1 | |
56 | ||
57 | cmn sp, #0 | |
58 | cmn sp, r0 | |
59 | cmn sp, r0, lsl #1 | |
60 | cmp sp, #0 | |
61 | cmp sp, r0 | |
62 | cmp sp, r0, lsl #1 | |
63 | ||
64 | sub sp, #0 | |
65 | subs sp, #0 | |
66 | sub r0, sp, #0 | |
67 | subs r0, sp, #0 | |
68 | ||
69 | @ ADD (sp plus immediate). | |
70 | ||
71 | add sp, #4 | |
72 | add r0, sp, #4 | |
73 | adds sp, #4 | |
74 | adds r0, sp, #4 | |
75 | addw r0, sp, #4 | |
76 | ||
77 | add sp, sp, #4 | |
78 | adds sp, sp, #4 | |
79 | addw sp, sp, #4 | |
80 | ||
81 | @ ADD (sp plus register). | |
82 | ||
83 | add sp, r0 | |
84 | add r0, sp, r0 | |
85 | add r0, sp, r0, lsl #1 | |
86 | adds sp, r0 | |
87 | adds r0, sp, r0 | |
88 | adds r0, sp, r0, lsl #1 | |
89 | ||
90 | add sp, sp, r0 | |
91 | add sp, sp, r0, lsl #1 | |
92 | adds sp, sp, r0 | |
93 | adds sp, sp, r0, lsl #1 | |
94 | ||
95 | add sp, sp, sp | |
96 | ||
97 | @ SUB (sp minus immediate). | |
98 | ||
99 | sub r0, sp , #0 | |
100 | subs r0, sp , #0 | |
101 | subw r0, sp , #0 | |
102 | ||
103 | sub sp, sp , #0 | |
104 | subs sp, sp , #0 | |
105 | subw sp, sp , #0 | |
106 | ||
107 | @ SUB (sp minus register). | |
108 | ||
109 | sub sp, #0 | |
110 | subs sp, #0 | |
111 | sub r0, sp, r0, lsl #1 | |
112 | subs r0, sp, r0, lsl #1 | |
113 | ||
114 | sub sp, sp, r0, lsl #1 | |
115 | subs sp, sp, r0, lsl #1 | |
116 | ||
117 | @ PC-related insns (equivalent to adr). | |
118 | ||
119 | add r0, pc, #4 | |
120 | sub r0, pc, #4 | |
121 | adds r0, pc, #4 | |
122 | subs r0, pc, #4 | |
123 | addw r0, pc, #4 | |
124 | subw r0, pc, #4 | |
125 | ||
126 | @ nops to pad the section out to an alignment boundary. | |
127 | ||
128 | nop | |
129 | nop | |
130 | nop |