Commit | Line | Data |
---|---|---|
8335d6aa JW |
1 | .text |
2 | .fpu neon | |
3 | .thumb | |
4 | .syntax unified | |
5 | .thumb_func | |
6 | thumb2_ldr: | |
7 | .macro vlxr regtype const | |
8 | .irp regindex, 0, 14, 28, 31 | |
9 | vldr \regtype\regindex, \const | |
10 | .endr | |
11 | .endm | |
12 | # Thumb-2 support vldr literal pool also. | |
13 | vlxr s "=0" | |
14 | vlxr s "=0xff000000" | |
15 | vlxr s "=-1" | |
16 | vlxr s "=0x0fff0000" | |
17 | .pool | |
18 | ||
19 | vlxr s "=0" | |
20 | vlxr s "=0x00ff0000" | |
21 | vlxr s "=0xff00ffff" | |
22 | vlxr s "=0x00fff000" | |
23 | .pool | |
24 | ||
25 | vlxr d "=0" | |
26 | vlxr d "=0xca000000" | |
27 | vlxr d "=-1" | |
28 | vlxr d "=0x0fff0000" | |
29 | .pool | |
30 | ||
31 | vlxr d "=0" | |
32 | vlxr d "=0x00ff0000" | |
33 | vlxr d "=0xff0000ff" | |
34 | vlxr d "=0x00fff000" | |
35 | .pool | |
36 | ||
37 | vlxr d "=0" | |
38 | vlxr d "=0xff00000000000000" | |
39 | vlxr d "=-1" | |
40 | vlxr d "=0x0fff000000000000" | |
41 | .pool | |
42 | ||
43 | vlxr d "=0" | |
44 | vlxr d "=0x00ff00000000000" | |
45 | vlxr d "=0xff00ffff0000000" | |
46 | vlxr d "=0xff00ffff0000000" | |
47 | .pool | |
48 | ||
49 | # pool should be aligned to 8-byte. | |
50 | .p2align 3 | |
51 | vldr d1, =0x0000fff000000000 | |
52 | .pool | |
53 | ||
54 | # no error when code is align already. | |
55 | .p2align 3 | |
56 | add r0, r1, #0 | |
57 | vldr d1, =0x0000fff000000000 | |
58 | .pool | |
59 | ||
60 | .p2align 3 | |
61 | vldr d1, =0x0000fff000000000 | |
62 | vldr s2, =0xff000000 | |
63 | # padding A | |
64 | vldr d3, =0x0000fff000000001 | |
65 | # reuse padding slot A | |
66 | vldr s4, =0xff000001 | |
67 | # reuse d3 | |
68 | vldr d5, =0x0000fff000000001 | |
69 | # new 8-byte entry | |
70 | vldr d6, =0x0000fff000000002 | |
71 | # new 8-byte entry | |
72 | vldr d7, =0x0000fff000000003 | |
73 | # new 4-byte entry | |
74 | vldr s8, =0xff000002 | |
75 | # padding B | |
76 | vldr d9, =0x0000fff000000004 | |
77 | # reuse padding slot B | |
78 | vldr s10, =0xff000003 | |
79 | # new 8-byte entry | |
80 | vldr d11, =0x0000fff000000005 | |
81 | # new 4 entry | |
82 | vldr s12, =0xff000004 | |
83 | # new 4 entry | |
84 | vldr s13, =0xff000005 | |
85 | # reuse value of s4 in pool | |
86 | vldr s14, =0xff000001 | |
87 | # reuse high part of d1 in pool | |
88 | vldr s15, =0x0000fff0 | |
89 | # 8-byte entry reuse two 4-byte entries. | |
90 | # d16 reuse s12, s13 | |
91 | vldr d16, =0xff000005ff000004 | |
92 | # d17 should not reuse high part of d11 and s12. | |
93 | # because the it's align 8-byte aligned. | |
94 | vldr d17, =0xff0000040000fff0 | |
95 | .pool |