Commit | Line | Data |
---|---|---|
8f06b2d8 PB |
1 | @ VFP Instructions for v1xD variants (Single precision only) |
2 | @ Same as vfp1xD.s, but for Thumb-2 | |
3 | .syntax unified | |
4 | .thumb | |
5 | .text | |
6 | .global F | |
7 | F: | |
8 | @ First we test the basic syntax and bit patterns of the opcodes. | |
9 | @ Most of these tests deliberatly use s0/r0 to avoid setting | |
10 | @ any more bits than necessary. | |
11 | ||
12 | @ Comparison operations | |
13 | ||
14 | fmstat | |
15 | ||
16 | fcmpes s0, s0 | |
17 | fcmpezs s0 | |
18 | fcmps s0, s0 | |
19 | fcmpzs s0 | |
20 | ||
21 | @ Monadic data operations | |
22 | ||
23 | fabss s0, s0 | |
24 | fcpys s0, s0 | |
25 | fnegs s0, s0 | |
26 | fsqrts s0, s0 | |
27 | ||
28 | @ Dyadic data operations | |
29 | ||
30 | fadds s0, s0, s0 | |
31 | fdivs s0, s0, s0 | |
32 | fmacs s0, s0, s0 | |
33 | fmscs s0, s0, s0 | |
34 | fmuls s0, s0, s0 | |
35 | fnmacs s0, s0, s0 | |
36 | fnmscs s0, s0, s0 | |
37 | fnmuls s0, s0, s0 | |
38 | fsubs s0, s0, s0 | |
39 | ||
40 | @ Load/store operations | |
41 | ||
42 | flds s0, [r0] | |
43 | fsts s0, [r0] | |
44 | ||
45 | @ Load/store multiple operations | |
46 | ||
47 | fldmias r0, {s0} | |
48 | fldmfds r0, {s0} | |
49 | fldmias r0!, {s0} | |
50 | fldmfds r0!, {s0} | |
51 | fldmdbs r0!, {s0} | |
52 | fldmeas r0!, {s0} | |
53 | ||
54 | fldmiax r0, {d0} | |
55 | fldmfdx r0, {d0} | |
56 | fldmiax r0!, {d0} | |
57 | fldmfdx r0!, {d0} | |
58 | fldmdbx r0!, {d0} | |
59 | fldmeax r0!, {d0} | |
60 | ||
61 | fstmias r0, {s0} | |
62 | fstmeas r0, {s0} | |
63 | fstmias r0!, {s0} | |
64 | fstmeas r0!, {s0} | |
65 | fstmdbs r0!, {s0} | |
66 | fstmfds r0!, {s0} | |
67 | ||
68 | fstmiax r0, {d0} | |
69 | fstmeax r0, {d0} | |
70 | fstmiax r0!, {d0} | |
71 | fstmeax r0!, {d0} | |
72 | fstmdbx r0!, {d0} | |
73 | fstmfdx r0!, {d0} | |
74 | ||
75 | @ Conversion operations | |
76 | ||
77 | fsitos s0, s0 | |
78 | fuitos s0, s0 | |
79 | ||
80 | ftosis s0, s0 | |
81 | ftosizs s0, s0 | |
82 | ftouis s0, s0 | |
83 | ftouizs s0, s0 | |
84 | ||
85 | @ ARM from VFP operations | |
86 | ||
87 | fmrs r0, s0 | |
88 | fmrx r0, fpsid | |
89 | fmrx r0, fpscr | |
90 | fmrx r0, fpexc | |
91 | ||
92 | @ VFP From ARM operations | |
93 | ||
94 | fmsr s0, r0 | |
95 | fmxr fpsid, r0 | |
96 | fmxr fpscr, r0 | |
97 | fmxr fpexc, r0 | |
98 | ||
99 | @ Now we test that the register fields are updated correctly for | |
100 | @ each class of instruction. | |
101 | ||
102 | @ Single register operations (compare-zero): | |
103 | ||
104 | fcmpzs s1 | |
105 | fcmpzs s2 | |
106 | fcmpzs s31 | |
107 | ||
108 | @ Two register comparison operations: | |
109 | ||
110 | fcmps s0, s1 | |
111 | fcmps s0, s2 | |
112 | fcmps s0, s31 | |
113 | fcmps s1, s0 | |
114 | fcmps s2, s0 | |
115 | fcmps s31, s0 | |
116 | fcmps s21, s12 | |
117 | ||
118 | @ Two register data operations (monadic) | |
119 | ||
120 | fnegs s0, s1 | |
121 | fnegs s0, s2 | |
122 | fnegs s0, s31 | |
123 | fnegs s1, s0 | |
124 | fnegs s2, s0 | |
125 | fnegs s31, s0 | |
126 | fnegs s12, s21 | |
127 | ||
128 | @ Three register data operations (dyadic) | |
129 | ||
130 | fadds s0, s0, s1 | |
131 | fadds s0, s0, s2 | |
132 | fadds s0, s0, s31 | |
133 | fadds s0, s1, s0 | |
134 | fadds s0, s2, s0 | |
135 | fadds s0, s31, s0 | |
136 | fadds s1, s0, s0 | |
137 | fadds s2, s0, s0 | |
138 | fadds s31, s0, s0 | |
139 | fadds s12, s21, s5 | |
140 | ||
141 | @ Conversion operations | |
142 | ||
143 | fsitos s0, s1 | |
144 | fsitos s0, s2 | |
145 | fsitos s0, s31 | |
146 | fsitos s1, s0 | |
147 | fsitos s2, s0 | |
148 | fsitos s31, s0 | |
149 | ||
150 | ftosis s0, s1 | |
151 | ftosis s0, s2 | |
152 | ftosis s0, s31 | |
153 | ftosis s1, s0 | |
154 | ftosis s2, s0 | |
155 | ftosis s31, s0 | |
156 | ||
157 | @ Move to VFP from ARM | |
158 | ||
159 | fmsr s0, r1 | |
160 | fmsr s0, r7 | |
161 | fmsr s0, r14 | |
162 | fmsr s1, r0 | |
163 | fmsr s2, r0 | |
164 | fmsr s31, r0 | |
165 | fmsr s21, r7 | |
166 | ||
167 | fmxr fpsid, r1 | |
168 | fmxr fpsid, r14 | |
169 | ||
170 | @ Move to ARM from VFP | |
171 | ||
172 | fmrs r0, s1 | |
173 | fmrs r0, s2 | |
174 | fmrs r0, s31 | |
175 | fmrs r1, s0 | |
176 | fmrs r7, s0 | |
177 | fmrs r14, s0 | |
178 | fmrs r9, s11 | |
179 | ||
180 | fmrx r1, fpsid | |
181 | fmrx r14, fpsid | |
182 | ||
183 | @ Load/store operations | |
184 | ||
185 | flds s0, [r1] | |
186 | flds s0, [r14] | |
187 | flds s0, [r0, #0] | |
188 | flds s0, [r0, #1020] | |
189 | flds s0, [r0, #-1020] | |
190 | flds s1, [r0] | |
191 | flds s2, [r0] | |
192 | flds s31, [r0] | |
193 | fsts s21, [r12, #804] | |
194 | ||
195 | @ Load/store multiple operations | |
196 | ||
197 | fldmias r0, {s1} | |
198 | fldmias r0, {s2} | |
199 | fldmias r0, {s31} | |
200 | fldmias r0, {s0-s1} | |
201 | fldmias r0, {s0-s2} | |
202 | fldmias r0, {s0-s31} | |
203 | fldmias r0, {s1-s31} | |
204 | fldmias r0, {s2-s31} | |
205 | fldmias r0, {s30-s31} | |
206 | fldmias r1, {s0} | |
207 | fldmias r14, {s0} | |
208 | ||
209 | fstmiax r0, {d1} | |
210 | fstmiax r0, {d2} | |
211 | fstmiax r0, {d15} | |
212 | fstmiax r0, {d0-d1} | |
213 | fstmiax r0, {d0-d2} | |
214 | fstmiax r0, {d0-d15} | |
215 | fstmiax r0, {d1-d15} | |
216 | fstmiax r0, {d2-d15} | |
217 | fstmiax r0, {d14-d15} | |
218 | fstmiax r1, {d0} | |
219 | fstmiax r14, {d0} | |
220 | ||
221 | @ Check that we assemble all the register names correctly | |
222 | ||
223 | fcmpzs s0 | |
224 | fcmpzs s1 | |
225 | fcmpzs s2 | |
226 | fcmpzs s3 | |
227 | fcmpzs s4 | |
228 | fcmpzs s5 | |
229 | fcmpzs s6 | |
230 | fcmpzs s7 | |
231 | fcmpzs s8 | |
232 | fcmpzs s9 | |
233 | fcmpzs s10 | |
234 | fcmpzs s11 | |
235 | fcmpzs s12 | |
236 | fcmpzs s13 | |
237 | fcmpzs s14 | |
238 | fcmpzs s15 | |
239 | fcmpzs s16 | |
240 | fcmpzs s17 | |
241 | fcmpzs s18 | |
242 | fcmpzs s19 | |
243 | fcmpzs s20 | |
244 | fcmpzs s21 | |
245 | fcmpzs s22 | |
246 | fcmpzs s23 | |
247 | fcmpzs s24 | |
248 | fcmpzs s25 | |
249 | fcmpzs s26 | |
250 | fcmpzs s27 | |
251 | fcmpzs s28 | |
252 | fcmpzs s29 | |
253 | fcmpzs s30 | |
254 | fcmpzs s31 | |
255 | ||
256 | @ Now we check the placement of the conditional execution substring. | |
257 | @ On VFP this is always at the end of the instruction. | |
258 | @ We use different register numbers here to check for correct | |
259 | @ disassembly | |
260 | ||
261 | @ Comparison operations | |
262 | ||
263 | itttt eq | |
264 | fmstateq | |
265 | ||
266 | fcmpeseq s3, s7 | |
267 | fcmpezseq s5 | |
268 | fcmpseq s1, s2 | |
269 | itttt eq | |
270 | fcmpzseq s1 | |
271 | ||
272 | @ Monadic data operations | |
273 | ||
274 | fabsseq s1, s3 | |
275 | fcpyseq s31, s19 | |
276 | fnegseq s20, s8 | |
277 | itttt eq | |
278 | fsqrtseq s5, s7 | |
279 | ||
280 | @ Dyadic data operations | |
281 | ||
282 | faddseq s6, s5, s4 | |
283 | fdivseq s3, s2, s1 | |
284 | fmacseq s31, s30, s29 | |
285 | itttt eq | |
286 | fmscseq s28, s27, s26 | |
287 | fmulseq s25, s24, s23 | |
288 | fnmacseq s22, s21, s20 | |
289 | fnmscseq s19, s18, s17 | |
290 | itttt eq | |
291 | fnmulseq s16, s15, s14 | |
292 | fsubseq s13, s12, s11 | |
293 | ||
294 | @ Load/store operations | |
295 | ||
296 | fldseq s10, [r8] | |
297 | fstseq s9, [r7] | |
298 | ||
299 | @ Load/store multiple operations | |
300 | ||
301 | itttt eq | |
302 | fldmiaseq r1, {s8} | |
303 | fldmfdseq r2, {s7} | |
304 | fldmiaseq r3!, {s6} | |
305 | fldmfdseq r4!, {s5} | |
306 | itttt eq | |
307 | fldmdbseq r5!, {s4} | |
308 | fldmeaseq r6!, {s3} | |
309 | ||
310 | fldmiaxeq r7, {d1} | |
311 | fldmfdxeq r8, {d2} | |
312 | itttt eq | |
313 | fldmiaxeq r9!, {d3} | |
314 | fldmfdxeq r10!, {d4} | |
315 | fldmdbxeq r11!, {d5} | |
316 | fldmeaxeq r12!, {d6} | |
317 | ||
318 | itttt eq | |
319 | fstmiaseq r13, {s2} | |
320 | fstmeaseq r14, {s1} | |
321 | fstmiaseq r1!, {s31} | |
322 | fstmeaseq r2!, {s30} | |
323 | itttt eq | |
324 | fstmdbseq r3!, {s29} | |
325 | fstmfdseq r4!, {s28} | |
326 | ||
327 | fstmiaxeq r5, {d7} | |
328 | fstmeaxeq r6, {d8} | |
329 | itttt eq | |
330 | fstmiaxeq r7!, {d9} | |
331 | fstmeaxeq r8!, {d10} | |
332 | fstmdbxeq r9!, {d11} | |
333 | fstmfdxeq r10!, {d12} | |
334 | ||
335 | @ Conversion operations | |
336 | ||
337 | itttt eq | |
338 | fsitoseq s27, s6 | |
339 | ftosiseq s25, s5 | |
340 | ftosizseq s23, s4 | |
341 | ftouiseq s21, s3 | |
342 | itttt eq | |
343 | ftouizseq s19, s2 | |
344 | fuitoseq s17, s1 | |
345 | ||
346 | @ ARM from VFP operations | |
347 | ||
348 | fmrseq r11, s3 | |
349 | fmrxeq r9, fpsid | |
350 | ||
351 | @ VFP From ARM operations | |
352 | ||
353 | itt eq | |
354 | fmsreq s3, r9 | |
355 | fmxreq fpsid, r8 | |
356 | ||
cd2cf30b PB |
357 | @ Implementation specific system registers |
358 | fmrx r0, fpinst | |
359 | fmrx r0, fpinst2 | |
360 | fmrx r0, mvfr0 | |
361 | fmrx r0, mvfr1 | |
362 | fmrx r0, c12 | |
363 | fmxr fpinst, r0 | |
364 | fmxr fpinst2, r0 | |
365 | fmxr mvfr0, r0 | |
366 | fmxr mvfr1, r0 | |
367 | fmxr c12, r0 | |
368 | ||
369 | nop | |
370 | nop | |
371 | nop | |
372 | nop | |
8f06b2d8 PB |
373 | nop |
374 | nop |