Commit | Line | Data |
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8df55cb8 CM |
1 | \r |
2 | .EXTERN MY_LABEL2;\r | |
3 | .section .text;\r | |
4 | \r | |
5 | //\r | |
6 | //4 MOVE\r | |
7 | //\r | |
8 | \r | |
9 | //genreg = genreg ; /* (a) */\r | |
10 | R0 = R0;\r | |
11 | R1 = R1;\r | |
12 | R2 = R2;\r | |
13 | R3 = R3;\r | |
14 | R4 = R4;\r | |
15 | R5 = R5;\r | |
16 | R6 = R6;\r | |
17 | R7 = R7;\r | |
18 | \r | |
19 | P0 = P0;\r | |
20 | P1 = P1;\r | |
21 | P2 = P2;\r | |
22 | P3 = P3;\r | |
23 | P4 = P4;\r | |
24 | P5 = P5;\r | |
25 | SP = SP;\r | |
26 | FP = FP;\r | |
27 | \r | |
28 | A0.X = A0.X;\r | |
29 | A0.W = A0.W;\r | |
30 | A1.X = A1.X;\r | |
31 | A1.W = A1.W;\r | |
32 | \r | |
33 | \r | |
34 | R0 = A1.W;\r | |
35 | R1 = A1.X;\r | |
36 | R2 = A0.W;\r | |
37 | R3 = A0.X;\r | |
38 | R4 = FP;\r | |
39 | R5 = SP;\r | |
40 | R6 = P5;\r | |
41 | R7 = P4;\r | |
42 | \r | |
43 | P0 = P3;\r | |
44 | P1 = P2;\r | |
45 | P2 = P1;\r | |
46 | P3 = P0;\r | |
47 | P4 = R7;\r | |
48 | P5 = R6;\r | |
49 | SP = R5;\r | |
50 | FP = R4;\r | |
51 | \r | |
52 | A0.X = R3;\r | |
53 | A0.W = R2;\r | |
54 | A1.X = R1;\r | |
55 | A1.W = R0;\r | |
56 | \r | |
57 | A0.X = A0.W;\r | |
58 | A0.X = A1.W;\r | |
59 | A0.X = A1.X;\r | |
60 | \r | |
61 | A1.X = A1.W;\r | |
62 | A1.X = A0.W;\r | |
63 | A1.X = A0.X;\r | |
64 | \r | |
65 | A0.W = A0.W;\r | |
66 | A0.W = A1.W;\r | |
67 | A0.W = A1.X;\r | |
68 | \r | |
69 | A1.W = A1.W;\r | |
70 | A1.W = A0.W;\r | |
71 | A1.W = A0.X;\r | |
72 | \r | |
73 | //genreg = dagreg ; /* (a) */\r | |
74 | R0 = I0;\r | |
75 | R1 = I1;\r | |
76 | R2 = I2;\r | |
77 | R3 = I3;\r | |
78 | R4 = M0;\r | |
79 | R5 = M1;\r | |
80 | R6 = M2;\r | |
81 | R7 = M3;\r | |
82 | \r | |
83 | R0 = B0;\r | |
84 | R1 = B1;\r | |
85 | R2 = B2;\r | |
86 | R3 = B3;\r | |
87 | R4 = L0;\r | |
88 | R5 = L1;\r | |
89 | R6 = L2;\r | |
90 | R7 = L3;\r | |
91 | \r | |
92 | P0 = I0;\r | |
93 | P1 = I1;\r | |
94 | P2 = I2;\r | |
95 | P3 = I3;\r | |
96 | P4 = M0;\r | |
97 | P5 = M1;\r | |
98 | SP = M2;\r | |
99 | FP = M3;\r | |
100 | \r | |
101 | P0 = B0;\r | |
102 | P1 = B1;\r | |
103 | P2 = B2;\r | |
104 | P3 = B3;\r | |
105 | P4 = L0;\r | |
106 | P5 = L1;\r | |
107 | SP = L2;\r | |
108 | FP = L3;\r | |
109 | \r | |
110 | \r | |
111 | A0.X = I0;\r | |
112 | A0.W = I1;\r | |
113 | A1.X = I2;\r | |
114 | A1.W = I3;\r | |
115 | \r | |
116 | A0.X = M0;\r | |
117 | A0.W = M1;\r | |
118 | A1.X = M2;\r | |
119 | A1.W = M3;\r | |
120 | \r | |
121 | A0.X = B0;\r | |
122 | A0.W = B1;\r | |
123 | A1.X = B2;\r | |
124 | A1.W = B3;\r | |
125 | \r | |
126 | A0.X = L0;\r | |
127 | A0.W = L1;\r | |
128 | A1.X = L2;\r | |
129 | A1.W = L3;\r | |
130 | \r | |
131 | //dagreg = genreg ; /* (a) */\r | |
132 | I0 = R0;\r | |
133 | I1 = P0;\r | |
134 | I2 = SP;\r | |
135 | I3 = FP;\r | |
136 | I0 = A0.X;\r | |
137 | I1 = A0.W;\r | |
138 | I2 = A1.X;\r | |
139 | I3 = A1.W;\r | |
140 | \r | |
141 | M0 = R0;\r | |
142 | M1 = P0;\r | |
143 | M2 = SP;\r | |
144 | M3 = FP;\r | |
145 | M0 = A0.X;\r | |
146 | M1 = A0.W;\r | |
147 | M2 = A1.X;\r | |
148 | M3 = A1.W;\r | |
149 | \r | |
150 | B0 = R0;\r | |
151 | B1 = P0;\r | |
152 | B2 = SP;\r | |
153 | B3 = FP;\r | |
154 | B0 = A0.X;\r | |
155 | B1 = A0.W;\r | |
156 | B2 = A1.X;\r | |
157 | B3 = A1.W;\r | |
158 | \r | |
159 | L0 = R0;\r | |
160 | L1 = P0;\r | |
161 | L2 = SP;\r | |
162 | L3 = FP;\r | |
163 | L0 = A0.X;\r | |
164 | L1 = A0.W;\r | |
165 | L2 = A1.X;\r | |
166 | L3 = A1.W;\r | |
167 | \r | |
168 | \r | |
169 | //dagreg = dagreg ; /* (a) */\r | |
170 | \r | |
171 | I0 = I1;\r | |
172 | I1 = M0;\r | |
173 | I2 = B1;\r | |
174 | I3 = L0;\r | |
175 | \r | |
176 | M0 = I1;\r | |
177 | M1 = M0;\r | |
178 | M2 = B1;\r | |
179 | M3 = L0;\r | |
180 | \r | |
181 | B0 = I1;\r | |
182 | B1 = M0;\r | |
183 | B2 = B1;\r | |
184 | B3 = L0;\r | |
185 | \r | |
186 | L0 = I1;\r | |
187 | L1 = M0;\r | |
188 | L2 = B1;\r | |
189 | L3 = L0;\r | |
190 | \r | |
191 | //genreg = USP ; /* (a)*/\r | |
192 | R1 = USP;\r | |
193 | P2 = USP;\r | |
194 | SP = USP;\r | |
195 | FP = USP;\r | |
196 | A0.X = USP;\r | |
197 | A1.W = USP;\r | |
198 | \r | |
199 | //USP = genreg ; /* (a)*/\r | |
200 | USP = R2;\r | |
201 | USP = P4;\r | |
202 | USP = SP;\r | |
203 | USP = FP;\r | |
204 | USP = A0.X;\r | |
205 | USP = A1.W;\r | |
206 | \r | |
207 | //Dreg = sysreg ; /* sysreg to 32-bit D-register (a) */\r | |
208 | R0 = ASTAT;\r | |
209 | R1 = SEQSTAT;\r | |
210 | R2 = SYSCFG;\r | |
211 | R3 = RETI;\r | |
212 | R4 = RETX;\r | |
213 | R5 = RETN;\r | |
214 | R6 = RETE;\r | |
215 | R7 = RETS;\r | |
216 | R0 = LC0;\r | |
217 | R1 = LC1;\r | |
218 | R2 = LT0;\r | |
219 | R3 = LT1;\r | |
220 | R4 = LB0;\r | |
221 | R5 = LB1;\r | |
222 | R6 = CYCLES;\r | |
223 | R7 = CYCLES2;\r | |
224 | //R0 = EMUDAT; \r | |
225 | //sysreg = Dreg ; /* 32-bit D-register to sysreg (a) */\r | |
226 | ASTAT = R0;\r | |
227 | SEQSTAT = R1;\r | |
228 | SYSCFG = R3;\r | |
229 | RETI = R4;\r | |
230 | RETX =R5;\r | |
231 | RETN = R6;\r | |
232 | RETE = R7;\r | |
233 | RETS = R0;\r | |
234 | LC0 = R1;\r | |
235 | LC1 = R2;\r | |
236 | LT0 = R3;\r | |
237 | LT1 = R4;\r | |
238 | LB0 = R5;\r | |
239 | LB1 = R6;\r | |
240 | CYCLES = R7;\r | |
241 | CYCLES2 = R0;\r | |
242 | //EMUDAT = R1; \r | |
243 | //sysreg = Preg ; /* 32-bit P-register to sysreg (a) */\r | |
244 | ASTAT = P0;\r | |
245 | SEQSTAT = P1;\r | |
246 | SYSCFG = P3;\r | |
247 | RETI = P4;\r | |
248 | RETX =P5;\r | |
249 | RETN = SP;\r | |
250 | RETE = FP;\r | |
251 | RETS = P0;\r | |
252 | LC0 = P1;\r | |
253 | LC1 = P2;\r | |
254 | LT0 = P3;\r | |
255 | LT1 = P4;\r | |
256 | LB0 = P5;\r | |
257 | LB1 = SP;\r | |
258 | CYCLES = SP;\r | |
259 | CYCLES2 = P0;\r | |
260 | //EMUDAT = P1; \r | |
261 | \r | |
262 | \r | |
263 | //sysreg = USP ; /* (a) */\r | |
264 | //ASTAT = USP;\r | |
265 | //SEQSTAT = USP;\r | |
266 | //SYSCFG = USP;\r | |
267 | //RETI = USP;\r | |
268 | //RETX =USP;\r | |
269 | //RETN = USP;\r | |
270 | //RETE = USP;\r | |
271 | //RETS = USP;\r | |
272 | //LC0 = USP;\r | |
273 | //LC1 = USP;\r | |
274 | //LT0 = USP;\r | |
275 | //LT1 = USP;\r | |
276 | //LB0 = USP;\r | |
277 | //LB1 = USP;\r | |
278 | //CYCLES = USP;\r | |
279 | //CYCLES2 = USP;\r | |
280 | //EMUDAT = USP; \r | |
281 | \r | |
282 | A0 = A1 ; /* move 40-bit Accumulator value (b) */\r | |
283 | \r | |
284 | A1 = A0 ; /* move 40-bit Accumulator value (b) */\r | |
285 | \r | |
286 | //A0 = Dreg ; /* 32-bit D-register to 40-bit A0, sign extended (b)*/\r | |
287 | A0 = R0;\r | |
288 | A0 = R1;\r | |
289 | A0 = R2;\r | |
290 | \r | |
291 | //A1 = Dreg ; /* 32-bit D-register to 40-bit A1, sign extended (b)*/\r | |
292 | \r | |
293 | A1 = R0;\r | |
294 | A1 = R1;\r | |
295 | A1 = R2;\r | |
296 | //Dreg_even = A0 (opt_mode) ; /* move 32-bit A0.W to even Dreg (b) */\r | |
297 | R0 = A0;\r | |
298 | R2 = A0(FU);\r | |
299 | R4 = A0(ISS2);\r | |
300 | \r | |
301 | //Dreg_odd = A1 (opt_mode) ; /* move 32-bit A1.W to odd Dreg (b) */\r | |
302 | R1 = A1;\r | |
303 | R3 = A1(FU);\r | |
304 | R5 = A1(ISS2);\r | |
305 | \r | |
306 | //Dreg_even = A0, Dreg_odd = A1 (opt_mode) ; /* move both Accumulators to a register pair (b) */\r | |
307 | R0 = A0, R1 = A1;\r | |
308 | R0 = A0, R1 = A1(FU);\r | |
309 | R6 = A0, R7 = A1(ISS2);\r | |
310 | \r | |
311 | \r | |
312 | //Dreg_odd = A1, Dreg_even = A0 (opt_mode) ; /* move both Accumulators to a register pair (b) */\r | |
313 | R1 = A1, R0 = A0;\r | |
314 | R3 = A1, R2 = A0(FU);\r | |
315 | R5 = A1, R4 = A0(ISS2);\r | |
316 | \r | |
317 | //IF CC DPreg = DPreg ; /* move if CC = 1 (a) */\r | |
318 | \r | |
319 | IF CC R3 = R0;\r | |
320 | IF CC R2 = R0;\r | |
321 | IF CC R7 = R0;\r | |
322 | \r | |
323 | IF CC R2 = P2;\r | |
324 | IF CC R4 = P1;\r | |
325 | IF CC R0 = P0;\r | |
326 | IF CC R7 = P4;\r | |
327 | \r | |
328 | IF CC P0 = P2;\r | |
329 | IF CC P4 = P5;\r | |
330 | IF CC P1 = P3;\r | |
331 | IF CC P5 = P4;\r | |
332 | \r | |
333 | IF CC P0 = R2;\r | |
334 | IF CC P4 = R3;\r | |
335 | IF CC P5 = R7;\r | |
336 | IF CC P2 = R6;\r | |
337 | \r | |
338 | //IF ! CC DPreg = DPreg ; /* move if CC = 0 (a) */\r | |
339 | IF !CC R3 = R0;\r | |
340 | IF !CC R2 = R0;\r | |
341 | IF !CC R7 = R0;\r | |
342 | \r | |
343 | IF !CC R2 = P2;\r | |
344 | IF !CC R4 = P1;\r | |
345 | IF !CC R0 = P0;\r | |
346 | IF !CC R7 = P4;\r | |
347 | \r | |
348 | IF !CC P0 = P2;\r | |
349 | IF !CC P4 = P5;\r | |
350 | IF !CC P1 = P3;\r | |
351 | IF !CC P5 = P4;\r | |
352 | \r | |
353 | IF !CC P0 = R2;\r | |
354 | IF !CC P4 = R3;\r | |
355 | IF !CC P5 = R7;\r | |
356 | IF !CC P2 = R6;\r | |
357 | \r | |
358 | //Dreg = Dreg_lo (Z) ; /* (a) */\r | |
359 | \r | |
360 | R0 = R0.L(Z);\r | |
361 | R2 = R1.L(Z);\r | |
362 | R1 = R2.L(Z);\r | |
363 | R7 = R6.L(Z);\r | |
364 | \r | |
365 | //Dreg = Dreg_lo (X) ; /* (a)*/\r | |
366 | R0 = R0.L(X);\r | |
367 | R2 = R1.L(X);\r | |
368 | R1 = R2.L(X);\r | |
369 | R7 = R6.L(X);\r | |
370 | \r | |
371 | R0 = R0.L;\r | |
372 | R2 = R1.L;\r | |
373 | R1 = R2.L;\r | |
374 | R7 = R6.L;\r | |
375 | \r | |
376 | //A0.X = Dreg_lo ; /* least significant 8 bits of Dreg into A0.X (b) */\r | |
377 | A0.X = R0.L;\r | |
378 | A0.X = R1.L;\r | |
379 | \r | |
380 | //A1.X = Dreg_lo ; /* least significant 8 bits of Dreg into A1.X (b) */\r | |
381 | A1.X = R0.L;\r | |
382 | A1.X = R1.L;\r | |
383 | \r | |
384 | //Dreg_lo = A0.X ; /* 8-bit A0.X, sign-extended, into least significant 16 bits of Dreg (b) */\r | |
385 | R0.L = A0.X;\r | |
386 | R1.L = A0.X;\r | |
387 | R7.L = A0.X;\r | |
388 | \r | |
389 | //Dreg_lo = A1.X ; /* 8-bit A1.X, sign-extended, into least significant 16 bits of Dreg (b) */\r | |
390 | R0.L = A1.X;\r | |
391 | R1.L = A1.X;\r | |
392 | R7.L = A1.X;\r | |
393 | \r | |
394 | //A0.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A0.W (b) */\r | |
395 | A0.L = R0.L;\r | |
396 | A0.L = R1.L;\r | |
397 | A0.L = R6.L;\r | |
398 | \r | |
399 | //A1.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A1.W (b) */\r | |
400 | A1.L = R0.L;\r | |
401 | A1.L = R1.L;\r | |
402 | A1.L = R6.L;\r | |
403 | \r | |
404 | //A0.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A0.W (b) */\r | |
405 | A0.H = R0.H;\r | |
406 | A0.H = R1.H;\r | |
407 | A0.H = R6.H;\r | |
408 | //A1.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A1.W (b) */\r | |
409 | A1.H = R0.H;\r | |
410 | A1.H = R1.H;\r | |
411 | A1.H = R6.H;\r | |
412 | \r | |
413 | //Dreg_lo = A0 (opt_mode) ; /* move A0 to lower half of Dreg (b) */\r | |
414 | R0.L = A0;\r | |
415 | R1.L = A0;\r | |
416 | \r | |
417 | R0.L = A0(FU);\r | |
418 | R1.L = A0(FU);\r | |
419 | \r | |
420 | R0.L = A0(IS);\r | |
421 | R1.L = A0(IS);\r | |
422 | \r | |
423 | R0.L = A0(IU);\r | |
424 | R1.L = A0(IU);\r | |
425 | \r | |
426 | R0.L = A0(T);\r | |
427 | R1.L = A0(T);\r | |
428 | \r | |
429 | R0.L = A0(S2RND);\r | |
430 | R1.L = A0(S2RND);\r | |
431 | \r | |
432 | R0.L = A0(ISS2);\r | |
433 | R1.L = A0(ISS2);\r | |
434 | \r | |
435 | R0.L = A0(IH);\r | |
436 | R1.L = A0(IH);\r | |
437 | \r | |
438 | //Dreg_hi = A1 (opt_mode) ; /* move A1 to upper half of Dreg (b) */\r | |
439 | R0.H = A1;\r | |
440 | R1.H = A1;\r | |
441 | \r | |
442 | R0.H = A1(FU);\r | |
443 | R1.H = A1(FU);\r | |
444 | \r | |
445 | R0.H = A1(IS);\r | |
446 | R1.H = A1(IS);\r | |
447 | \r | |
448 | R0.H = A1(IU);\r | |
449 | R1.H = A1(IU);\r | |
450 | \r | |
451 | R0.H = A1(T);\r | |
452 | R1.H = A1(T);\r | |
453 | \r | |
454 | R0.H = A1(S2RND);\r | |
455 | R1.H = A1(S2RND);\r | |
456 | \r | |
457 | R0.H = A1(ISS2);\r | |
458 | R1.H = A1(ISS2);\r | |
459 | \r | |
460 | R0.H = A1(IH);\r | |
461 | R1.H = A1(IH);\r | |
462 | \r | |
463 | \r | |
464 | //Dreg_lo = A0, Dreg_hi = A1 (opt_mode) ; /* move both values at once; must go to the lower and upper halves of the same Dreg (b)*/\r | |
465 | \r | |
466 | R0.L = A0, R0.H = A1; \r | |
467 | R1.L = A0, R1.H = A1; \r | |
468 | \r | |
469 | R0.L = A0, R0.H = A1(FU); \r | |
470 | R1.L = A0, R1.H = A1(FU);\r | |
471 | \r | |
472 | R0.L = A0, R0.H = A1(IS); \r | |
473 | R1.L = A0, R1.H = A1(IS);\r | |
474 | \r | |
475 | R0.L = A0, R0.H = A1(IU); \r | |
476 | R1.L = A0, R1.H = A1(IU);\r | |
477 | \r | |
478 | R0.L = A0, R0.H = A1(T); \r | |
479 | R1.L = A0, R1.H = A1(T);\r | |
480 | \r | |
481 | R0.L = A0, R0.H = A1(S2RND); \r | |
482 | R1.L = A0, R1.H = A1(S2RND);\r | |
483 | \r | |
484 | R0.L = A0, R0.H = A1(ISS2); \r | |
485 | R1.L = A0, R1.H = A1(ISS2);\r | |
486 | \r | |
487 | R0.L = A0, R0.H = A1(IH); \r | |
488 | R1.L = A0, R1.H = A1(IH);\r | |
489 | \r | |
490 | //Dreg_hi = A1, Dreg_lo = AO (opt_mode) ; /* move both values at once; must go to the upper and lower halves of the same Dreg (b) */\r | |
491 | \r | |
492 | R0.H = A1,R0.L = A0; \r | |
493 | R1.H = A1,R1.L = A0; \r | |
494 | \r | |
495 | R0.H = A1,R0.L = A0 (FU); \r | |
496 | R1.H = A1,R1.L = A0 (FU);\r | |
497 | \r | |
498 | R0.H = A1,R0.L = A0 (IS); \r | |
499 | R1.H = A1,R1.L = A0 (IS);\r | |
500 | \r | |
501 | R0.H = A1,R0.L = A0 (IU); \r | |
502 | R1.H = A1,R1.L = A0 (IU);\r | |
503 | \r | |
504 | R0.H = A1,R0.L = A0 (T); \r | |
505 | R1.H = A1,R1.L = A0 (T);\r | |
506 | \r | |
507 | R0.H = A1,R0.L = A0 (S2RND); \r | |
508 | R1.H = A1,R1.L = A0 (S2RND);\r | |
509 | \r | |
510 | R0.H = A1,R0.L = A0 (ISS2); \r | |
511 | R1.H = A1,R1.L = A0 (ISS2);\r | |
512 | \r | |
513 | R0.H = A1,R0.L = A0 (IH); \r | |
514 | R1.H = A1,R1.L = A0 (IH);\r | |
515 | \r | |
516 | //Dreg = Dreg_byte (Z) ; /* (a)*/\r | |
517 | \r | |
518 | R0 = R1.B(Z);\r | |
519 | R0 = R2.B(Z);\r | |
520 | \r | |
521 | R7 = R1.B(Z);\r | |
522 | R7 = R2.B(Z);\r | |
523 | \r | |
524 | //Dreg = Dreg_byte (X) ; /* (a) */\r | |
525 | R0 = R1.B(X);\r | |
526 | R0 = R2.B(X);\r | |
527 | \r | |
528 | R7 = R1.B(X);\r | |
529 | R7 = R2.B(X);\r | |
530 | \r |