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* gas/bfin/flow2.d: Match changed assembler behaviour.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / bfin / shift2.s
CommitLineData
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CM		 1\r
2.EXTERN MY_LABEL2;\r
3.section .text;\r
4\r
5//\r
6//9 SHIFT/ROTATE OPERATIONS\r
7//\r
8\r
9//Preg = ( Preg + Preg ) << 1 ; /* dest_reg = (dest_reg + src_reg) x 2 (a) */\r
10P0 = (P0+P0)<<1;\r
11P0 = (P0+P1)<<1;\r
12P2 = (P2+P0)<<1;\r
13P1 = (P1+P2)<<1;\r
14\r
15//P0 = (P2+P0)<<1;\r
16\r
17//Preg = ( Preg + Preg ) << 2 ; /* dest_reg = (dest_reg + src_reg) x 4 (a) */\r
18P0 = (P0+P0)<<2;\r
19P0 = (P0+P1)<<2;\r
20P2 = (P2+P0)<<2;\r
21P1 = (P1+P2)<<2;\r
22\r
23//P0 = (P2+P0)<<2;\r
24\r
25//Dreg = (Dreg + Dreg) << 1 ; /* dest_reg = (dest_reg + src_reg) x 2 (a) */\r
26R0 = (R0+R0)<<1;\r
27R0 = (R0+R1)<<1;\r
28R2 = (R2+R0)<<1;\r
29R1 = (R1+R2)<<1;\r
30\r
31//R0 = (R2+R0)<<1;\r
32\r
33\r
34//Dreg = (Dreg + Dreg) << 2 ; /* dest_reg = (dest_reg + src_reg) x 4 (a) */\r
35R0 = (R0+R0)<<2;\r
36R0 = (R0+R1)<<2;\r
37R2 = (R2+R0)<<2;\r
38R1 = (R1+R2)<<2;\r
39\r
40//R0 = (R2+R0)<<2;\r
41\r
42//Preg = Preg + ( Preg << 1 ) ; /* adder_pntr + (src_pntr x 2) (a) */\r
43P0 = P0 + (P0 << 1);\r
44P0 = P0 + (P1 << 1);\r
45P0 = P0 + (P2 << 1);\r
46P0 = P1 + (P2 << 1);\r
47P0 = P2 + (P3 << 1);\r
48P1 = P0 + (P0 << 1);\r
49P1 = P0 + (P1 << 1);\r
50P1 = P0 + (P2 << 1);\r
51P1 = P1 + (P2 << 1);\r
52P1 = P2 + (P3 << 1);\r
53\r
54//Preg = Preg + ( Preg << 2 ) ; /* adder_pntr + (src_pntr x 4) (a) */\r
55P0 = P0 + (P0 << 2);\r
56P0 = P0 + (P1 << 2);\r
57P0 = P0 + (P2 << 2);\r
58P0 = P1 + (P2 << 2);\r
59P0 = P2 + (P3 << 2);\r
60P1 = P0 + (P0 << 2);\r
61P1 = P0 + (P1 << 2);\r
62P1 = P0 + (P2 << 2);\r
63P1 = P1 + (P2 << 2);\r
64P1 = P2 + (P3 << 2);\r
65\r
66//Dreg >>>= uimm5 ; /* arithmetic right shift (a) */\r
67R0 >>>= 0;\r
68R0 >>>= 31;\r
69R0 >>>= 5;\r
70R5 >>>= 0;\r
71R5 >>>= 31;\r
72R5 >>>= 5;\r
73\r
74//Dreg <<= uimm5 ; /* logical left shift (a) */\r
75R0 <<= 0;\r
76R0 <<= 31;\r
77R0 <<= 5;\r
78R5 <<= 0;\r
79R5 <<= 31;\r
80R5 <<= 5;\r
81//Dreg_lo_hi = Dreg_lo_hi >>> uimm4 ; /* arithmetic right shift (b) */\r
82R0.L = R0.L >>> 0;\r
83R0.L = R0.L >>> 15;\r
84R0.L = R0.H >>> 0;\r
85R0.L = R0.H >>> 15;\r
86R0.H = R0.L >>> 0;\r
87R0.H = R0.L >>> 15;\r
88R0.H = R0.H >>> 0;\r
89R0.H = R0.H >>> 15;\r
90\r
91R0.L = R1.L >>> 0;\r
92R0.L = R1.L >>> 15;\r
93R0.L = R1.H >>> 0;\r
94R0.L = R1.H >>> 15;\r
95R0.H = R1.L >>> 0;\r
96R0.H = R1.L >>> 15;\r
97R0.H = R1.H >>> 0;\r
98R0.H = R1.H >>> 15;\r
99\r
100R0.L = R7.L >>> 0;\r
101R1.L = R6.L >>> 15;\r
102R2.L = R5.H >>> 0;\r
103R3.L = R4.H >>> 15;\r
104R4.H = R3.L >>> 0;\r
105R5.H = R2.L >>> 15;\r
106R6.H = R1.H >>> 0;\r
107R7.H = R0.H >>> 15;\r
108\r
109//Dreg_lo_hi = Dreg_lo_hi << uimm4 (S) ; /* arithmetic left shift (b) */\r
110R0.L = R0.L << 0(S);\r
111R0.L = R0.L << 15(S);\r
112R0.L = R0.H << 0(S);\r
113R0.L = R0.H << 15(S);\r
114R0.H = R0.L << 0(S);\r
115R0.H = R0.L << 15(S);\r
116R0.H = R0.H << 0(S);\r
117R0.H = R0.H << 15(S);\r
118\r
119R0.L = R1.L << 0(S);\r
120R0.L = R1.L << 15(S);\r
121R0.L = R1.H << 0(S);\r
122R0.L = R1.H << 15(S);\r
123R0.H = R1.L << 0(S);\r
124R0.H = R1.L << 15(S);\r
125R0.H = R1.H << 0(S);\r
126R0.H = R1.H << 15(S);\r
127\r
128R0.L = R7.L << 0(S);\r
129R1.L = R6.L << 15(S);\r
130R2.L = R5.H << 0(S);\r
131R3.L = R4.H << 15(S);\r
132R4.H = R3.L << 0(S);\r
133R5.H = R2.L << 15(S);\r
134R6.H = R1.H << 0(S);\r
135R7.H = R0.H << 15(S);\r
136//Dreg = Dreg >>> uimm5 ; /* arithmetic right shift (b) */\r
137R0 = R0 >>> 0;\r
138R0 = R0 >>> 31;\r
139R0 = R1 >>> 0;\r
140R0 = R1 >>> 31;\r
141R7 = R0 >>> 0;\r
142R6 = R1 >>> 31;\r
143R5 = R2 >>> 0;\r
144R4 = R3 >>> 31;\r
145R3 = R4 >>> 0;\r
146R2 = R5 >>> 31;\r
147R1 = R6 >>> 0;\r
148R0 = R7 >>> 31;\r
149\r
150//Dreg = Dreg << uimm5 (S) ; /* arithmetic left shift (b) */\r
151R0 = R0 << 0(S);\r
152R0 = R0 << 31(S);\r
153R0 = R1 << 0(S);\r
154R0 = R1 << 31(S);\r
155R7 = R0 << 0(S);\r
156R6 = R1 << 31(S);\r
157R5 = R2 << 0(S);\r
158R4 = R3 << 31(S);\r
159R3 = R4 << 0(S);\r
160R2 = R5 << 31(S);\r
161R1 = R6 << 0(S);\r
162R0 = R7 << 31(S);\r
163//A0 = A0 >>> uimm5 ; /* arithmetic right shift (b) */\r
164A0 = A0 >>> 0;\r
165A0 = A0 >>> 15;\r
166A0 = A0 >>> 31;\r
167\r
168//A0 = A0 << uimm5 ; /* logical left shift (b) */\r
169A0 = A0 << 0;\r
170A0 = A0 << 15;\r
171A0 = A0 << 31;\r
172\r
173//A1 = A1 >>> uimm5 ; /* arithmetic right shift (b) */\r
174A1 = A1 >>> 0;\r
175A1 = A1 >>> 15;\r
176A1 = A1 >>> 31;\r
177\r
178//A1 = A1 << uimm5 ; /* logical left shift (b) */\r
179A1 = A1 << 0;\r
180A1 = A1 << 15;\r
181A1 = A1 << 31;\r
182\r
183//Dreg >>>= Dreg ; /* arithmetic right shift (a) */\r
184R0 >>>= R0;\r
185R0 >>>= R1;\r
186R1 >>>= R0;\r
187R1 >>>= R7;\r
188\r
189//Dreg <<= Dreg ; /* logical left shift (a) */\r
190R0 <<= R0;\r
191R0 <<= R1;\r
192R1 <<= R0;\r
193R1 <<= R7;\r
194\r
195//Dreg_lo_hi = ASHIFT Dreg_lo_hi BY Dreg_lo (opt_sat) ; /* arithmetic right shift (b) */\r
196r3.l = ashift r0.h by r7.l ; /* shift, half-word */\r
197r3.h = ashift r0.l by r7.l ;\r
198r3.h = ashift r0.h by r7.l ;\r
199r3.l = ashift r0.l by r7.l ;\r
200r3.l = ashift r0.h by r7.l(s) ; /* shift, half-word, saturated */\r
201r3.h = ashift r0.l by r7.l(s) ; /* shift, half-word, saturated */\r
202r3.h = ashift r0.h by r7.l(s) ;\r
203r3.l = ashift r0.l by r7.l (s) ;\r
204\r
205//Dreg = ASHIFT Dreg BY Dreg_lo (opt_sat) ; /* arithmetic right shift (b) */\r
206r4 = ashift r2 by r7.l ; /* shift, word */\r
207r4 = ashift r2 by r7.l (s) ; /* shift, word, saturated */\r
208\r
209//A0 = ASHIFT A0 BY Dreg_lo ; /* arithmetic right shift (b)*/\r
210A0 = ashift A0 by r7.l ; /* shift, Accumulator */\r
211\r
212//A1 = ASHIFT A1 BY Dreg_lo ; /* arithmetic right shift (b)*/\r
213A1 = ashift A1 by r7.l ; /* shift, Accumulator */\r
214\r
215p3 = p2 >> 1 ; /* pointer right shift by 1 */\r
216p3 = p3 >> 2 ; /* pointer right shift by 2 */\r
217p4 = p5 << 1 ; /* pointer left shift by 1 */\r
218p0 = p1 << 2 ; /* pointer left shift by 2 */\r
219r3 >>= 17 ; /* data right shift */\r
220r3 <<= 17 ; /* data left shift */\r
221r3.l = r0.l >> 4 ; /* data right shift, half-word register */\r
222r3.l = r0.h >> 4 ; /* same as above; half-word register combinations are arbitrary */\r
223r3.h = r0.l << 12 ; /* data left shift, half-word register */\r
224r3.h = r0.h << 14 ; /* same as above; half-word register combinations are arbitrary */\r
225\r
226r3 = r6 >> 4 ; /* right shift, 32-bit word */\r
227r3 = r6 << 4 ; /* left shift, 32-bit word */\r
228\r
229a0 = a0 >> 7 ; /* Accumulator right shift */\r
230a1 = a1 >> 25 ; /* Accumulator right shift */\r
231a0 = a0 << 7 ; /* Accumulator left shift */\r
232a1 = a1 << 14 ; /* Accumulator left shift */\r
233\r
234r3 >>= r0 ; /* data right shift */\r
235r3 <<= r1 ; /* data left shift */\r
236\r
237r3.l = lshift r0.l by r2.l ; /* shift direction controlled by sign of R2.L */\r
238r3.h = lshift r0.l by r2.l ;\r
239\r
240a0 = lshift a0 by r7.l ;\r
241a1 = lshift a1 by r7.l ;\r
242\r
243r4 = rot r1 by 31 ; /* rotate left */\r
244r4 = rot r1 by -32 ; /* rotate right */\r
245r4 = rot r1 by 5 ; /* rotate right */\r
246\r
247a0 = rot a0 by 22 ; /* rotate Accumulator left */\r
248a0 = rot a0 by -32 ; /* rotate Accumulator left */\r
249a0 = rot a0 by 31 ; /* rotate Accumulator left */\r
250\r
251a1 = rot a1 by -32 ; /* rotate Accumulator right */\r
252a1 = rot a1 by 31 ; /* rotate Accumulator right */\r
253a1 = rot a1 by 22 ; /* rotate Accumulator right */\r
254\r
255r4 = rot r1 by r2.l ;\r
256a0 = rot a0 by r3.l ;\r
257a1 = rot a1 by r7.l ;\r
258\r
GDB Binutils - Deliverables
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