projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 8df55cb8 CM |
1 | \r |
| 2 | .EXTERN MY_LABEL2;\r | |
| 3 | .section .text;\r | |
| 4 | \r | |
| 5 | //\r | |
| 6 | //5 STACK CONTROL\r | |
| 7 | //\r | |
| 8 | \r | |
| 9 | //[ -- SP ] = allreg ; /* predecrement SP (a) */\r | |
| 10 | \r | |
| 11 | [--SP ] = R0;\r | |
| 12 | [--SP ] = R6;\r | |
| 13 | \r | |
| 14 | [--SP ] = P0;\r | |
| 15 | [--SP ] = P4;\r | |
| 16 | \r | |
| 17 | [--SP ] = I0;\r | |
| 18 | [--SP ] = I1;\r | |
| 19 | \r | |
| 20 | [--SP ] = M0;\r | |
| 21 | [--SP ] = M1;\r | |
| 22 | \r | |
| 23 | [--SP ] = L0;\r | |
| 24 | [--SP ] = L1;\r | |
| 25 | \r | |
| 26 | [--SP ] = B0;\r | |
| 27 | [--SP ] = B1;\r | |
| 28 | \r | |
| 29 | [--SP ] = A0.X;\r | |
| 30 | [--SP ] = A1.X;\r | |
| 31 | \r | |
| 32 | [--SP ] = A0.W;\r | |
| 33 | [--SP ] = A1.W;\r | |
| 34 | \r | |
| 35 | [--SP ] = ASTAT;\r | |
| 36 | [--SP ] = RETS;\r | |
| 37 | [--SP ] = RETI;\r | |
| 38 | [--SP ] = RETX;\r | |
| 39 | [--SP ] = RETN;\r | |
| 40 | [--SP ] = RETE;\r | |
| 41 | [--SP ] = LC0;\r | |
| 42 | [--SP ] = LC1;\r | |
| 43 | [--SP ] = LT0;\r | |
| 44 | [--SP ] = LT1;\r | |
| 45 | [--SP ] = LB0;\r | |
| 46 | [--SP ] = LB1;\r | |
| 47 | [--SP ] = CYCLES;\r | |
| 48 | [--SP ] = CYCLES2;\r | |
| 49 | //[--SP ] = EMUDAT;\r | |
| 50 | [--SP ] = USP;\r | |
| 51 | [--SP ] = SEQSTAT;\r | |
| 52 | [--SP ] = SYSCFG;\r | |
| 53 | \r | |
| 54 | \r | |
| 55 | //[ -- SP ] = ( R7 : Dreglim , P5 : Preglim ) ; /* Dregs and indexed Pregs (a) */\r | |
| 56 | [--SP ] = ( R7:0, P5:0);\r | |
| 57 | \r | |
| 58 | \r | |
| 59 | //[ -- SP ] = ( R7 : Dreglim ) ; /* Dregs, only (a) */\r | |
| 60 | [--SP ] = ( R7:0);\r | |
| 61 | \r | |
| 62 | //[ -- SP ] = ( P5 : Preglim ) ; /* indexed Pregs, only (a) */\r | |
| 63 | [--SP ] = (P5:0);\r | |
| 64 | \r | |
| 65 | \r | |
| 66 | //mostreg = [ SP ++ ] ; /* post-increment SP; does not apply to Data Registers and Pointer Registers (a) */\r | |
| 67 | \r | |
| 68 | R0= [ SP ++ ] ; \r | |
| 69 | R6= [ SP ++ ] ; \r | |
| 70 | \r | |
| 71 | P0= [ SP ++ ] ; \r | |
| 72 | P4= [ SP ++ ] ; \r | |
| 73 | \r | |
| 74 | I0= [ SP ++ ] ; \r | |
| 75 | I1= [ SP ++ ] ; \r | |
| 76 | \r | |
| 77 | M0= [ SP ++ ] ; \r | |
| 78 | M1= [ SP ++ ] ; \r | |
| 79 | \r | |
| 80 | L0= [ SP ++ ] ; \r | |
| 81 | L1= [ SP ++ ] ; \r | |
| 82 | \r | |
| 83 | B0= [ SP ++ ] ; \r | |
| 84 | B1= [ SP ++ ] ; \r | |
| 85 | \r | |
| 86 | A0.X= [ SP ++ ] ; \r | |
| 87 | A1.X= [ SP ++ ] ; \r | |
| 88 | \r | |
| 89 | A0.W= [ SP ++ ] ; \r | |
| 90 | A1.W= [ SP ++ ] ; \r | |
| 91 | \r | |
| 92 | ASTAT= [ SP ++ ] ; \r | |
| 93 | RETS= [ SP ++ ] ; \r | |
| 94 | RETI= [ SP ++ ] ; \r | |
| 95 | RETX= [ SP ++ ] ; \r | |
| 96 | RETN= [ SP ++ ] ; \r | |
| 97 | RETE= [ SP ++ ] ; \r | |
| 98 | LC0= [ SP ++ ] ; \r | |
| 99 | LC1= [ SP ++ ] ; \r | |
| 100 | LT0= [ SP ++ ] ; \r | |
| 101 | LT1= [ SP ++ ] ; \r | |
| 102 | LB0= [ SP ++ ] ; \r | |
| 103 | LB1= [ SP ++ ] ; \r | |
| 104 | CYCLES= [ SP ++ ] ; \r | |
| 105 | CYCLES2= [ SP ++ ] ; \r | |
| 106 | //EMUDAT= [ SP ++ ] ; \r | |
| 107 | USP= [ SP ++ ] ; \r | |
| 108 | SEQSTAT= [ SP ++ ] ; \r | |
| 109 | SYSCFG= [ SP ++ ] ; \r | |
| 110 | \r | |
| 111 | //( R7 : Dreglim, P5 : Preglim ) = [ SP ++ ] ; /* Dregs and indexed Pregs (a) */\r | |
| 112 | ( R7:0, P5:0) = [ SP++ ];\r | |
| 113 | \r | |
| 114 | //( R7 : Dreglim ) = [ SP ++ ] ; /* Dregs, only (a) */\r | |
| 115 | ( R7:0) = [ SP++ ];\r | |
| 116 | \r | |
| 117 | //( P5 : Preglim ) = [ SP ++ ] ; /* indexed Pregs, only (a) */\r | |
| 118 | ( P5:0) = [ SP++ ];\r | |
| 119 | \r | |
| 120 | //LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */\r | |
| 121 | LINK 0X0;\r | |
| 122 | LINK 0X8;\r | |
| 123 | LINK 0x3FFFC;\r | |
| 124 | \r | |
| 125 | UNLINK ; /* de-allocate the stack frame (b)*/\r |