Commit | Line | Data |
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a9298102 JZ |
1 | |
2 | .EXTERN MY_LABEL2; | |
3 | .section .text; | |
4 | ||
5 | // | |
6 | //5 STACK CONTROL | |
7 | // | |
8 | ||
9 | //[ -- SP ] = allreg ; /* predecrement SP (a) */ | |
10 | ||
11 | [--SP ] = R0; | |
12 | [--SP ] = R6; | |
13 | ||
14 | [--SP ] = P0; | |
15 | [--SP ] = P4; | |
16 | ||
17 | [--SP ] = I0; | |
18 | [--SP ] = I1; | |
19 | ||
20 | [--SP ] = M0; | |
21 | [--SP ] = M1; | |
22 | ||
23 | [--SP ] = L0; | |
24 | [--SP ] = L1; | |
25 | ||
26 | [--SP ] = B0; | |
27 | [--SP ] = B1; | |
28 | ||
29 | [--SP ] = A0.X; | |
30 | [--SP ] = A1.X; | |
31 | ||
32 | [--SP ] = A0.W; | |
33 | [--SP ] = A1.W; | |
34 | ||
35 | [--SP ] = ASTAT; | |
36 | [--SP ] = RETS; | |
37 | [--SP ] = RETI; | |
38 | [--SP ] = RETX; | |
39 | [--SP ] = RETN; | |
40 | [--SP ] = RETE; | |
41 | [--SP ] = LC0; | |
42 | [--SP ] = LC1; | |
43 | [--SP ] = LT0; | |
44 | [--SP ] = LT1; | |
45 | [--SP ] = LB0; | |
46 | [--SP ] = LB1; | |
47 | [--SP ] = CYCLES; | |
48 | [--SP ] = CYCLES2; | |
49 | //[--SP ] = EMUDAT; | |
50 | [--SP ] = USP; | |
51 | [--SP ] = SEQSTAT; | |
52 | [--SP ] = SYSCFG; | |
53 | ||
54 | ||
55 | //[ -- SP ] = ( R7 : Dreglim , P5 : Preglim ) ; /* Dregs and indexed Pregs (a) */ | |
56 | [--SP ] = ( R7:0, P5:0); | |
57 | ||
58 | ||
59 | //[ -- SP ] = ( R7 : Dreglim ) ; /* Dregs, only (a) */ | |
60 | [--SP ] = ( R7:0); | |
61 | ||
62 | //[ -- SP ] = ( P5 : Preglim ) ; /* indexed Pregs, only (a) */ | |
63 | [--SP ] = (P5:0); | |
64 | ||
65 | ||
66 | //mostreg = [ SP ++ ] ; /* post-increment SP; does not apply to Data Registers and Pointer Registers (a) */ | |
67 | ||
68 | R0= [ SP ++ ] ; | |
69 | R6= [ SP ++ ] ; | |
70 | ||
71 | P0= [ SP ++ ] ; | |
72 | P4= [ SP ++ ] ; | |
73 | ||
74 | I0= [ SP ++ ] ; | |
75 | I1= [ SP ++ ] ; | |
76 | ||
77 | M0= [ SP ++ ] ; | |
78 | M1= [ SP ++ ] ; | |
79 | ||
80 | L0= [ SP ++ ] ; | |
81 | L1= [ SP ++ ] ; | |
82 | ||
83 | B0= [ SP ++ ] ; | |
84 | B1= [ SP ++ ] ; | |
85 | ||
86 | A0.X= [ SP ++ ] ; | |
87 | A1.X= [ SP ++ ] ; | |
88 | ||
89 | A0.W= [ SP ++ ] ; | |
90 | A1.W= [ SP ++ ] ; | |
91 | ||
92 | ASTAT= [ SP ++ ] ; | |
93 | RETS= [ SP ++ ] ; | |
94 | RETI= [ SP ++ ] ; | |
95 | RETX= [ SP ++ ] ; | |
96 | RETN= [ SP ++ ] ; | |
97 | RETE= [ SP ++ ] ; | |
98 | LC0= [ SP ++ ] ; | |
99 | LC1= [ SP ++ ] ; | |
100 | LT0= [ SP ++ ] ; | |
101 | LT1= [ SP ++ ] ; | |
102 | LB0= [ SP ++ ] ; | |
103 | LB1= [ SP ++ ] ; | |
104 | CYCLES= [ SP ++ ] ; | |
105 | CYCLES2= [ SP ++ ] ; | |
106 | //EMUDAT= [ SP ++ ] ; | |
107 | USP= [ SP ++ ] ; | |
108 | SEQSTAT= [ SP ++ ] ; | |
109 | SYSCFG= [ SP ++ ] ; | |
110 | ||
111 | //( R7 : Dreglim, P5 : Preglim ) = [ SP ++ ] ; /* Dregs and indexed Pregs (a) */ | |
112 | ( R7:0, P5:0) = [ SP++ ]; | |
113 | ||
114 | //( R7 : Dreglim ) = [ SP ++ ] ; /* Dregs, only (a) */ | |
115 | ( R7:0) = [ SP++ ]; | |
116 | ||
117 | //( P5 : Preglim ) = [ SP ++ ] ; /* indexed Pregs, only (a) */ | |
118 | ( P5:0) = [ SP++ ]; | |
119 | ||
120 | //LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */ | |
121 | LINK 0X0; | |
122 | LINK 0X8; | |
123 | LINK 0x3FFFC; | |
124 | ||
125 | UNLINK ; /* de-allocate the stack frame (b)*/ | |
5e8c8f8f JZ |
126 | |
127 | L$L$foo: (R7:6,P5:3) = [SP++]; /* Pop multiple on the same line with a label */ |