Add script to build and test GDB using enable-targets=all.

[deliverable/binutils-gdb.git] / gas / testsuite / gas / bfin / vector2.s

\r
.EXTERN MY_LABEL2;\r
.section .text;\r
\r
//\r
//14 VECTOR OPERATIONS\r
//\r
\r
//Dreg_hi = Dreg_lo = SIGN ( Dreg_hi ) * Dreg_hi + SIGN ( Dreg_lo ) * Dreg_lo ; /* (b) */\r
\r
r7.h=r7.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;\r
r0.h=r0.l=sign(r1.h)*r2.h+sign(r1.l)*r2.l ;\r
r3.h=r3.l=sign(r4.h)*r5.h+sign(r4.l)*r5.l ;\r
r6.h=r6.l=sign(r7.h)*r0.h+sign(r7.l)*r0.l ;\r
r1.h=r1.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;\r
r4.h=r4.l=sign(r5.h)*r6.h+sign(r5.l)*r6.l ;\r
r7.h=r7.l=sign(r0.h)*r1.h+sign(r0.l)*r1.l ;\r
r2.h=r2.l=sign(r3.h)*r4.h+sign(r3.l)*r4.l ;\r
\r
//Dual 16-Bit Operation\r
//Dreg = VIT_MAX ( Dreg , Dreg ) (ASL) ; /* shift history bits left (b) */\r
//Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */\r
//Single 16-Bit Operation\r
//Dreg_lo = VIT_MAX ( Dreg ) (ASL) ; /* shift history bits left (b) */\r
//Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */\r
r5 = vit_max(r3, r2)(asl) ; /* shift left, dual operation */\r
r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */\r
\r
r0 = vit_max(r1, r2)(asl) ; /* shift left, dual operation */\r
r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */\r
r6 = vit_max(r7, r0)(asl) ; /* shift left, dual operation */\r
r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */\r
r4 = vit_max(r5, r6)(asl) ; /* shift left, dual operation */\r
r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */\r
r2 = vit_max(r3, r4)(asl) ; /* shift left, dual operation */\r
r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */\r
\r
\r
r3.l = vit_max (r1)(asl) ; /* shift left, single operation */\r
r3.l = vit_max (r1)(asr) ; /* shift right, single operation */\r
\r
r0.l = vit_max (r1)(asl) ; /* shift left, single operation */\r
r2.l = vit_max (r3)(asr) ; /* shift right, single operation */\r
r4.l = vit_max (r5)(asl) ; /* shift left, single operation */\r
r6.l = vit_max (r7)(asr) ; /* shift right, single operation */\r
r1.l = vit_max (r2)(asl) ; /* shift left, single operation */\r
r3.l = vit_max (r4)(asr) ; /* shift right, single operation */\r
r5.l = vit_max (r6)(asl) ; /* shift left, single operation */\r
r7.l = vit_max (r0)(asr) ; /* shift right, single operation */\r
\r
//Dreg = ABS Dreg (V) ; /* (b) */\r
r3 = abs r1 (v) ;\r
\r
r0 = abs r0 (v) ;\r
r0 = abs r1 (v) ;\r
r2 = abs r3 (v) ;\r
r4 = abs r5 (v) ;\r
r6 = abs r7 (v) ;\r
r1 = abs r0 (v) ;\r
r3 = abs r2 (v) ;\r
r5 = abs r4 (v) ;\r
r7 = abs r6 (v) ;\r
\r
//Dual 16-Bit Operations\r
//Dreg = Dreg +|+ Dreg (opt_mode_0) ; /* add | add (b) */\r
r5=r3 +|+ r4 ; /* dual 16-bit operations, add|add */\r
\r
r0=r1 +|+ r2 ;\r
r3=r4 +|+ r5 ;\r
r6=r7 +|+ r0 ;\r
r1=r2 +|+ r3 ;\r
r4=r3 +|+ r5 ;\r
r6=r3 +|+ r7 ;\r
\r
r0=r1 +|+ r2 (S);\r
r3=r4 +|+ r5 (S);\r
r6=r7 +|+ r0 (S);\r
r1=r2 +|+ r3 (S);\r
r4=r3 +|+ r5 (S);\r
r6=r3 +|+ r7 (S);\r
\r
r0=r1 +|+ r2 (CO);\r
r3=r4 +|+ r5 (CO);\r
r6=r7 +|+ r0 (CO) ;\r
r1=r2 +|+ r3 (CO);\r
r4=r3 +|+ r5 (CO);\r
r6=r3 +|+ r7 (CO);\r
\r
r0=r1 +|+ r2 (SCO);\r
r3=r4 +|+ r5 (SCO);\r
r6=r7 +|+ r0 (SCO);\r
r1=r2 +|+ r3 (SCO);\r
r4=r3 +|+ r5 (SCO);\r
r6=r3 +|+ r7 (SCO);\r
\r